CN109857606A - Avoid the memory redundant digit test method and device of loss yield - Google Patents
Avoid the memory redundant digit test method and device of loss yield Download PDFInfo
- Publication number
- CN109857606A CN109857606A CN201910111971.6A CN201910111971A CN109857606A CN 109857606 A CN109857606 A CN 109857606A CN 201910111971 A CN201910111971 A CN 201910111971A CN 109857606 A CN109857606 A CN 109857606A
- Authority
- CN
- China
- Prior art keywords
- memory
- test
- target
- redundant digit
- avoiding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of memory redundant digit test method and device for avoiding loss yield, method is the following steps are included: test signal can be used by receiving；According to test signal can be used, partial test is carried out to target memory；Test result is obtained, judges whether target memory is qualified according to test result.By selectively being tested just for the available memory that target in memory uses, interference of the redundancy memory failure to test result is avoided, under the premise of guaranteeing does not influence use, improves testing efficiency, the yields of memory is improved simultaneously, reduces production cost.
Description
Technical field
The present invention relates to test methods, especially relate to a kind of memory redundancy bit test side for avoiding loss yield
Method and device.
Background technique
In circuit design process, since the performance of memory compiler limits, the memory size generated is not
The demand of user can be fully met, for the performance limitation for adapting to existing memory compiler, some memory meetings generated
Some row or columns are had more, but these parts can give it up again in actual function.
But in manufacturing defect screening process, if it is because the defect of these memory redundant digits occurs, entire core
Piece abandons, and it will cause unnecessary wastes, while reducing the yield of memory.
Summary of the invention
In order to solve the defect of the above-mentioned prior art, the object of the present invention is to provide a kind of memory for avoiding loss yield
Redundant digit test method and device.
In order to achieve the above objectives, the technical scheme is that
A kind of memory redundant digit test method avoiding loss yield, comprising the following steps:
Test signal can be used by receiving；
According to test signal can be used, partial test is carried out to target memory；
Test result is obtained, judges whether target memory is qualified according to test result.
Further, the basis can use test signal, before carrying out partial test step to target memory, including,
Redundancy memory is filtered out, using redundancy memory as non-test target, and using remaining memory as target
memory。
Further, described that partial test step is carried out to target memory, including,
Partial test is carried out to memory by BIST logic.
Further, described that partial test step is carried out to memory by BIST logic, including, reception can use test letter
The test address memory information in number；
Memory is tested according to test address.
The invention also provides a kind of memory redundant digit test devices for avoiding loss yield, comprising:
Signal receiving unit can use test signal for receiving；
Partial test unit, for carrying out partial test to target memory according to test signal can be used；
As a result acquiring unit judges whether target memory is qualified according to test result for obtaining test result.
It further, further include screening unit, the screening unit, for filtering out redundancy memory, by redundancy
Memory is as non-test target, and using remaining memory as target memory.
Further, the partial test unit is also used to carry out partial test to memory by BIST logic.
Further, the partial test unit, including address receiving module and test module,
The address receiving module can use the test address the memory information in test signal for receiving；
The test module, for being tested according to test address memory.
The beneficial effects of the present invention are: being kept away by being tested just for the available memory that target in memory uses
Interference of the redundancy memory failure to test result has been opened, under the premise of guaranteeing does not influence use, has improved memory test effect
Rate, while the yields of memory is improved, reduce production cost.
Detailed description of the invention
Fig. 1 is a kind of method flow diagram for the memory redundant digit test method for avoiding loss yield of the present invention；
Fig. 2 is a kind of step flow chart for carrying out partial test step to memory by BIST logic of the present invention；
Fig. 3 is conventional testing procedures figure；
Fig. 4 is the improved test process of the present invention；
Fig. 5 is a kind of structural block diagram for the memory redundant digit test device for avoiding loss yield of the present invention；
Fig. 6 is a kind of structural block diagram of partial test unit of the present invention.
Specific embodiment
To illustrate thought and purpose of the invention, the present invention is done further below in conjunction with the drawings and specific embodiments
Explanation.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiment is only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts it is all its
His embodiment, shall fall within the protection scope of the present invention.
It is to be appreciated that the directional instruction (up, down, left, right, before and after etc.) of institute is only used in the embodiment of the present invention
It explains in relative positional relationship, the motion conditions etc. under a certain particular pose (as shown in the picture) between each component, if the spy
When determining posture and changing, then directionality instruction also correspondingly changes correspondingly, and the connection, which can be, to be directly connected to, can also
To be to be indirectly connected with.
In addition, the description for being such as related to " first ", " second " in the present invention is used for description purposes only, and should not be understood as
Its relative importance of indication or suggestion or the quantity for implicitly indicating indicated technical characteristic.Define as a result, " first ",
The feature of " second " can explicitly or implicitly include at least one of the features.In addition, the technical side between each embodiment
Case can be combined with each other, but must be based on can be realized by those of ordinary skill in the art, when the combination of technical solution
Conflicting or cannot achieve when occur will be understood that the combination of this technical solution is not present, also not the present invention claims guarantor
Within the scope of shield.
Unless otherwise instructed, "/" herein represents meaning as "or".
Memory is used to a large amount of binary data for storing and reading and writing.By functionally classifying, it is big that two can be divided into substantially
Class: read-only memory (ROM) and random access memory (RAM).ROM can only be read, and cannot be write；RAM can read but also write.RAM
With volatibility.After power-off, the data that save in RAM are by whole loss；And the data in ROM can then save for a long time.
BIST is to be implanted into related functional circuits in circuit in design for providing the technology of selftest function, with this
Device detection is reduced to the degree of dependence of automatic test equipment (ATE).
Referring to Fig.1-4, one embodiment of the invention proposes a kind of memory redundant digit test method for avoiding loss yield,
The following steps are included:
S10, reception can use test signal.
S30, basis can use test signal, carry out partial test to target memory.
S40, test result is obtained, judges whether target memory is qualified according to test result.
For step S10, reception can use test signal, can use the physical address that target memory is carried in test signal,
According to that can directly can be tested available memory (target memory) with test signal, memory can be used by accurately understanding
Function it is whether normal, also, can use in test signal and not carry the physical address of redundancy memory, in actual test process
In, directly skip redundancy memory, detecting for differentiation be not added to the memory of full wafer, only to the memory used into
Row quickly test, improves testing efficiency.
For step S30, the physical address of memory can be used with target is carried in test signal, believed according to that can use to test
Number directly available memory can be tested, whether can with the function of memory normal, also, can be with surveying if accurately understanding
The physical address for not carrying redundancy memory in trial signal directly skips the redundancy memory during actual test, not right
The memory of full wafer is not added differentiation and detect, and is only quickly tested available memory, improves testing efficiency.?
Can be normal with the function of memory, and in the case that the function of redundancy memory goes wrong, full wafer memory can also be regarded
It for non-defective unit, rather than directly abandons as before, tests yield after improving, reduce production cost.
Specifically, step S30 includes step S31: carrying out partial test to memory by BIST logic.
Specifically, BIST logic is the built-in self-test algorithm logic of conventional memory defect test, due to it is this from
Test logic cannot arbitrarily change internal structure, while also need to only keep original conventional BIST logic structure, still be suitable for
Existing memory reduces testing cost without building a set of new test logical architecture again according to the present invention.It realizes and both adapted to
BIST logic is tested, but will not the part false retrieval redundancy memory purpose, existing line position sequence of partial sums position can be used
Part substitutes the line position sequence of partial sums bit position of redundant circuit.
The circuit DFT of the application is designed, and the demand of existing MemoryBIST test logic has both been adapted to, using practical use
Line position sequence of partial sums bit position to memory substitutes (the line position sequence of partial sums position portion comprising redundancy memory whole memory
Point) participate in MemoryBIST and carry out circuit realization, avoid because the part redundancy memory taken less than occur defect cause it is good
The problem of rate reduces.
With reference to Fig. 2, step S31 the following steps are included:
S311, reception can use the test address the memory information in test signal；
S312, memory is tested according to test address.
For step S311 and S312, the physical address of memory can be used with target is carried in test signal, that is,
The test address memory information, according to can directly can be surveyed to available memory with the address information that carries in test signal
Whether examination, accurately understanding can normal with the function of memory.Also, the object for not carrying redundancy memory in test signal can be used
Redundancy memory is directly skipped, examining for differentiation is not added to the memory of full wafer during actual test in reason address
It surveys, only available memory is quickly tested, improves testing efficiency.It is normal in the function of available memory, and redundancy
In the case that the function of memory goes wrong, also full wafer memory can be considered as non-defective unit, rather than as before directly
It abandons, tests yield after improving, reduce production cost.
Specifically, further including step S20 before step S30: redundancy memory is filtered out, using redundancy memory as non-
Test target, and using remaining memory as target memory.
For step S20, before test, redundancy memory is oriented according to the screening of the overall condition of memory, is left
Other as can use memory, subsequent carry out stress test, and redundancy memory is directly skipped during the test, without
Test, will not have an impact test result.
For step S40, after the completion of test, the test knot of full wafer memory can be just represented with the test result of memory
Whether fruit skips redundancy memory completely, go wrong regardless of redundancy memory, all do not interfere with available memory whether just
Often, therefore the test result of full wafer memory will not be influenced, helps to save chip cost, improves testing engineering efficiency.
This programme is avoided superfluous by selectively being tested just for the available memory that target in memory uses
Interference of the remaining memory failure to test result improves testing efficiency, improves simultaneously under the premise of guaranteeing does not influence use
The yields of memory reduces production cost.
It is a kind of concrete application for the memory redundant digit test method for avoiding loss yield of the present invention with reference to Fig. 3 and 4:
For example having a parameter in circuit is the memory of 132X32, wherein bit [31] is that redundancy is useless in function realization, bit
[30:0] be then it is useful, just bit [31] is out of joint in manufacturer's manufacturing process, accidentally abandon will cause the upper of production cost
It rises.
As shown in figure 3, conventional method is that testing for differentiation is not added to entire memory with memory BIST, input
bit[31:0].And as shown in figure 4, using the scheme of the invention is (superfluous using bit [30] (memory can be used) substitution bit [31]
Remaining memory) test is participated in, even if production occurs in bit in this way [31], defect can be also skipped, and will not generate fault cues, in turn
Avoid the appearance for accidentally abandoning situation.Specific processing method is: redundant digit bit [31] is found disconnection in BIST logic,
And this is signally attached on other any one bit, it can be any one position acted in the bit [30:0] used, than
Such as bit [30] or bit [28].
It refers to Figures 5 and 6, the invention also provides a kind of memory redundant digit test devices for avoiding loss yield, comprising:
Signal receiving unit 10 can use test signal for receiving；
Screening unit 20, for filtering out redundancy memory, using redundancy memory as non-test target, and by remaining
Memory is as target memory.
Partial test unit 30, for carrying out partial test to target memory according to test signal can be used；
As a result acquiring unit 40 judge whether target memory is qualified according to test result for obtaining test result.
For signal receiving unit 10, reception can use test signal, can use memory with target is carried in test signal
Physical address, according to can with test signal directly available memory can be tested, accurately understand can use memory
Function it is whether normal, also, can use in test signal and not carry the physical address of redundancy memory, in actual test process
In, directly skip redundancy memory, detecting for differentiation be not added to the memory of full wafer, only to the memory used into
Row quickly test, improves testing efficiency.
For screening unit 20, before test, redundancy memory is oriented according to the screening of the overall condition of memory, is remained
Under other as can use memory, subsequent carry out stress test, and redundancy memory is directly skipped during the test, not into
Row test, will not have an impact test result.
For partial test unit 30, the physical address of memory can be used with target is carried in test signal, according to can
Directly available memory can be tested with test signal, whether accurately understand can normal with the function of memory, and
And the redundancy can be directly skipped during actual test with the physical address for not carrying redundancy memory in test signal
Detecting for differentiation is not added to the memory of full wafer in memory, is only quickly tested available memory, is improved
Testing efficiency.Function in available memory is normal and in the case that the function of redundancy memory goes wrong, also can be whole by this
Piece memory is considered as non-defective unit, rather than directly abandons as before, tests yield after improving, reduces production cost.
Specifically, partial test unit 30 is also used to carry out partial test to memory by BIST logic.
With reference to Fig. 6, partial test unit 30, including address receiving module 31 and test module 32.
Address receiving module 31 can use the test address the memory information in test signal for receiving；
Test module 32, for being tested according to test address memory.
Specifically, BIST logic is the built-in self-test algorithm logic of conventional memory defect test, due to it is this from
Test logic cannot arbitrarily change internal structure, while also need to only keep original conventional BIST logic structure, still be suitable for
Existing memory reduces testing cost without building a set of new test logical architecture again according to the present invention.It realizes and both adapted to
BIST logic is tested, but will not the part false retrieval redundancy memory purpose, existing line position sequence of partial sums position can be used
Part substitutes the line position sequence of partial sums bit position of redundant circuit.
The circuit DFT of the application is designed, and the demand of existing MemoryBIST test logic has both been adapted to, using practical use
Line position sequence of partial sums bit position to memory substitutes (the line position sequence of partial sums position portion comprising redundancy memory whole memory
Point) participate in MemoryBIST and carry out circuit realization, avoid because the part redundancy memory taken less than occur defect cause it is good
The problem of rate reduces.
For address receiving module 31 and test module 32, the physics of memory can be used with target is carried in test signal
Address, that is, the test address memory information, according to can be directly to available with the address information that carries in test signal
Memory is tested, and whether accurately understand can normal with the function of memory.Also, it can be superfluous with not carried in test signal
The physical address of remaining memory is directly skipped redundancy memory, the memory of full wafer is not added during actual test
That distinguishes detect, and is only quickly tested available memory, improves testing efficiency.In the function of available memory
Normally, and in the case that the function of redundancy memory goes wrong, also full wafer memory can be considered as non-defective unit, rather than as it
Preceding equally direct discarding tests yield after improving, reduces production cost.
For result acquiring unit 40, after the completion of test, full wafer memory can be just represented with the test result of memory
Test result, skip redundancy memory completely, whether go wrong regardless of redundancy memory, all do not interfere with available memory
It is whether normal, therefore the test result of full wafer memory will not be influenced, help to save chip cost, improve test work
Journey efficiency.
This programme is avoided superfluous by selectively being tested just for the available memory that target in memory uses
Interference of the remaining memory failure to test result improves testing efficiency, improves simultaneously under the premise of guaranteeing does not influence use
The yields of memory reduces production cost.
The above description is only a preferred embodiment of the present invention, is not intended to limit the scope of the invention, all utilizations
Equivalent structure or equivalent flow shift made by description of the invention and accompanying drawing content is applied directly or indirectly in other correlations
Technical field, be included within the scope of the present invention.
Claims (8)
1. a kind of memory redundant digit test method for avoiding loss yield, which comprises the following steps:
Test signal can be used by receiving；
According to test signal can be used, partial test is carried out to target memory；
Test result is obtained, judges whether target memory is qualified according to test result.
2. avoiding the memory redundant digit test method of loss yield as described in claim 1, which is characterized in that the basis
Test signal can be used, before carrying out partial test step to target memory, including,
Redundancy memory is filtered out, using redundancy memory as non-test target, and using remaining memory as target memory.
3. avoiding the memory redundant digit test method of loss yield as described in claim 1, which is characterized in that described to mesh
It marks memory and carries out partial test step, including,
Partial test is carried out to memory by BIST logic.
4. avoiding the memory redundant digit test method of loss yield as claimed in claim 3, which is characterized in that described to pass through
BIST logic carries out partial test step to memory, including,
The test address the memory information in test signal can be used by receiving；
Memory is tested according to test address.
5. a kind of memory redundant digit test device for avoiding loss yield characterized by comprising
Signal receiving unit can use test signal for receiving；
Partial test unit, for carrying out partial test to target memory according to test signal can be used；
As a result acquiring unit judges whether target memory is qualified according to test result for obtaining test result.
6. avoiding the memory redundant digit test device of loss yield as claimed in claim 5, which is characterized in that further include sieve
Menu member, the screening unit, for filtering out redundancy memory, using redundancy memory as non-test target, and by remaining
Memory is as target memory.
7. avoiding the memory redundant digit test device of loss yield as claimed in claim 5, which is characterized in that the part
Test cell is also used to carry out partial test to memory by BIST logic.
8. avoiding the memory redundant digit test device of loss yield as claimed in claim 7, which is characterized in that the part
Test cell, including address receiving module and test module,
The address receiving module can use the test address the memory information in test signal for receiving；
The test module, for being tested according to test address memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910111971.6A CN109857606A (en) | 2019-02-12 | 2019-02-12 | Avoid the memory redundant digit test method and device of loss yield |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910111971.6A CN109857606A (en) | 2019-02-12 | 2019-02-12 | Avoid the memory redundant digit test method and device of loss yield |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109857606A true CN109857606A (en) | 2019-06-07 |
Family
ID=66897757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910111971.6A Pending CN109857606A (en) | 2019-02-12 | 2019-02-12 | Avoid the memory redundant digit test method and device of loss yield |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109857606A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1708808A (en) * | 2002-12-16 | 2005-12-14 | 国际商业机器公司 | Enabling memory redundancy during testing |
| CN101339811A (en) * | 2008-08-14 | 2009-01-07 | 四川登巅微电子有限公司 | Build-in self-test method of memory |
| CN101630337A (en) * | 2009-07-28 | 2010-01-20 | 浪潮电子信息产业股份有限公司 | Realization method for improving chip yield |
| CN107039084A (en) * | 2017-03-01 | 2017-08-11 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of memory chip with redundancy unit |
-
2019
- 2019-02-12 CN CN201910111971.6A patent/CN109857606A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1708808A (en) * | 2002-12-16 | 2005-12-14 | 国际商业机器公司 | Enabling memory redundancy during testing |
| CN101339811A (en) * | 2008-08-14 | 2009-01-07 | 四川登巅微电子有限公司 | Build-in self-test method of memory |
| CN101630337A (en) * | 2009-07-28 | 2010-01-20 | 浪潮电子信息产业股份有限公司 | Realization method for improving chip yield |
| CN107039084A (en) * | 2017-03-01 | 2017-08-11 | 上海华虹宏力半导体制造有限公司 | The crystal round test approach of memory chip with redundancy unit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6550023B1 (en) | On-the-fly memory testing and automatic generation of bitmaps | |
| US7178072B2 (en) | Methods and apparatus for storing memory test information | |
| US7206984B2 (en) | Built-in self test circuit and test method for storage device | |
| JP3893238B2 (en) | Semiconductor memory device failure analysis device | |
| CN101515479B (en) | Method for increasing test coverage of scan chain and device thereof | |
| JP2007172778A (en) | Memory test circuit and memory test method | |
| US20090172483A1 (en) | On-chip failure analysis circuit and on-chip failure analysis method | |
| US20090089637A1 (en) | Semiconductor test system and test method thereof | |
| US20040068675A1 (en) | Circuit board having boundary scan self-testing function | |
| US7249296B2 (en) | Semiconductor integrated circuit | |
| US7152194B2 (en) | Method and circuit for scan testing latch based random access memory | |
| US20120229155A1 (en) | Semiconductor integrated circuit, failure diagnosis system and failure diagnosis method | |
| EP1332416A2 (en) | Bist for parallel testing of on-chip memory | |
| US20040153806A1 (en) | Technique for testability of semiconductor integrated circuit | |
| CN109857606A (en) | Avoid the memory redundant digit test method and device of loss yield | |
| CN1934655B (en) | Method for detecting delay fault in semiconductor memories and test circuit | |
| US7760541B2 (en) | Functional float mode screen to test for leakage defects on SRAM bitlines | |
| US8441277B2 (en) | Semiconductor testing device, semiconductor device, and testing method | |
| CN112151103B (en) | DRAM fault detection method and device based on March algorithm | |
| US6732348B1 (en) | Method for locating faults in a programmable logic device | |
| CN114333959A (en) | Memory self-checking device and method | |
| JP2006286030A (en) | Semiconductor apparatus | |
| US7370257B2 (en) | Test vehicle data analysis | |
| JP2865035B2 (en) | Test method for semiconductor memory device | |
| US20100174957A1 (en) | Correlation and overlay of large design physical partitions and embedded macros to detect in-line defects |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190607 |