CN104599998A - Method for electrical failure analysis of failure chips - Google Patents
Method for electrical failure analysis of failure chips Download PDFInfo
- Publication number
- CN104599998A CN104599998A CN201510071049.0A CN201510071049A CN104599998A CN 104599998 A CN104599998 A CN 104599998A CN 201510071049 A CN201510071049 A CN 201510071049A CN 104599998 A CN104599998 A CN 104599998A
- Authority
- CN
- China
- Prior art keywords
- safe register
- register
- chip
- safe
- lock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for electrical failure analysis of failure chips. Characteristic parameters of the chips are recorded in the CP (chip probing) process, the chip characteristic parameters collected during CP are written into a safe register finally and are changed to the read-only status so as to obtain chip characteristic parameters in the initial CP quickly and efficiently in subsequent electrical failure analysis, and accordingly labor and cost of a testing machine are saved to some extent, and analysis efficiency of the chips in the later period is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of method of chip failing being carried out to electrical property failure analysis.
Background technology
Failure analysis is the important means improving semiconductor product yield, its principle is generally when the chip produced breaks down, by ineffectiveness analysis, to orient the physical address of disabling unit, and analysis is which kind of defect causes described disabling unit to lose efficacy, so that improve in follow-up preparation process, improve yield.
In the production technology of this area, person skilled is in order to carry out the electrical property failure of batch chip analysis, or collection production line suffers the wafer of low yield, or the performance data of the quantitative sample (Package) of collection client returns, often adopt following two kinds of methods:
First: if at CP (Chip Probing, chip testing) in test technology process, there is the characterisitic parameter being recorded each chip by the file (datalog) of Self-adaptive, when so the later stage will carry out electrical property failure analysis to chip failing, just go to consult the file generated in the test of corresponding chip failing.
Second: if not by the characterisitic parameter of each chip of file record of Self-adaptive in CP test process, when so the later stage will carry out electrical property failure analysis to chip failing, need the parameter remeasuring and arrange all chip characteristics.
Above-mentioned first method is in subsequent analysis, need server to be searched the datalog on the corresponding inefficacy wafer of decompress(ion), but the datalog file of CP is very large often, think all performance datas of some chip failing in locating file, very inconvenient, often require a great deal of time, or please special data processing personnel help exploitation corresponding code, cause extra spending.
Above-mentioned second method is in subsequent analysis, need the characterisitic parameter of expensive time manpower and the new Collection and analysis chip failing of board time duplicate removal, and some characterisitic parameters cannot regather because chip itself is not in initial condition, various characterisitic parameters under such as UV state, also have some parameters because of chip later stage lost efficacy also become and cannot collect, thus cannot recognize CP test in some characterisitic parameter whether be in edge fail (marginal fail) state.
Therefore, need badly and a kind of novel scheme being conducive to electrical property failure analysis is provided, become the direction that those skilled in the art are devoted to study.
Summary of the invention
In view of the above problems, the invention provides a kind of method of chip failing being carried out to electrical property failure analysis, the method can record required characterisitic parameter in CP test process, testing final stage at CP writes in safe register (security register) by characterisitic parameter, and it can be made to become a read states, so that in follow-up electrical property failure is analyzed, the supplemental characteristic of chip rapidly and efficiently can be obtained.
The present invention solves the problems of the technologies described above adopted technical scheme:
Chip failing is carried out to a method for electrical property failure analysis, wherein, described method comprises:
Step S1, provide original chip, and this original chip is provided with memory block;
Step S2, chip testing is carried out to described original chip, with obtain and the characterisitic parameter storing this original chip to described memory block;
Wherein, when described original chip lost efficacy, read the part or all of described characterisitic parameter be stored in described memory block, and carried out described electrical property failure analysis according to the characterisitic parameter read.
Preferably, above-mentioned method, wherein, described original chip is provided with storage array district, and described memory block and described storage array district are independently arranged.
Preferably, above-mentioned method, wherein, described memory block is safe register, and includes the first safe register, the second safe register, the 3rd safe register and the 4th safe register.
Preferably, above-mentioned method, wherein, described step S2 specifically comprises:
Chip testing is carried out to described original chip, obtains the characterisitic parameter of this original chip;
Described characterisitic parameter is recorded in a variable, and by described variable storage in described first safe register;
The essential information of described original chip is continued to be stored in described first safe register successively, to be classified according to voltage, electric current and time by the characterisitic parameter in described variable, and one_to_one corresponding is stored in the second safe register, the 3rd safe register and the 4th safe register respectively.
Preferably, above-mentioned method, wherein, the essential information of described original chip is followed successively by batch, wafer numbering, coordinate and chip quality classification.
Preferably, above-mentioned method, wherein, described characterisitic parameter all stores in floating type mode, and each described characterisitic parameter all occupies 4 bytes.
Preferably, above-mentioned method, wherein, in described step S2, when the characterisitic parameter of original chip is stored to after in described memory block, also comprise: write status register by one and described first safe register, described second safe register, described 3rd safe register and described 4th safe register are processed, be all in a read states to make it.
Preferably, above-mentioned method, wherein, described in write in status register and store the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit;
Described status register of writing processes described first safe register, described second safe register, described 3rd safe register and described 4th safe register one to one respectively by the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit.
Preferably, above-mentioned method, wherein, write status register described in and with correspondence, described first safe register, described second safe register, described 3rd safe register and described 4th safe register are become a read states by the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit all being become ' 1 '.
Preferably, above-mentioned method, wherein, when described original chip lost efficacy, read the part or all of described characterisitic parameter in safe register reading described first safe register, described second safe register, described 3rd safe register and described 4th safe register by one, and carry out described electrical property failure analysis according to the characterisitic parameter read.
Technique scheme tool has the following advantages or beneficial effect:
The invention discloses a kind of method of chip failing being carried out to electrical property failure analysis, save manpower and tester table cost to a certain extent, improve the analysis efficiency of later stage to the chip lost efficacy, this method is equivalent to make each chip have oneself birth health record, in the follow-up state to each characterisitic parameter in their CP tests can be traced back to during fine or not chip analysis, thus provide full and accurate data foundation.
Concrete accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more apparent.Mark identical in whole accompanying drawing indicates identical part.Proportionally can not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the method flow schematic diagram in the present invention, chip failing being carried out to electrical property failure analysis.
Embodiment
When the electrical property failure of chip failing being analyzed in prior art for solving, the all performance data programs obtaining some chip failing are comparatively complicated, or because fullying understand that the characterisitic parameter of chip failing causes judging many defects such as chip failure type, the invention provides a kind of method of chip failing being carried out to electrical property failure analysis.
Core concept of the present invention is: in CP test process, record required characterisitic parameter, in CP test finally by the chip characteristics parameter read-in safe register collected, and make it become a read states, so that in follow-up electrical property failure is analyzed, the characterisitic parameter of each chip in initial CP rapidly and efficiently can be obtained.
Below in conjunction with accompanying drawing and specific embodiment, the present invention is further illustrated, but not as limiting to the invention.
As shown in Figure 1, these concrete steps of chip failing being carried out to the method for electrical property failure analysis are:
Step S1, provide original chip, storage array district and memory block is provided with in this original chip, this memory block and this storage array district independently exist, and when subsequent clients carries out any operation to this storage array district, can not change the information stored in this memory block.
Step S2, chip testing is carried out to this original chip, i.e. CP, with obtain and the characterisitic parameter storing this original chip in memory block.
Carry out Electrical analysis because of follow-up to this original chip, need some characterisitic parameter searching this chip, therefore first, we are in all test item analyses utilizing CP to chip, obtain characterisitic parameter corresponding in those test items, and arrange it.
Preferably, this memory block is safe register, and this safe register of matrix comprises several as follows, i.e. the first safe register, the second safe register, the 3rd safe register and the 4th safe register.
Concrete, chip testing is carried out to original chip, after obtaining the characterisitic parameter of this original chip, the characterisitic parameter after arranging is recorded in a variable, and is stored in the first safe register;
The essential information of this original chip is continued to be stored in the first safe register successively, to be classified according to voltage, electric current and time by the characterisitic parameter in variable, and one_to_one corresponding is stored in the second safe register, the 3rd safe register and the 4th safe register respectively.By in characterisitic parameter corresponding stored to the second safe register of above-mentioned voltage class; By other characterisitic parameter corresponding stored of current capacity in the 3rd safe register; By the characterisitic parameter corresponding stored of time classification in the 4th safe register, wherein, characterisitic parameter is all stored in corresponding safe register in floating type mode, and each characterisitic parameter all occupies 4 bytes.
In an embodiment of the present invention, preferably, the essential information of this original chip is followed successively by batch (lot), wafer numbering (wafer id), coordinate and chip quality classification (bin).
Preferably, the characterisitic parameter of voltage class is stored in above-mentioned second safe register, and specifically comprise: the low end value of VT, peak value and high end value under UV state, under erase status (erase status) and under programming state (programstatus), the low end value of VT, peak value, the high end value of all bits (bit) under being in erase status and programming state under gridiron pattern state (checker board).
Preferably, store other characterisitic parameter of current capacity in above-mentioned 3rd safe register, and specifically comprise: the electric current of memory cell under the electric current (ICC standby) of ICC, dynamic current (ICC active), erasing shape and programming state, chip are in the leakage current (BL leakage) under UV, erasing and programming state on BL.
Preferably, store the characterisitic parameter of time classification in above-mentioned 4th safe register, and specifically comprise: erasing time of 64K, 32K, 4K sector, chip failing programming time, time in programming complete ' 0 ' and chessboard trellis state down-sampling programmed page.
Wherein, above-mentioned each safe register is the safe register of NOR Flash, after the characterisitic parameter of original chip is stored to corresponding safe register, also needs to carry out following operation:
Utilize one to write status register (write status register) to process respectively in the first above-mentioned safe register, the second safe register, the 3rd safe register and the 4th safe register, be all in a read states to make each safe register.
Concrete, this is write in status register and stores the first lock-bit (lock bit0), the second lock-bit (lock bit1), the 3rd lock-bit (lock bit2) and the 4th lock-bit (lock bit3).
This is write status register and with correspondence, the first safe register, the second safe register, the 3rd safe register and the 4th safe register is become a read states by the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit all being become ' 1 ', namely status register is write by the first lock-bit is become ' 1 ', carry out, to the first safe register process, making it be only a read states; Equally, this writes status register by the second lock-bit is become ' 1 ', carries out, to the second safe register process, making it be only a read states, for the same alignment processing of the 3rd, the 4th safe register, does not repeat them here.
Wherein, when each safe register after processed keeps read states, the information of its storage inside can not be changed by mistake, further ensure follow-up to chip carry out electrical property failure analyze time, the information of correct characterisitic parameter can be obtained.
Step S3, when original chip lost efficacy, read the part or all of characterisitic parameter that is stored in memory block, and carry out electrical property failure analysis according to the characterisitic parameter read.
Concrete, read safe register by one and read part or all of described characterisitic parameter in this first safe register, the second safe register, the 3rd safe register and the 4th safe register, and carry out electrical property failure analysis according to the characterisitic parameter read, to complete analysis process, the means that further enhancing is analyzed this chip, reduce time cost, improve analysis efficiency.
In sum, the invention discloses a kind of method of chip failing being carried out to electrical property failure analysis, by recording the characterisitic parameter of required chip in CP test process, in CP test finally by the chip characteristics parameter read-in safe register collected, and make it become a read states, so that in follow-up electrical property failure is analyzed, rapidly and efficiently can obtain the characterisitic parameter of each chip in initial CP, therefore save manpower and tester table cost to a certain extent, improve the later stage to the analysis efficiency of chip.
It should be appreciated by those skilled in the art that those skilled in the art are realizing described change case in conjunction with prior art and above-described embodiment, do not repeat at this.Such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. chip failing is carried out to a method for electrical property failure analysis, it is characterized in that, described method comprises:
Step S1, provide original chip, and this original chip is provided with memory block;
Step S2, chip testing is carried out to described original chip, with obtain and the characterisitic parameter storing this original chip to described memory block;
Wherein, when described original chip lost efficacy, read the part or all of described characterisitic parameter be stored in described memory block, and carried out described electrical property failure analysis according to the characterisitic parameter read.
2. the method for claim 1, is characterized in that, described original chip is provided with storage array district, and described memory block and described storage array district are independently arranged.
3. the method for claim 1, is characterized in that, described memory block is safe register, and includes the first safe register, the second safe register, the 3rd safe register and the 4th safe register.
4. method as claimed in claim 3, it is characterized in that, described step S2 specifically comprises:
Chip testing is carried out to described original chip, obtains the characterisitic parameter of this original chip;
Described characterisitic parameter is recorded in a variable, and by described variable storage in described first safe register;
The essential information of described original chip is continued to be stored in described first safe register successively, to be classified according to voltage, electric current and time by the characterisitic parameter in described variable, and one_to_one corresponding is stored in the second safe register, the 3rd safe register and the 4th safe register respectively.
5. method as claimed in claim 4, is characterized in that, the essential information of described original chip is followed successively by batch, wafer numbering, coordinate and chip quality classification.
6. method as claimed in claim 4, it is characterized in that, described characterisitic parameter all stores in floating type mode, and each described characterisitic parameter all occupies 4 bytes.
7. method as claimed in claim 4, it is characterized in that, in described step S2, when the characterisitic parameter of original chip is stored to after in described memory block, also comprise: write status register by one and described first safe register, described second safe register, described 3rd safe register and described 4th safe register are processed, be all in a read states to make it.
8. method as claimed in claim 7, is characterized in that, described in write in status register and store the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit;
Described status register of writing processes described first safe register, described second safe register, described 3rd safe register and described 4th safe register one to one respectively by the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit.
9. method as claimed in claim 8, it is characterized in that, described in write status register and with correspondence, described first safe register, described second safe register, described 3rd safe register and described 4th safe register become a read states by the first lock-bit, the second lock-bit, the 3rd lock-bit and the 4th lock-bit all being become ' 1 '.
10. method as claimed in claim 7, it is characterized in that, when described original chip lost efficacy, read the part or all of described characterisitic parameter in safe register reading described first safe register, described second safe register, described 3rd safe register and described 4th safe register by one, and carry out described electrical property failure analysis according to the characterisitic parameter read.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510071049.0A CN104599998B (en) | 2015-02-10 | 2015-02-10 | A method of electrical property failure analysis is carried out to chip failing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510071049.0A CN104599998B (en) | 2015-02-10 | 2015-02-10 | A method of electrical property failure analysis is carried out to chip failing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104599998A true CN104599998A (en) | 2015-05-06 |
| CN104599998B CN104599998B (en) | 2018-08-24 |
Family
ID=53125690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510071049.0A Active CN104599998B (en) | 2015-02-10 | 2015-02-10 | A method of electrical property failure analysis is carried out to chip failing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104599998B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110082666A (en) * | 2019-04-10 | 2019-08-02 | 浙江省北大信息技术高等研究院 | Chip testing analysis method, device, equipment and storage medium |
| CN112557881A (en) * | 2020-12-22 | 2021-03-26 | 上海华岭集成电路技术股份有限公司 | Method for managing and controlling test quality of integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0528291A (en) * | 1991-07-22 | 1993-02-05 | Mitsubishi Electric Corp | Storage device |
| CN1320950A (en) * | 2000-03-27 | 2001-11-07 | 日本电气株式会社 | Semiconductor device producing system and method |
| CN101196553A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for improving SOC chip testing efficiency |
-
2015
- 2015-02-10 CN CN201510071049.0A patent/CN104599998B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0528291A (en) * | 1991-07-22 | 1993-02-05 | Mitsubishi Electric Corp | Storage device |
| CN1320950A (en) * | 2000-03-27 | 2001-11-07 | 日本电气株式会社 | Semiconductor device producing system and method |
| CN101196553A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for improving SOC chip testing efficiency |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110082666A (en) * | 2019-04-10 | 2019-08-02 | 浙江省北大信息技术高等研究院 | Chip testing analysis method, device, equipment and storage medium |
| CN110082666B (en) * | 2019-04-10 | 2022-02-22 | 杭州微纳核芯电子科技有限公司 | Chip test analysis method, device, equipment and storage medium |
| CN112557881A (en) * | 2020-12-22 | 2021-03-26 | 上海华岭集成电路技术股份有限公司 | Method for managing and controlling test quality of integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104599998B (en) | 2018-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8873318B2 (en) | Mechanisms for built-in self repair of memory devices using failed bit maps and obvious repairs | |
| KR101498009B1 (en) | Defective block isolation in a non-volatile memory system | |
| US8724408B2 (en) | Systems and methods for testing and assembling memory modules | |
| Li et al. | March-based RAM diagnosis algorithms for stuck-at and coupling faults | |
| CN101369463B (en) | Flash memory detection classification method | |
| KR101211042B1 (en) | Storage device and storing method for fault information of memory | |
| Hsiao et al. | Built-in self-repair schemes for flash memories | |
| US20140241084A1 (en) | Method and apparatus for repairing defective memory cells | |
| CN102208204A (en) | Method and device for detecting hard disks | |
| CN104361909A (en) | On-chip RAM built-in self-testing method and circuit | |
| CN105006253B (en) | A kind of flash memory chip data retention inspection method and system | |
| CN101308703B (en) | Method for nrom array word line retry erasing and threshold voltage recovering | |
| CN112579382A (en) | NVMe solid state disk bad block analysis method, device, terminal and storage medium | |
| Lu et al. | Efficient built-in self-repair techniques for multiple repairable embedded RAMs | |
| CN104599998A (en) | Method for electrical failure analysis of failure chips | |
| CN103811065A (en) | Non-volatile memory system | |
| CN102004220B (en) | Method and system for testing chips | |
| US10636509B2 (en) | Memory test apparatus | |
| CN107481764B (en) | 3D Nand Flash scanning detection method and system | |
| US20130100752A1 (en) | Method of restoring reconstructed memory spaces | |
| CN113380314A (en) | Memory repair test method and system | |
| Appello et al. | A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques | |
| KR101477603B1 (en) | Semiconductor memory device reducing the number of input test bit and test data writing method therefor | |
| CN117393032B (en) | Storage device and data processing method thereof | |
| CN109920461A (en) | A kind of resistance-variable storing device based on thin film transistor (TFT) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |