CN104599998B - A method of electrical property failure analysis is carried out to chip failing - Google Patents
A method of electrical property failure analysis is carried out to chip failing Download PDFInfo
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- CN104599998B CN104599998B CN201510071049.0A CN201510071049A CN104599998B CN 104599998 B CN104599998 B CN 104599998B CN 201510071049 A CN201510071049 A CN 201510071049A CN 104599998 B CN104599998 B CN 104599998B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention relates to technical field of manufacturing semiconductors, a kind of more particularly to method that electrical property failure analysis is carried out to chip failing, pass through the characterisitic parameter of the memorization COMS clip in CP test process, being tested in CP finally will be in the chip characteristics parameter read-in safe register that be collected into, and so that it becomes read-only status, in order in the analysis of subsequent electrical property failure, the characterisitic parameter of initial CP chips can rapidly and efficiently be obtained, therefore manpower and tester table cost are saved to a certain extent, improve analysis efficiency of the later stage to chip.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of electrical property failure analysis is carried out to chip failing
Method.
Background technology
Failure analysis is to improve an important means of semiconductor product yield, and principle is usually in the chip produced
It is described in which kind of defect causes to orient the physical address of disabling unit, and analyze by ineffectiveness analysis when failure
Disabling unit fails, and in order to be improved in subsequent preparation process, improves yield.
In the production technology of this field, related technical personnel in order to carry out to the electrical property failure of batch chip to analysis, or
Person collects the wafer by low yield on production line, or collects the performance data of the quantitative sample (Package) of client returns,
Often use following two methods：
First：If during CP (Chip Probing, chip testing) test technology, there is the text by Self -adaptive
Part (datalog) records the characterisitic parameter of each chip, then when the later stage will carry out electrical property failure analysis to chip failing, just goes
Consult the file generated in corresponding chip failing test.
Second：If not by the characterisitic parameter of each chip of the file record of Self -adaptive in CP test process, that
When later stage will carry out electrical property failure analysis to chip failing, the parameter for remeasuring and arranging all chip characteristics is needed.
Above-mentioned first method needs to search on server on the corresponding failure wafer of decompression in subsequent analysis
Datalog, but the datalog files of CP are often very big, think all performance datas of certain chip failings in locating file,
It is very inconvenient, it generally requires to devote a tremendous amount of time, or ask special data processing personnel to help and develop corresponding generation
Code, causes additional spending.
Above-mentioned second method needs to take a lot of time manpower and the board time goes to collect again in subsequent analysis
With the characterisitic parameter of analysis chip failing, and some characterisitic parameters can not be received again since chip itself is not at original state
Collection, such as the various characteristics parameter under UV states, also some parameters also become not collecting because the later stage of chip fails, to
It can not recognize whether certain characterisitic parameters are in edge fail (marginal fail) state in CP tests.
Therefore, it is urgent to provide a kind of novel scheme for being conducive to electrical property failure analysis, become those skilled in the art's cause
Power is in the direction of research.
Invention content
In view of the above problems, the present invention provides a kind of method carrying out electrical property failure analysis to chip failing, and this method can
Required characterisitic parameter is recorded in CP test process, and safe register is written into characterisitic parameter in CP tests final stage
In (security register), and can be so that it becomes read-only status can be fast in being analyzed in subsequent electrical property failure
Speed efficiently obtains the supplemental characteristic of chip.
Technical solution is used by the present invention solves above-mentioned technical problem：
A method of electrical property failure analysis is carried out to chip failing, wherein the method includes：
Step S1, original chip is provided, and memory block is provided in the original chip；
Step S2, chip testing is carried out to the original chip, to obtain and store the characterisitic parameter of the original chip extremely
In the memory block；
Wherein, when the original chip fails, some or all of reading is stored in the memory block characteristic
Parameter, and the electrical property failure analysis is carried out according to the characterisitic parameter of reading.
Preferably, above-mentioned method, wherein be provided with storage array area, the memory block and institute in the original chip
Storage array area is stated to be independently arranged.
Preferably, above-mentioned method, wherein the memory block be safe register, and include the first safe register,
Second safe register, third safe register and the 4th safe register.
Preferably, above-mentioned method, wherein the step S2 is specifically included：
Chip testing is carried out to the original chip, obtains the characterisitic parameter of the original chip；
The characterisitic parameter is recorded in a variable, and by the variable storage in first safe register；
Continue to store the essential information of the original chip to first safe register successively, by the change
Characterisitic parameter in amount is classified according to voltage, electric current and time, and correspond store respectively to the second safe register,
In third safe register and the 4th safe register.
Preferably, above-mentioned method, wherein the essential information of the original chip is followed successively by batch, wafer number, coordinate
With chip quality classification.
Preferably, above-mentioned method, wherein the characterisitic parameter is stored in a manner of floating type, and each spy
Property parameter occupies 4 bytes.
Preferably, above-mentioned method, wherein in the step S2, deposited when the characterisitic parameter of original chip is stored to described
After in storage area, further include：Pass through the first safe register, second safe register, institute described in a write state register pair
It states third safe register and the 4th safe register is handled, so that it is in read-only status.
Preferably, above-mentioned method, wherein be stored with the first lock-bit, the second lock-bit, third in the write state register
Lock-bit and the 4th lock-bit；
The write state register is corresponded by the first lock-bit, the second lock-bit, third lock-bit and the 4th lock-bit respectively
To first safe register, second safe register, the third safe register and it is described 4th safety post
Storage is handled.
Preferably, above-mentioned method, wherein the write state register is by locking the first lock-bit, the second lock-bit, third
Position and the 4th lock-bit become ' 1 ' with corresponding by first safe register, second safe register, the third
Safe register and the 4th safe register become read-only status.
Preferably, above-mentioned method, wherein when the original chip fails, read safe register by one and read institute
It states in the first safe register, second safe register, the third safe register and the 4th safe register
Some or all of the characterisitic parameter, and the electrical property failure analysis is carried out according to the characterisitic parameter of reading.
Above-mentioned technical proposal has the following advantages that or advantageous effect：
The invention discloses it is a kind of to chip failing carry out electrical property failure analysis method, to a certain extent save manpower and
Tester table cost improves analysis efficiency of the later stage to the chip of failure, and this method, which is equivalent to, makes each chip have certainly
Oneself records birth physical condition, and each characterisitic parameter in their CP tests can be traced back to when subsequently to fine or not chip analysis
State, to provide full and accurate data foundation.
Specific description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in whole attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the purport of the present invention.
Fig. 1 is the method flow schematic diagram for carrying out electrical property failure analysis in the present invention to chip failing.
Specific implementation mode
When to solve in the prior art to analyze the electrical property failure of chip failing, all characteristics of certain chip failings are obtained
Data program is complex, or because that can not fully understand that the characterisitic parameter of chip failing leads to not judge chip failure type etc.
Many defects, the present invention provides a kind of methods carrying out electrical property failure analysis to chip failing.
Core of the invention thought is：Required characterisitic parameter is recorded in CP test process, will finally be received in CP tests
In the chip characteristics parameter read-in safe register collected, and so that it becomes read-only status, in order in subsequent electrical property failure
In analysis, the characterisitic parameter of each chip in initial CP can be rapidly and efficiently obtained.
The present invention is further illustrated with specific embodiment below in conjunction with the accompanying drawings, but not as the limit of the present invention
It is fixed.
As shown in Figure 1, this to chip failing carry out electrical property failure analysis method the specific steps are：
Step S1, original chip is provided, be provided with storage array area and memory block in the original chip, the memory block with
The storage array area is individually present, and when subsequent clients carry out any operation to the storage array area, will not be changed in the memory block
The information stored.
Step S2, chip testing, i.e. CP, to obtain and store the characterisitic parameter of the original chip are carried out to the original chip
Into memory block.
Because subsequently to original chip progress Electrical analysis, requiring to look up certain characterisitic parameters of the chip, therefore first,
We are analyzing all test items of chip using CP, obtain corresponding characterisitic parameter in those test items, and carry out to it
It arranges.
Preferably, which is safe register, and the safe register of matrix includes following several, i.e., the first safety
Register, the second safe register, third safe register and the 4th safe register.
Specifically, to original chip progress chip testing, after the characterisitic parameter for obtaining the original chip, after arrangement
Characterisitic parameter is recorded in a variable, and is stored in the first safe register；
Continue to store the essential information of the original chip to the first safe register successively, by the characteristic in variable
Parameter is classified according to voltage, electric current and time, and is corresponded to be stored respectively to the second safe register, third and be posted safely
In storage and the 4th safe register.The characterisitic parameter of above-mentioned voltage class correspondence is stored into the second safe register；
The other characterisitic parameter correspondence of current capacity is stored into third safe register；By the characterisitic parameter of time classification correspondence store to
In 4th safe register, wherein characterisitic parameter is stored in corresponding safe register, and each characteristic in a manner of floating type
Parameter occupies 4 bytes.
In an embodiment of the present invention, it is preferred that the essential information of the original chip is followed successively by batch (lot), wafer is compiled
Number (wafer id), coordinate and chip quality classification (bin).
Preferably, it is stored with the characterisitic parameter of voltage class in above-mentioned second safe register, and specifically included：UV states
Under, the VT low sides value under erase status (erase status) and under programming state (program status), peak value and high-end
It is worth, the VT low sides of all bits (bit) under erase status and programming state is under gridiron pattern state (checker board)
Value, peak value, high end value.
Preferably, it is stored with the other characterisitic parameter of current capacity in above-mentioned third safe register, and specifically included：ICC's
Electric current, the chip of storage unit under electric current (ICC standby), dynamic current (ICC active), erasing shape and programming state
Leakage current (BL leakage) on BL under UV, erased and programmed states.
Preferably, the characterisitic parameter of having time classification is stored in above-mentioned 4th safe register, and is specifically included：64K,
Erasing time of the sector 32K, 4K, chip failing programming time, in programming complete ' 0 ' and chessboard trellis state down-sampling programmed page
Between.
Wherein, above-mentioned each safe register is the safe register of NOR Flash, when the characterisitic parameter of original chip stores
After to corresponding safe register, it is also necessary to carry out following operation：
Using a write state register (write status register) to the first above-mentioned safe register, second
It is respectively processed in safe register, third safe register and the 4th safe register, so that each safe register is equal
In read-only status.
Specifically, be stored in the write state register the first lock-bit (lock bit0), the second lock-bit (lock bit1),
Third lock-bit (lock bit2) and the 4th lock-bit (lock bit3).
The write state register by the first lock-bit, the second lock-bit, third lock-bit and the 4th lock-bit by becoming ' 1 ' with right
That answers becomes read-only shape by the first safe register, the second safe register, third safe register and the 4th safe register
State, i.e. write state register carry out, to the processing of the first safe register, keeping it only read-only by the way that the first lock-bit is become ' 1 '
State；Equally, which carries out, to the processing of the second safe register, making it only by the way that the second lock-bit is become ' 1 '
For read-only status, for third, the 4th same alignment processing of safe register, it will not be described here.
Wherein, when by treated each safe register keeps read-only status when, the information of storage inside will not be missed
Change, when further ensuring subsequently to chip progress electrical property failure analysis, the information of correct characterisitic parameter can be obtained.
Step S3, when original chip fails, some or all of reading is stored in memory block characterisitic parameter, and according to
The characterisitic parameter of reading carries out electrical property failure analysis.
Specifically, reading first safe register, the second safe register, third safety by a reading safe register
The characterisitic parameter some or all of in register and the 4th safe register, and carried out electrically according to the characterisitic parameter of reading
Failure analysis further enhances the means analyzed the chip to complete analysis process, reduces time cost, improves and divides
Analyse efficiency.
In conclusion the invention discloses a kind of methods carrying out electrical property failure analysis to chip failing, by being surveyed in CP
The characterisitic parameter of chip needed for being recorded during examination finally posts safely the chip characteristics parameter read-in being collected into CP tests
In storage, and so that it becomes read-only status can rapidly and efficiently obtain in initial CP in being analyzed in subsequent electrical property failure
The characterisitic parameter of each chip, therefore manpower and tester table cost are saved to a certain extent, improve analysis of the later stage to chip
Efficiency.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize the change case, this will not be repeated here.Such change case does not affect the essence of the present invention, not superfluous herein
It states.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this field
It applies；Any technical person familiar with the field, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit any simple modifications, equivalents, and modifications made to the above embodiment of the present invention, still fall within the present invention
In the range of technical solution protection.
Claims (10)
1. a kind of method carrying out electrical property failure analysis to chip failing, which is characterized in that the method includes：
Step S1, original chip is provided, and memory block is provided in the original chip；
Step S2, chip testing is carried out to the original chip, to obtain and store the characterisitic parameter of the original chip to described
In memory block；
Wherein, when the original chip fails, some or all of reading is stored in the memory block characterisitic parameter,
And the electrical property failure analysis is carried out according to the characterisitic parameter of reading；
By the electrical property failure analysis to the characterisitic parameter, it is to orient the physical address of disabling unit, and analyze
Which kind of defect causes the disabling unit to fail, and in order to be improved in subsequent preparation process, improves yield.
2. the method as described in claim 1, which is characterized in that storage array area is provided in the original chip, it is described to deposit
Storage area is independently arranged with the storage array area.
3. the method as described in claim 1, which is characterized in that the memory block is safe register, and includes the first peace
Full register, the second safe register, third safe register and the 4th safe register.
4. method as claimed in claim 3, which is characterized in that the step S2 is specifically included：
Chip testing is carried out to the original chip, obtains the characterisitic parameter of the original chip；
The characterisitic parameter is recorded in a variable, and by the variable storage in first safe register；
Continue to store the essential information of the original chip to first safe register successively, it will be in the variable
Characterisitic parameter classify according to voltage, electric current and time, and correspond stored respectively to the second safe register, third
In safe register and the 4th safe register.
5. method as claimed in claim 4, which is characterized in that the essential information of the original chip is followed successively by batch, wafer
Number, coordinate and chip quality classification.
6. method as claimed in claim 4, which is characterized in that the characterisitic parameter is stored in a manner of floating type, and
Each characterisitic parameter occupies 4 bytes.
7. method as claimed in claim 4, which is characterized in that in the step S2, when the characterisitic parameter of original chip stores
To after in the memory block, further include：It is posted by the first safe register described in a write state register pair, second safety
Storage, the third safe register and the 4th safe register are handled, so that it is in read-only status.
8. the method for claim 7, which is characterized in that be stored with the first lock-bit, second in the write state register
Lock-bit, third lock-bit and the 4th lock-bit；
The write state register is right correspondingly by the first lock-bit, the second lock-bit, third lock-bit and the 4th lock-bit respectively
First safe register, second safe register, the third safe register and the 4th safe register
It is handled.
9. method as claimed in claim 8, which is characterized in that the write state register is by locking the first lock-bit, second
Position, third lock-bit and the 4th lock-bit become ' 1 ' with it is corresponding by first safe register, the second safety deposit
Device, the third safe register and the 4th safe register become read-only status.
10. the method for claim 7, which is characterized in that when the original chip fails, safety deposit is read by one
Device reads first safe register, second safe register, the third safe register and the 4th safety
The characterisitic parameter some or all of in register, and the electrical property failure analysis is carried out according to the characterisitic parameter of reading.
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| CN201510071049.0A CN104599998B (en) | 2015-02-10 | 2015-02-10 | A method of electrical property failure analysis is carried out to chip failing |
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| CN201510071049.0A CN104599998B (en) | 2015-02-10 | 2015-02-10 | A method of electrical property failure analysis is carried out to chip failing |
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| CN104599998B true CN104599998B (en) | 2018-08-24 |
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| CN110082666B (en) * | 2019-04-10 | 2022-02-22 | 杭州微纳核芯电子科技有限公司 | Chip test analysis method, device, equipment and storage medium |
| CN112557881A (en) * | 2020-12-22 | 2021-03-26 | 上海华岭集成电路技术股份有限公司 | Method for managing and controlling test quality of integrated circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320950A (en) * | 2000-03-27 | 2001-11-07 | 日本电气株式会社 | Semiconductor device producing system and method |
| CN101196553A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for improving SOC chip testing efficiency |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0528291A (en) * | 1991-07-22 | 1993-02-05 | Mitsubishi Electric Corp | Storage device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1320950A (en) * | 2000-03-27 | 2001-11-07 | 日本电气株式会社 | Semiconductor device producing system and method |
| CN101196553A (en) * | 2006-12-04 | 2008-06-11 | 上海华虹Nec电子有限公司 | Method for improving SOC chip testing efficiency |
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