CN110289042B

CN110289042B - EMMC chip test system

Info

Publication number: CN110289042B
Application number: CN201910289428.5A
Authority: CN
Inventors: 李想; 刘星亮
Original assignee: Allwinner Technology Co Ltd
Current assignee: Allwinner Technology Co Ltd
Priority date: 2019-04-11
Filing date: 2019-04-11
Publication date: 2021-05-18
Anticipated expiration: 2039-04-11
Also published as: CN110289042A

Abstract

The application relates to an EMMC chip test system. The EMMC chip test system is provided with the upper computer and the lower computers, so that the upper computer can monitor the test processes of the EMMC chips of the lower computers at the same time, and the test efficiency is high. In addition, each lower computer carries on a plurality of EMMC chips for a plurality of EMMC chips can be tested in proper order to the lower computer, and the test process is automatic, and efficiency of software testing is further improved, and uses manpower and materials sparingly.

Description

EMMC chip test system

Technical Field

The application relates to the field of electronic product testing, in particular to an EMMC chip testing system.

Background

EMMC (Embedded Multi Media card) is an embedded multimedia card. The EMMC adopts a unified MMC standard interface to package a high-density NAND-Flash (one type of Flash memory, the interior of the memory adopts a nonlinear macro-unit mode, and a cheap and effective solution is provided for realizing a solid-state large-capacity memory) memory and an MMC-Controller (multimedia Controller) in a BGA (Ball Grid Array package) chip. The EMMC has the main advantages of simplifying the design of the memory of the mobile phone, increasing the updating speed and accelerating the research and development speed of the product, and is therefore popular with mobile phone manufacturers.

The EMMC compatibility test of the system-on-chip (system-on-chip) hard software of the traditional host mainly comprises two modes: a direct soldering mode and an EMMC daughter board testing mode.

The direct welding mode is to weld the EMMC chip to be tested on the system level mainboard on the chip of the host computer directly and then test the chip. The direct welding mode has the following problems: when the EMMC chip to be tested is replaced, the tested EMMC chip needs to be dismounted, and a new EMMC chip is welded, so that the method is time-consuming and labor-consuming, and the system-on-chip mainboard and the EMMC chip are easily damaged, and resource waste is caused.

The EMMC daughter board test mode is that an EMMC chip to be tested is welded on a daughter board to form an EMMC daughter board, and the EMMC daughter board is inserted into a clamping groove of an on-chip system level mainboard to be tested. However, the problems with this test method are: still can only test an EMMC chip at every turn, the EMMC daughter board that needs to dismantle to change after the test, and efficiency of software testing is low.

Disclosure of Invention

Therefore, it is necessary to provide an EMMC chip testing system for solving the problem that the conventional EMMC chip testing system can only test one EMMC chip in a single test and has low testing efficiency.

The application provides an EMMC chip test system, includes:

the upper computer is used for monitoring the test process of the EMMC chip;

the lower computers are in communication connection with the upper computers and used for executing the testing process of the EMMC chips, and each lower computer carries a plurality of EMMC chips.

In one embodiment, the upper computer includes:

and the monitoring module is used for simultaneously monitoring the test process of the EMMC chips in the lower computers.

In one embodiment, the lower computer is an on-chip system level main board, and an EMMC sub-board is embedded in each on-chip system level main board.

In one embodiment, the on-chip system-level motherboard includes:

and the system level mainboard on the chip sends the test result of the EMMC chip to the upper computer through the mainboard interface.

In one embodiment, the EMMC daughter board carries the plurality of EMMC chips.

In one embodiment, the EMMC daughter board further includes:

the control module is respectively electrically connected with the plurality of EMMC chips and is used for switching the EMMC chips to enable the system-on-chip mainboard to execute the test process of another EMMC chip after the test process executed by the system-on-chip mainboard on one EMMC chip is finished;

the processor is electrically connected with the control module and used for sending a control signal to the control module so as to control the control module to complete the switching of the EMMC chip;

and the daughter board interface is electrically connected with the processor and the upper computer respectively, and the upper computer sends a control instruction for switching the EMMC chip to the processor through the daughter board interface.

In one embodiment, the EMMC daughter board further includes:

and the signal connecting seat is arranged on the EMMC daughter board, is electrically connected with the control module and is used for connecting the on-chip system level mainboard with the EMMC daughter board.

In one embodiment, the signal connecting socket further includes:

the slot is arranged on the signal connecting seat;

the EMMC daughter board is detachably connected with the on-chip system level mainboard through the slot.

In one embodiment, the EMMC daughter board further includes:

the power supply conversion device is electrically connected with the processor and the signal connecting seat respectively and is used for supplying power to the EMMC daughter board and the on-chip system level mainboard;

the power conversion device is also used for simultaneously executing power restarting operation on the EMMC daughter board and the on-chip system level mainboard when the EMMC chip is switched so as to reestablish connection between the on-chip system level mainboard and the switched EMMC chip.

In one embodiment, the power conversion apparatus includes:

the power supply circuit is used for supplying power to the EMMC daughter board and the on-chip system level mainboard;

and the relay is respectively and electrically connected with the power circuit, the processor and the signal connecting seat and is used for connecting or disconnecting the power circuit under the control of the processor.

The application provides an EMMC chip test system for through setting up host computer and a plurality of lower computer for the test process of the EMMC chip of a plurality of lower computers can be monitored simultaneously to the host computer, and efficiency of software testing is high. In addition, each lower computer carries on a plurality of EMMC chips for a plurality of EMMC chips can be tested in proper order to the lower computer, and the test process is automatic, and efficiency of software testing is further improved, and uses manpower and materials sparingly.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of an EMMC chip test system provided by the present application;

FIG. 2 is a schematic structural diagram of an upper computer in the EMMC chip test system provided by the present application;

fig. 3 is a schematic structural diagram of an embodiment of an on-chip system-in-board in an EMMC chip test system provided in the present application;

FIG. 4 is a schematic structural diagram of an embodiment of a system-on-chip motherboard in the EMMC chip test system provided in the present application;

FIG. 5 is a schematic structural diagram of an embodiment of a system-on-chip motherboard in the EMMC chip test system provided in the present application;

FIG. 6 is a schematic structural diagram of an embodiment of a system-on-chip motherboard in the EMMC chip test system provided in the present application;

fig. 7 is a schematic structural diagram of an embodiment of an EMMC chip test system provided in the present application.

Reference numerals:

100 upper computer

110 monitoring module

200 lower computer

210 on-chip system-level motherboard

211 mainboard interface

220 EMMC daughter board

221 EMMC chip

222 control module

223 processor

224 daughter board interface

225 signal connecting seat

226 slot

227 power supply conversion device

228 power supply circuit

229 Relay

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The application provides an EMMC chip test system. It should be noted that the EMMC chip test system provided in the present application does not limit the type of test applied thereto. The EMMC chip test system may be used for a variety of test types of EMMC chips 221. The EMMC chip test system can be used for one or more of power supply test, signal test, power consumption test and stability test.

As shown in fig. 1, in an embodiment of the present application, the EMMC chip test system includes an upper computer 100 and a plurality of lower computers 200. The lower computer 200 is in communication connection with the upper computer 100. Each lower computer 200 mounts a plurality of EMMC chips 221. The upper computer 100 is used for monitoring the testing process of the EMMC chip 221. The lower computer 200 is used for executing a test process of the EMMC chip 221. The EMMC chip 221 is an embedded multimedia card.

In particular, the EMMC chip 221 is also called an embedded multimedia card. Optionally, the upper computer 100 may be a mobile terminal. Specifically, the upper computer 100 may be a PC (personal computer). The EMMC chip 221 has firmware built in. When the EMMC chip 221 is produced, a manufacturer burns a test program of the EMMC chip 221 into firmware of the EMMC chip 221. When the lower computer 200 executes the testing process of the EMMC chip 221, the lower computer 200 reads a test program in the firmware of the EMMC chip 221 to test. The upper computer 100 may monitor a plurality of test processes of the lower computer 200 at the same time. Each of the lower computers 200 can test only one of the EMMC chips 221 at a time. After one of the EMMC chips 221 is tested, the upper computer 100 controls the lower computer 200 to replace the EMMC chip 221 until all the EMMC chips 221 are tested. The test mode realizes automation of the test process.

In this embodiment, by setting the upper computer 100 and the plurality of lower computers 200, the upper computer 100 can monitor the test processes of the EMMC chips 221 of the plurality of lower computers 200 at the same time, and the test efficiency is high. In addition, each lower computer 200 is provided with a plurality of EMMC chips 221, so that the lower computer 200 can test the plurality of EMMC chips 221 in sequence, the testing process is automatic, the testing efficiency is further improved, and manpower and material resources are saved.

As shown in fig. 2, in an embodiment of the present application, the upper computer 100 includes a monitoring module 110. The monitoring module 110 is configured to monitor the testing process of the EMMC chips 221 in the plurality of lower computers 200 at the same time.

Specifically, the monitoring module 110 is embedded in the upper computer 100. After one of the EMMC chips 221 completes the test, the lower computer 200 sends a test completion message to the upper computer 100, and the monitoring module 110 of the upper computer 100 sends an instruction for replacing the EMMC chip 221 to the lower computer 200. The lower computer 200 reads a test program in the firmware of the other EMMC chip 221 according to the instruction for replacing the EMMC chip 221, and starts to test the other EMMC chip 221.

In this embodiment, the monitoring module 110 is disposed in the upper computer 100, so that the testing process of the plurality of EMMC chips 221 of the lower computer 200 can be monitored in real time, and the testing process is automated and efficient.

As shown in fig. 3, in an embodiment of the present application, the lower computer 200 may be an on-chip system-level motherboard 210. Each of the on-chip system-level motherboards 210 embeds an EMMC daughter board 220.

Specifically, the lower computer 200 may be a system-on-chip motherboard 210, that is, a motherboard running an SOC system (system-on-chip). Each of the on-chip system-level motherboards 210 has a plurality of electronic devices integrated thereon. Each of the on-chip system-level motherboards 210 embeds an EMMC daughter board 220. The EMMC sub-board 220 may mount the EMMC chip 221 thereon. Optionally, the EMMC daughter board 220 is detachably connected to the on-chip system-in-board 210. After the test process of the EMMC chip 221 on one EMMC daughter board 220 is completed, the EMMC daughter board 220 may be pulled out and another EMMC daughter board 220 may be replaced for testing.

In this embodiment, the EMMC daughter board 220 is disposed on the on-chip system-in-board main board 210, so that the EMMC chip 221 can be recycled after testing, and is not damaged, thereby saving physical resources.

Referring to fig. 3, in an embodiment of the present application, the on-chip system-level motherboard 210 includes a motherboard interface 211. The mainboard interface 211 is electrically connected to the upper computer 100. The on-chip system-level motherboard 210 sends the test result of the EMMC chip 221 to the upper computer 100 through the motherboard interface 211.

Specifically, after the test of the EMMC chip 221 is completed, the chip upper system motherboard sends the test result of the EMMC chip 221 to the upper computer 100 through the motherboard interface 211. Optionally, each time one of the EMMC chips 221 completes testing, the upper system motherboard sends the test result of the EMMC chip 221 to the upper computer 100 through the motherboard interface 211. Optionally, after all the EMMC chips 221 on the upper system motherboard are tested, the upper system motherboard sends the test results of all the EMMC chips 221 to the upper computer 100 through the motherboard interface 211.

In this embodiment, the motherboard interface 211 is disposed on the on-chip system-level motherboard 210, so that the upper computer 100 can obtain the test result of the EMMC chip 221 in real time.

Referring to fig. 3, in an embodiment of the present application, the EMMC daughter board 220 mounts the plurality of EMMC chips 221.

Specifically, the plurality of EMMC chips 221 may be soldered to the EMMC daughter board 220. The number of the EMMC chips 221 and the arrangement of the EMMC chips 221 are determined by the circuit structure of the EMMC daughter board 220. Optionally, one EMMC daughter board 220 mounts 8 EMMC chips 221.

In this embodiment, the plurality of EMMC chips 221 are carried on the EMMC daughter board 220, so that a single upper system motherboard can test the plurality of EMMC chips 221 in turn in a total test, the trouble of frequently plugging and unplugging the EMMC daughter board 220 is eliminated, and the test efficiency is greatly improved.

Referring still to fig. 3, in an embodiment of the present application, the EMMC daughter board 220 further includes a control module 222, a processor 223, and a daughter board interface 224. The control modules 222 are electrically connected to the EMMC chips 221, respectively. The processor 223 is electrically connected to the control module 222. The daughter board interface 224 is electrically connected to the processor 223 and the host computer 100, respectively. The control module 222 is configured to switch the EMMC chip 221 after the test procedure executed by the on-chip system-level motherboard 210 on one EMMC chip 221 is finished, so that the on-chip system-level motherboard 210 executes the test procedure of another EMMC chip 221. The processor 223 is configured to send a control signal to the control module 222 to control the control module 222 to complete the switching of the EMMC chip 221. The upper computer 100 sends a control instruction for switching the EMMC chip 221 to the processor 223 through the daughter board interface 224.

Specifically, the processor 223 may be an MCU (micro control unit). The control module 222 may be an analog switch bank. The processor 223 is a processing core of the EMMC daughter board 220. The control module 222 is provided with a plurality of EMMC interfaces, and each of the EMMC interfaces is connected to one of the EMMC chips 221. When the upper system motherboard executes a test process on one of the EMMC chips 221, the processor 223 controls the control module 222 to open the EMMC interface corresponding to the EMMC chip 221 to be tested and close the EMMC interface corresponding to the other non-EMMC chips 221 to be tested. After the upper system motherboard finishes the test execution process of the EMMC chip 221, the upper system motherboard returns a test result to the upper computer 100. The upper computer 100 sends a control instruction for switching the EMMC chip 221 to the processor 223 of the EMMC daughter board 220 through the daughter board interface 224. Further, the processor 223 sends a control signal to the control module 222 to control the control module 222 to open the EMMC interface of another EMMC chip 221 to be tested, so as to complete the switching of the EMMC chip 221.

In this embodiment, the control module 222, the processor 223 and the daughter board interface 224 are arranged on the EMMC daughter board 220, so that after the testing process of one EMMC chip 221 is finished, the testing process of the other EMMC chip 221 is automatically switched, the testing of the EMMC chip 221 is automated, the EMMC chip 221 does not need to be manually replaced, manual supervision is not needed, and manpower is saved.

Referring to fig. 3, in an embodiment of the present application, the EMMC daughter board 220 further includes a signal connection socket 225. The signal connection socket 225 is disposed on the EMMC daughter board 220. The signal connection socket 225 is electrically connected to the control module 222. The signal connection socket 225 is used for connecting the on-chip system-level main board 210 and the EMMC sub-board 220.

Specifically, the signal connection socket 225 has a connection circuit built therein, so that the EMMC daughter board 220 and the on-chip system-level motherboard 210 are electrically connected.

In this embodiment, the signal connection socket 225 is disposed on the EMMC sub-board 220, so that the EMMC sub-board 220 can be fixedly connected and electrically connected to the on-chip system-level main board 210 through the signal connection socket 225.

As shown in fig. 4, in an embodiment of the present application, the signal connecting socket 225 further includes a slot 226. The insertion slot 226 is disposed in the signal connection socket 225. The EMMC daughter board 220 is detachably connected to the on-chip system-in-board 210 through the socket 226.

Specifically, when a test of one of the EMMC daughter boards 220 is started, the EMMC daughter board 220 is inserted into the slot 226 of the signal connection socket 225. When the test of one of the EMMC daughter boards 220 is finished, the EMMC daughter board 220 is pulled out of the slot 226 of the signal connection socket 225.

In this embodiment, the detachable connection between the EMMC daughter board 220 and the on-chip system-level motherboard 210 is realized by arranging the slot 226 on the signal connection socket 225, so that the EMMC daughter board 220 can be safely pulled out after the test is finished, the EMMC daughter board 220 is not damaged, the EMMC chip 221 inside the EMMC daughter board 220 is not damaged, the test can be circulated, and the test cost is saved.

As shown in fig. 5, in an embodiment of the present application, the EMMC daughter board 220 further includes a power conversion device 227. The power conversion device 227 is electrically connected to the processor 223. The power conversion device 227 is also electrically connected to the signal connection socket 225. The power conversion device 227 is electrically connected to the on-chip system-level motherboard 210 through the signal connection socket 225. The power conversion device 227 is used for supplying power to the EMMC daughter board 220 and the on-chip system-level motherboard 210.

The power conversion device 227 is further configured to perform a power restart operation on the EMMC daughter board 220 and the on-chip system-level motherboard 210 simultaneously when the EMMC chip 221 is switched, so as to reestablish a connection between the on-chip system-level motherboard and the switched EMMC chip.

Specifically, each time the EMMC daughter board 220 switches the EMMC chip 221, a power source restart needs to be performed on the EMMC daughter board 220 and the on-chip system-level motherboard 210 at the same time. After the power supply of the EMMC daughter board 220 and the on-chip system-level motherboard 210 is restarted, a test process is performed on the switched new EMMC chip 221. And when the next EMMC chip is switched, restarting the power supply again. Before each of the EMMC chips 221 is tested, a connection relationship between the EMMC chip 221 and the on-chip system-level motherboard 210 needs to be established. When the EMMC chip 221 is switched, the connection relationship between the last EMMC chip 221 and the on-chip system-level motherboard 210 needs to be disconnected, and a new connection relationship between the EMMC chip 221 and the on-chip system-level motherboard 210 needs to be established. Therefore, a power restart needs to be performed for both the EMMC daughter board 220 and the on-chip system-level motherboard 210. In an embodiment of the present application, by setting the power conversion device 227, when the EMMC chip 221 is switched, the EMMC daughter board 220 and the on-chip system-level motherboard 210 are restarted by power, so that the on-chip system-level motherboard 210 and the switched EMMC chip 221 are reconnected, and the monitoring target of the upper computer 100 can be conveniently replaced.

As shown in fig. 6, in an embodiment of the present application, the power conversion device 227 includes a power circuit 228 and a relay 229. The relay 229 is electrically connected to the power circuit 228, the processor 223, and the signal connection socket 225, respectively. The power circuit 228 is used to provide power to the EMMC daughter board 220 and the on-chip system-in-board 210. The relay 229 is used to switch the power circuit 228 on or off under the control of the processor 223.

Specifically, when the EMMC daughter board 220 and the on-chip system-on-board main board 210 need to be powered on, the processor 223 controls the on-off actuation of the relay 229, and the relay 229 is communicated with the power circuit 228. When power needs to be cut off for the EMMC sub-board 220 and the on-chip system level main board 210, the processor 223 controls the switch of the relay 229 to be opened, and the relay 229 is disconnected from the power circuit 228.

In an embodiment of the present application, the relay 229 and the power circuit 228 are arranged to power on and power off the EMMC daughter board 220 and the on-chip system-on-board main board 210, so that the EMMC chip testing system can automatically execute the testing process of the EMMC chip 221.

Fig. 7 is a schematic structural diagram of an embodiment of an EMMC chip test system provided in the present application. This embodiment covers the technical features mentioned in all the embodiments above.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. An EMMC chip test system, comprising:

the upper computer (100) is used for monitoring the test process of the EMMC chip (221); the EMMC chip (221) is an embedded multimedia card;

each lower computer (200) is in communication connection with the upper computer (100) and is used for executing the test process of the EMMC chip (221);

the lower computer (200) is an on-chip system level main board (210), an EMMC sub-board (220) is embedded in each on-chip system level main board (210), and the EMMC sub-board (220) carries a plurality of EMMC chips (221);

the EMMC daughterboard (220) includes:

the control module (222) is respectively electrically connected with the plurality of EMMC chips (221), and is used for switching the EMMC chips (221) to enable the on-chip system-level motherboard (210) to execute the test process of another EMMC chip (221) after the test process executed by the on-chip system-level motherboard (210) on one EMMC chip (221) is finished;

the processor (223) is electrically connected with the control module (222) and is used for sending a control signal to the control module (222) so as to control the control module (222) to complete the switching of the EMMC chip (221); and

and the daughter board interface (224) is respectively electrically connected with the processor (223) and the upper computer (100), and the upper computer (100) sends a control instruction for switching the EMMC chip (221) to the processor (223) through the daughter board interface (224).

2. The EMMC chip testing system according to claim 1, wherein the upper computer (100) comprises:

and the monitoring module (110) is used for monitoring the test process of the EMMC chips (221) in the lower computers (200) at the same time.

3. The EMMC chip test system according to claim 1, wherein the on-chip system-level motherboard (210) further comprises:

and the mainboard interface (211) is electrically connected with the upper computer (100), and the on-chip system level mainboard (210) sends the test result of the EMMC chip (221) to the upper computer (100) through the mainboard interface (211).

4. The EMMC chip test system of claim 1, wherein the EMMC daughter board (220) further comprises:

and the signal connecting seat (225) is arranged on the EMMC sub-board (220), is electrically connected with the control module (222), and is used for connecting the on-chip system level main board (210) and the EMMC sub-board (220).

5. The EMMC chip testing system of claim 4, wherein the signal connection socket (225) further comprises:

a slot (226) disposed in the signal connection socket (225);

the EMMC sub-board (220) is detachably connected with the on-chip system level main board (210) through the slot (226).

6. The EMMC chip test system of claim 5, wherein the EMMC daughter board (220) further comprises:

the power supply conversion device (227) is electrically connected with the processor (223) and the signal connection seat (225) respectively and used for supplying power to the EMMC sub-board (220) and the on-chip system-level main board (210);

the power conversion device (227) is further configured to, when the EMMC chip (221) is switched, perform a power restart operation on the EMMC daughter board (220) and the on-chip system-level motherboard (210) at the same time, so as to reestablish a connection between the on-chip system-level motherboard (210) and the switched EMMC chip (221).

7. The EMMC chip test system according to claim 6, wherein the power conversion device (227) comprises:

a power supply circuit (228) for supplying power to the EMMC daughter board (220) and the on-chip system-level motherboard (210);

a relay (229) electrically connected to the power circuit (228), the processor (223) and the signal connection socket (225), respectively, for switching on or off the power circuit (228) under the control of the processor (223).