CN100397646C - Integrated circuit structure having multi-version circuit selection - Google Patents
Integrated circuit structure having multi-version circuit selection Download PDFInfo
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- CN100397646C CN100397646C CNB2005100690262A CN200510069026A CN100397646C CN 100397646 C CN100397646 C CN 100397646C CN B2005100690262 A CNB2005100690262 A CN B2005100690262A CN 200510069026 A CN200510069026 A CN 200510069026A CN 100397646 C CN100397646 C CN 100397646C
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- 238000003466 welding Methods 0.000 claims description 16
- 230000005611 electricity Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 5
- 239000011324 bead Substances 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 101100272964 Arabidopsis thaliana CYP71B15 gene Proteins 0.000 description 1
- 101150030164 PADI3 gene Proteins 0.000 description 1
- 102100035734 Protein-arginine deiminase type-3 Human genes 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
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Abstract
The present invention discloses an integrated circuit structure with multiple versions of circuit selection. The integrated circuit structure comprises an integrated circuit module of each version, wherein the integrated circuit module of each version is provided with an input buffer. A plurality of selection bonding pads and power supply bonding pads which are connected with the selection bonding pads are arranged near a power supply bus of an integrated circuit, wherein the power supply bonding pads and the power supply bus are switched on and connected; the selection bonding pads and the input buffers are in one-to-one correspondence, and the selection bonding pads and input ends of the input buffers are switched on and connected. Compared with the prior art, the present invention has the characteristics that the structure is reasonable and simple, the difficulty of circuit design can be effectively reduced, cost is saved, electricity is saved, and energy is saved, etc.
Description
Technical field
The present invention relates to a kind of structure of integrated circuit (IC) design, particularly a kind of integrated circuit structure with multi-version circuit selection.
Technical background
At present, when designing integrated circuit, people usually are integrated into the approximate circuit design of several versions in a master die or the chip.In conventional solution, integrated circuit encapsulation back is if introduce power supply, the power pad (PAD) of power supply source input then is set in the edge of integrated circuit, and the corresponding power supply that is provided with for external power supply draws pin (PIN) in its encapsulation, and power supply draws pin and imports with power supply that conducting is connected between the pad.And all adopt input buffer (Input Buffer) to import the control signal that it enters operating state for the circuit module of each version.Here, the circuit module of each version must connect pull-up resistor or pull down resistor at the input of its corresponding input buffer when idle condition (normal state).Described pull-up resistor is that the one end connects positive supply VDD, and its other end connects input buffer.Pull down resistor is that one section connects negative supply VSS, and its other end connects input buffer.The operating state of the circuit module of each version then is to select pad (Option PAD) by being provided with on integrated circuit, be used to connect the input of input buffer, and positive supply VDD or negative supply VSS, thereby introduce the selection signal starting circuit module work of high/low level.Before the finished product with this master die or chip offers the user, the mode that to utilize bonding wire (bonding wire) bonding (welding) to select pad and power supply to draw pin is carried out elastic registration (bonding option), to select the circuit module of different versions.
Before coming into operation, need demand according to the user, select the module work of a version between IC1, the IC2 in this chip, as when selecting IC1, between VSS PIN and selection pad 1 (Option PAD 1), connect a root bead line (bonding wire) (as shown in phantom in FIG.), make the input end grounding of In1, thereby selected IC1 in running order.
This way can obtain to save the plate-making cost, use characteristics such as flexible.
But there is following inevitable defective simultaneously in this structure:
1,, therefore when selection pad and negative supply VSS being drawn pin or positive supply VDD and draw pin and weld, will there be leakage current on pull-up resistor or the pull down resistor owing to must use pull-up resistor or pull down resistor.
2, because the restriction of the physical condition of the making integrated circuit of prior art is drawn pin (Package Pin) for each encapsulation, the quantity of the bonding wire that it can be placed (bonding wire) is very limited, generally is no more than two.And generally between power supply PIN and power supply PAD, must adopt at least one root bead line (bonding wire) to connect, generally connect better, and adopt two root bead lines (bonding wire) for power supply.The bonding wire (bonding wire) that so just makes power supply PIN and select can be provided with between the pad seldom.Therefore, when selecting the pad setting many more, people just have to be provided with the power supply PIN that more is specifically designed to and selects pad welding (bonding), like this with regard to encapsulation to integrated circuit caused physically waste and the increase of cost.
3, in the prior art, in order to weld (bonding) to power supply PIN, select pad must be in close proximity to VDD PAD or VSS PAD placement, and when specifically implementing, often be difficult to find suitable placement to select the position of pad at VDD PAD or the contiguous place of VSS PAD, therefore design is gone up and is had bigger trouble.
Summary of the invention
The objective of the invention is: at the deficiencies in the prior art, provide a kind of rational in infrastructure, and can simplify the integrated circuit structure that multi-version circuit is selected that has of circuit design.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of integrated circuit structure with multi-version circuit selection, the integrated circuit modules that comprises each version, and the integrated circuit modules of each version all has its input buffer, the power pad that is provided with a plurality of selection pads and is used for and selects pad to be connected on the power bus side of integrated circuit, wherein power pad is connected with the power bus conducting, described selection pad is corresponding one by one with described input buffer, and selects pad to be connected with the input conducting of input buffer.When the version that carries out integrated circuit was selected, the selection pad of the integrated circuit modules of selected work and power pad welding obtained to select signal.
Described power pad can comprise a pair of positive supply pad and negative supply pad at least, they are arranged at each respectively and select the pad both sides, the selection pad of the integrated circuit modules of selected work with just/negative supply pad welding, the selection pad of the integrated circuit modules that leave unused welds with negative/positive supply pad.
A plurality of selection pads can a shared power pad.
Two adjacent selection pads can a shared power pad that is between them.
Non-conterminous a plurality of selection pad can a shared power pad.
In technique scheme, the present invention is owing to set up the power pad that is specifically designed to and selects pad welding (bonding) near power bus, thereby make when the version that carries out integrated circuit is selected, directly the selection pad with the circuit module of selected work welds with power pad, can obtain to select signal.Therefore select the placement location of pad and power pad not to be subjected to power supply to draw the pin position and draw restriction, can be provided with arbitrarily in the position of IC interior near power bus at the power pad position of answering with power supply.And since pad the bonding wire (bonding wire) that can weld simultaneously quantity greatly more than encapsulation draw pin PackagePin the quantity of the bonding wire (bonding wire) that can weld simultaneously, therefore, can not cause waste physically.
Further, power pad of the present invention comprises a pair of positive supply pad and negative supply pad at least, thereby can realize making selected work circuit module the selection pad with just/negative supply pad welding (bonding), make by the selection pad of idle circuit module and negative/positive supply pad welding (bonding).So just saved and drawn on connecting/necessity of pull down resistor, also just saved draw/pull down resistor caused the trouble of leakage current.
Therefore, relative prior art, that the present invention has is rational in infrastructure, simple, can effectively reduce the circuit design difficulty, save characteristics such as cost, power and energy saving.
Description of drawings
Accompanying drawing 1 is the structure principle chart of a kind of integrated circuit of the prior art;
Accompanying drawing 2 is the structure principle chart of the integrated circuit of a kind of preferred embodiment of the present invention;
Accompanying drawing 3 is the structure principle chart of the integrated circuit of another kind of embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description and specific embodiment the present invention is described in further detail.
Embodiment 1:
Present embodiment provides a kind of integrated circuit structure that two kinds of versions are selected that has.
With reference to the accompanying drawings 2, A is the integrated circuit outer package, and B is an integrated circuit.VDD PIN and VSS PIN are respectively that positive supply draws pin and negative supply draws pin, are used for this integrated circuit B external power supply.VDD PAD and VSS PAD are respectively positive supply pad and the negative supply pad on the edge that is arranged at B, and corresponding conducting is connected with VSS PIN with VDD PIN respectively for they, thereby introduce power supply to integrated circuit B.VDDBus and VSS Bus are respectively positive power bus and the negative power supply bus that is arranged at the inner somewhere of integrated circuit B (can be any rational position of the inside of integrated circuit B).IC1 and IC2 are respectively the integrated circuit modules of two different editions, and IN1 and IN2 are respectively the input buffer InputBuffer of IC 1 and IC2.Select pad 1 (Option PAD 1) and select pad 2 (Option PAD 2) to be respectively the selection pad of IC 1 and IC2.Select the contiguous VSS PAD that is provided with of pad and two VDDPAD for being used for and the power pad of selecting pad welding (bonding) for two, they respectively with integrated circuit modules in corresponding power bus conducting connect.Three power pads and two selection pads are provided with in twos at interval, thereby make positive supply pad and negative supply pad be respectively in the left and right sides that each selects pad.Dotted line a, b, c, d are respectively the bonding wire (bonding wires) when carrying out elastic registration (bonding option).
Adopt the integrated circuit of this structure, when carrying out elastic registration (bonding option), as select integrated circuit modules (as IC1) when work of one of them version, then selecting to use bonding wire (bonding wire) a welding between pad 1 (OptionPAD 1) the VDD PAD adjacent, and selecting to use bonding wire (bonding wire) c welding between pad 2 (Option PAD 2) the VSS PAD adjacent with its left side with its left side.Otherwise, then use b and d.So, then make the input of IN1 insert high level, start IC1 and enter operating state.Make the input end grounding of IN2 simultaneously, prevent that the input of IN2 is unsettled, pull down resistor must be set, have the defective of leakage current and cause.And, owing to select pad and power pad adjacent arranging at interval, to be convenient in the actual course of processing on the one hand, a bead on point between selection pad and the power pad can be realized adopting the conducting of bonding wire to connect, and make its technical process simple relatively; Also make on the other hand adjacent two select pads can be shared that power pad between them, as select pad 1 (Option PAD 1) and select pad 2 (Option PAD 2) just can be shared VSS PAD between them, make when having the circuit module that surpasses two versions, if IC1 and IC2 are idle condition, then select pad 1 (Option PAD 1) and select the pad 2 (Option PAD 2) can be simultaneously and the welding of the VSS PAD between them (bonding).
By above-mentioned analysis as can be seen, the integrated circuit of this structure, it is selected pad and is used for all can being placed on any rational position contiguous with power bus on the integrated circuit with the power pad of selecting pad welding (bonding), so the limitation of its physical location is very little.And select pad to need not to draw pin welding (bonding), thereby simplified the outer enclosure structure Design greatly and arranged with power supply.In addition, the input of input buffer can be not unsettled under any state, therefore need not unnecessary the setting and draw/pull down resistor, just removed the loss of leakage current from yet.
Embodiment 2:
Present embodiment provides a kind of integrated circuit structure that 3 kinds of versions are selected that has.
With reference to the accompanying drawings 3 and since the title of each parts all with the accompanying drawing 2 of embodiment 1 in identical, for simplicity's sake, the structure of difference is only described here.
Be with first kind of difference of embodiment 1: increased set of circuits module I C3, thereby corresponding its Input Buffer IN3 of increase and selection pad Option PAD3, and the bonding wire (bonding wire) 5,6 that is used to carry out elastic registration (bonding option).
Be with second kind of difference of embodiment 1: select arranging of pad and power pad different.As can be seen from Figure 3, though present embodiment has three to select pad, a positive supply pad VDD PAD and a negative supply pad VSS PAD have only been adopted.Be that non-conterminous a plurality of selection pad also can the common source pad.
The relative embodiment 1 of present embodiment needs the power pad of setting few, can simplify physical structure, but because the shared power pad of non-conterminous a plurality of selection pads causes the placement difficulty of bonding wire (bonding wire) to increase, therefore relative embodiment 1, its processing technology is comparatively complicated.
Although having the integrated circuit structure that multi-version circuit selects to the present invention with the foregoing description, the present invention is described in detail, but because its structure can mentality of designing according to the present invention be made multiple conversion, as change the distributing order of power pad among two embodiment, change welding (bonding) relation of selecting pad and positive supply pad when starting operating state among two embodiment, increase or reduce the power pad that is adopted among two embodiment or the quantity of selecting pad or the like, and specification of the present invention is difficult to these conversion of limit, therefore the present invention is not limited in above embodiment, and can extend to those of ordinary skill in the art by reading the apparent and easy to know embodiment that above embodiment expects.
Therefore, any change or modification that those of ordinary skill in the art has done the integrated circuit structure with multi-version circuit selection of the present invention ought to drop within the present invention's claim scope required for protection.
Claims (5)
1. one kind has the integrated circuit structure that multi-version circuit is selected, the integrated circuit modules that comprises each version, and the integrated circuit modules of each version all has its input buffer, it is characterized in that: the power pad that is provided with a plurality of selection pads and is used for and selects pad to be connected on the power bus side of integrated circuit, wherein power pad is connected with the power bus conducting, described selection pad is corresponding one by one with described input buffer, and select pad to be connected with the input conducting of input buffer, when the version that carries out integrated circuit is selected, the selection pad of the integrated circuit modules of selected work and power pad welding obtain to select signal.
2. has the integrated circuit structure that multi-version circuit is selected according to claim 1, it is characterized in that: described power pad comprises a pair of positive supply pad and negative supply pad at least, they are arranged at each respectively and select the pad both sides, the selection pad of the integrated circuit modules of selected work with just/negative supply pad welding, the selection pad of the integrated circuit modules that leave unused welds with negative/positive supply pad.
3. as described in claim 2, have the integrated circuit structure that multi-version circuit is selected, it is characterized in that: the shared power pad of a plurality of selection pads.
4. as described in claim 3, have the integrated circuit structure that multi-version circuit is selected, it is characterized in that: select the shared power pad that is between them of pad for adjacent two.
5. as described in claim 3, have the integrated circuit structure that multi-version circuit is selected, it is characterized in that: the shared power pad of non-conterminous a plurality of selection pads.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100690262A CN100397646C (en) | 2005-05-10 | 2005-05-10 | Integrated circuit structure having multi-version circuit selection |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100690262A CN100397646C (en) | 2005-05-10 | 2005-05-10 | Integrated circuit structure having multi-version circuit selection |
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| CN1700471A CN1700471A (en) | 2005-11-23 |
| CN100397646C true CN100397646C (en) | 2008-06-25 |
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| CNB2005100690262A Expired - Fee Related CN100397646C (en) | 2005-05-10 | 2005-05-10 | Integrated circuit structure having multi-version circuit selection |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105430902A (en) * | 2015-11-23 | 2016-03-23 | 广东欧珀移动通信有限公司 | Mobile terminal and PCB for same |
| CN114117989A (en) * | 2020-08-31 | 2022-03-01 | 长鑫存储技术有限公司 | Chip design method, chip design device, computer equipment and storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010043081A1 (en) * | 1998-06-08 | 2001-11-22 | David B. Rees | Universal logic chip |
| US6355980B1 (en) * | 1999-07-15 | 2002-03-12 | Nanoamp Solutions Inc. | Dual die memory |
| US20020192846A1 (en) * | 2001-06-13 | 2002-12-19 | Samsung Electronics Co., Ltd. | Control signal transmitting method with package power pin and related integrated circuit package structure |
| US20030235090A1 (en) * | 2002-06-24 | 2003-12-25 | Jun-Keun Lee | Semiconductor memory device with reduced package test time |
-
2005
- 2005-05-10 CN CNB2005100690262A patent/CN100397646C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010043081A1 (en) * | 1998-06-08 | 2001-11-22 | David B. Rees | Universal logic chip |
| US6355980B1 (en) * | 1999-07-15 | 2002-03-12 | Nanoamp Solutions Inc. | Dual die memory |
| US20020192846A1 (en) * | 2001-06-13 | 2002-12-19 | Samsung Electronics Co., Ltd. | Control signal transmitting method with package power pin and related integrated circuit package structure |
| US20030235090A1 (en) * | 2002-06-24 | 2003-12-25 | Jun-Keun Lee | Semiconductor memory device with reduced package test time |
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| CN1700471A (en) | 2005-11-23 |
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Granted publication date: 20080625 Termination date: 20120510 |