CN209570840U - A kind of Separable data acquisition system - Google Patents

A kind of Separable data acquisition system Download PDF

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Publication number
CN209570840U
CN209570840U CN201920682579.2U CN201920682579U CN209570840U CN 209570840 U CN209570840 U CN 209570840U CN 201920682579 U CN201920682579 U CN 201920682579U CN 209570840 U CN209570840 U CN 209570840U
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CN
China
Prior art keywords
resistance
data acquisition
acquisition system
fpga programmable
programmable unit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN201920682579.2U
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Chinese (zh)
Inventor
丁景明
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Individual
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Individual
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Priority to CN201920682579.2U priority Critical patent/CN209570840U/en
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Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a kind of Separable data acquisition system, including pcb board, control panel, power module and PC machine, the pcb board includes optical-electric module, A/D conditioning circuit, high-speed a/d conversion circuit, phaselocked loop, DDRII slot and communication module;The control panel includes FPGA programmable unit;The FPGA programmable unit is removably buckled in the DDRII slot, and the FPGA programmable unit is electrically connected by the DDRII slot and the communication module;The FPGA programmable unit is electrically connected by the DDRII slot through the phaselocked loop and the high-speed a/d conversion circuit;The optical-electric module passes sequentially through A/D conditioning circuit, high-speed a/d conversion circuit and is electrically connected through the DDRII slot and the FPGA programmable unit;The power module is to provide working power to the pcb board, control panel.

Description

A kind of Separable data acquisition system
Technical field
The utility model belongs to data collection system field, specifically a kind of Separable data acquisition system.
Background technique
With the fast development of network technology, more and more critically important is become for the acquisition of data, but at present on the market Data collection system, designed by PCB control panel using unitary design, i.e. all core devices (such as FPGA Chip) it is to be directly welded on pcb board, this mode has a problem, for example fpga chip damages, replacement not easy to repair, But the device on other pcb boards does not damage, and needs to scrap entire pcb board if when fpga chip can not repair, this Sample is given with not causing economic loss unnecessary.
Utility model content
The purpose of the utility model is to overcome the technical problems present on, provide a kind of medical bed for nursing care control system System.
To achieve the above object, the utility model adopts the following technical scheme.
A kind of Separable data acquisition system, including pcb board, control panel, power module and PC machine, the pcb board include Optical-electric module, A/D conditioning circuit, high-speed a/d conversion circuit, phaselocked loop, DDRII slot and communication module;The control panel packet Include FPGA programmable unit;The FPGA programmable unit is removably buckled in the DDRII slot, and the FPGA can Programming unit is electrically connected by the DDRII slot and the communication module;The FPGA programmable unit passes through described DDRII slot is electrically connected through the phaselocked loop and the high-speed a/d conversion circuit;The optical-electric module passes sequentially through A/D tune It manages circuit, high-speed a/d conversion circuit and is electrically connected through the DDRII slot and the FPGA programmable unit;The power supply For module to provide working power to the pcb board, control panel, the power module includes triode T1, triode T2, electricity Hinder R1, resistance R2, resistance RQ , AMP arithmetic unit, the triode T1, triode T2 emitter be grounded altogether, the triode T1 Collector and base stage be shorted after connect resistance R2 and AMP arithmetic unit positive input foot, the collector and base of the triode T2 It is extremely short connect after by resistance RQ The negative input foot of resistance R1 and AMP arithmetic unit is connected, the resistance R2, the other end of resistance R1 are total It is connected with the output pin of AMP arithmetic unit.
Further, the FPGA programmable unit uses EP4CE10F17C8 chip.
Further, the optical-electric module is PIN photodiode, the model of the PIN photodiode HPI340R2。
Further, the A/D conditioning circuit uses OPA657 operational amplifier.
Further, the communication module is RJ45 module.
Further, the high-speed a/d conversion circuit uses ADC08D500 chip.
Further, the phaselocked loop uses CD4046 chip.
The utility model the utility model has the advantages that
1, pcb board and control panel use separate design, facilitate follow-up maintenance, reduce customer using cost.
2, power module is designed using reference voltage source, and precision is high, noise is low, it is ensured that powered stable.
Detailed description of the invention
Fig. 1: the circuit structure block diagram of the utility model embodiment one.
Fig. 2: the circuit diagram of power module.
Specific embodiment
The utility model is described in detail with reference to the accompanying drawings and embodiments.
Embodiment one:
As shown in Figure 1, a kind of Separable data acquisition system, including pcb board, control panel, power module and PC machine, it is described Pcb board includes optical-electric module, A/D conditioning circuit, high-speed a/d conversion circuit, phaselocked loop, DDRII slot and communication module;It is described Control panel includes FPGA programmable unit;The FPGA programmable unit is removably buckled in the DDRII slot, institute FPGA programmable unit is stated to be electrically connected by the DDRII slot and the communication module;The FPGA programmable unit is logical The DDRII slot is crossed to be electrically connected through the phaselocked loop and the high-speed a/d conversion circuit;The optical-electric module passes sequentially through A/D conditioning circuit, high-speed a/d conversion circuit are simultaneously electrically connected through the DDRII slot and the FPGA programmable unit;It is described Power module is to provide working power to the pcb board, control panel.
Wherein, the FPGA programmable unit uses EP4CE10F17C8 chip, and the optical-electric module is two pole of PIN photoelectricity Pipe, the model HPI340R2 of the PIN photodiode.The A/D conditioning circuit uses OPA657 operational amplifier.It is described Communication module is RJ45 module.The high-speed a/d conversion circuit uses ADC08D500 chip.The phaselocked loop uses CD4046 Chip.
The FPGA programmable unit is removably buckled in the DDRII slot, such to be advantageous in that, when described When FPGA programmable unit breaks down, can directly it be replaced with good FPGA programmable unit, i.e., it directly will be good FPGA programmable unit is buckled in DDRII slot, not only facilitates follow-up maintenance in this way, but also can utilize to the full extent Original device will not cause waste unnecessary to user.
As shown in Fig. 2, the power module includes triode T1, triode T2, resistance R1, resistance R2, resistance RQ 、AMP Arithmetic unit, the triode T1, triode T2 emitter be grounded altogether, the collector and base stage of the triode T1 connect after being shorted The positive input foot of connecting resistance R2 and AMP arithmetic unit, the collector and base stage of the triode T2 pass through resistance R after being shortedQ Connection The negative input foot of resistance R1 and AMP arithmetic unit, the other end output pin with AMP arithmetic unit jointly of the resistance R2, resistance R1 It is connected, to provide working power to the component of pcb board, control panel.Power module is designed using this reference voltage source, tool There are precision height, low noise advantages, it is ensured that powered stable.
Finally, it should be noted that above embodiments are only to illustrate the utility model and not limit the utility model and retouched The technical solution stated;Therefore, although this specification the utility model is had been carried out referring to above-mentioned each embodiment it is detailed Illustrate, still, those skilled in the art should understand that, it still can modify to the utility model or equally replace It changes;And the technical solution and its improvement of all spirit and scope for not departing from the utility model, it should all cover practical new at this In the scope of the claims of type.

Claims (7)

1. a kind of Separable data acquisition system, it is characterised in that: described including pcb board, control panel, power module and PC machine Pcb board includes optical-electric module, A/D conditioning circuit, high-speed a/d conversion circuit, phaselocked loop, DDRII slot and communication module;It is described Control panel includes FPGA programmable unit;The FPGA programmable unit is removably buckled in the DDRII slot, institute FPGA programmable unit is stated to be electrically connected by the DDRII slot and the communication module;The FPGA programmable unit is logical The DDRII slot is crossed to be electrically connected through the phaselocked loop and the high-speed a/d conversion circuit;The optical-electric module passes sequentially through A/D conditioning circuit, high-speed a/d conversion circuit are simultaneously electrically connected through the DDRII slot and the FPGA programmable unit;It is described For power module to provide working power to the pcb board, control panel, the power module includes triode T1, triode T2, resistance R1, resistance R2, resistance RQ , AMP arithmetic unit, the triode T1, triode T2 emitter be grounded altogether, described three The collector and base stage of pole pipe T1 connects the positive input foot of resistance R2 and AMP arithmetic unit, the current collection of the triode T2 after being shorted Pole and base stage pass through resistance R after being shortedQ Connect resistance R1 and AMP arithmetic unit negative input foot, the resistance R2, resistance R1 it is another One end is connected with the output pin of AMP arithmetic unit jointly.
2. Separable data acquisition system according to claim 1, it is characterised in that: the FPGA programmable unit is adopted With EP4CE10F17C8 chip.
3. Separable data acquisition system according to claim 1, it is characterised in that: the optical-electric module is PIN photoelectricity Diode, the model HPI340R2 of the PIN photodiode.
4. Separable data acquisition system according to claim 1, it is characterised in that: the A/D conditioning circuit uses OPA657 operational amplifier.
5. Separable data acquisition system according to claim 1, it is characterised in that: the communication module is RJ45 mould Block.
6. Separable data acquisition system according to claim 1, it is characterised in that: the high-speed a/d conversion circuit is adopted With ADC08D500 chip.
7. Separable data acquisition system according to claim 1, it is characterised in that: the phaselocked loop uses CD4046 Chip.
CN201920682579.2U 2019-05-14 2019-05-14 A kind of Separable data acquisition system Expired - Fee Related CN209570840U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201920682579.2U CN209570840U (en) 2019-05-14 2019-05-14 A kind of Separable data acquisition system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201920682579.2U CN209570840U (en) 2019-05-14 2019-05-14 A kind of Separable data acquisition system

Publications (1)

Publication Number Publication Date
CN209570840U true CN209570840U (en) 2019-11-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201920682579.2U Expired - Fee Related CN209570840U (en) 2019-05-14 2019-05-14 A kind of Separable data acquisition system

Country Status (1)

Country Link
CN (1) CN209570840U (en)

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20191101

Termination date: 20210514

CF01 Termination of patent right due to non-payment of annual fee