WO2024036876A1

WO2024036876A1 - Memory

Info

Publication number: WO2024036876A1
Application number: PCT/CN2023/070175
Authority: WO
Inventors: 季汝敏
Original assignee: 长鑫科技集团股份有限公司
Priority date: 2022-08-17
Filing date: 2023-01-03
Publication date: 2024-02-22
Also published as: CN115050411B; CN115050411A

Abstract

Disclosed in the embodiments of the present disclosure is a memory. The memory comprises at least one array area, the array area comprising a storage body area, a first latch area and a second latch area, wherein the first latch area is coupled to a first end of the storage body area, and the second latch area is coupled to a second end of the storage body area; the first end and the second end of the storage body area are two opposite ends in a first direction; and the first latch area and the second latch area are used for latching fuse data and transmitting same to the storage body area.

Description

a memory

Cross-references to related applications

This disclosure is based on a Chinese patent application with the application number 202210984495.0, the filing date is August 17, 2022, and the invention name is "a memory", and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is in This disclosure is incorporated by reference.

Technical field

The present disclosure relates to, but is not limited to, a memory.

Background technique

In integrated circuits, one-time programmable devices based on Anti-fuse technology are widely used in various types of chips. An antifuse array is installed in the chip. When the chip is powered on and started, the fuse data stored in the antifuse array will be sent through the built-in transmission circuit and latched where it needs to be used.

Contents of the invention

In view of this, embodiments of the present disclosure provide a memory that can save wiring settings, reduce delays and losses during the transmission process of fuse data, and save power consumption.

The technical solution of the embodiment of the present disclosure is implemented as follows:

Embodiments of the present disclosure provide a memory, which includes at least one array area; the array area includes: a memory bank area, a first latch area, and a second latch area; wherein the first latch area Coupled to the first end of the memory bank area, the second latch area is coupled to the second end of the memory bank area; the first end and the second end of the memory bank area are along the first Two opposite ends; the first latch area and the second latch area are used to latch and transmit fuse data to the memory bank area.

In the above scheme, the memory bank area includes: N memory bank groups; the first latch area includes: N first latch units; the second latch area includes: N second latch units ; N memory bank groups, N first latch units and N second latch units are respectively arranged in sequence along the second direction; the second direction is perpendicular to the first direction; The N memory bank groups are coupled to the N first latch units in a one-to-one correspondence, and are coupled to the N second latch units in a one-to-one correspondence.

In the above solution, the memory further includes: at least one antifuse array and at least one signal path; at least one of the signal paths extends along the first direction and is disposed opposite the memory bank area along the second direction. At least one of the two ends; the antifuse array, used to store and send the fuse data; the signal path, respectively coupled to the antifuse array, the first latch area and the A second latch area is used to transmit the fuse data to the first latch area and the second latch area.

In the above scheme, the fuse data sent by the anti-fuse array is in a parallel state; the memory further includes: at least one serializer; the serializer is disposed between the anti-fuse array and the The antifuse array and the signal path are respectively coupled between the signal paths for converting the fuse data sent by the antifuse array into a serial state and transmitting it to the signal path.

In the above solution, the memory further includes: at least one first parallelizer and at least one second parallelizer; the first parallelizer is disposed between the signal path and the first latch area, and is coupled respectively. Connect the signal path and the first latch area for converting the fuse data transmitted by the signal path into a parallel state and transmit it to the first latch area; the second parallelizer , disposed between the signal path and the second latch area, respectively coupled to the signal path and the second latch area, for converting the fuse data transmitted by the signal path into parallel status and transferred to the second latch area.

In the above solution, the number of the array areas is two, including: a first array area and a second array area; the first array area and the second array area are arranged oppositely along the first direction; at least one The antifuse array is disposed between the first array area and the second array area.

In the above solution, the number of the antifuse array is one; the number of the signal paths is two, including: a first signal path and a second signal path; the first signal path is provided in the first array The third end of the area; the first signal path is coupled to the antifuse array, and the first signal path is also coupled to the first latch area and the third in the first array area respectively. Two latch areas; the second signal path is provided at the third end of the second array area; the second signal path is coupled to the antifuse array, and the second signal path is also coupled to the the first latch area and the second latch area in the second array area.

In the above solution, the number of the anti-fuse arrays is two, including: a first anti-fuse array and a second anti-fuse array; the number of the signal paths is four, including: a first signal path, a second anti-fuse array. a signal path, a third signal path and a fourth signal path; the first signal path is provided at the third end of the first array area; the first signal path is coupled to the first antifuse array, so The first signal path is also coupled to the first latch area and the second latch area in the first array area respectively; the second signal path is provided in a third part of the second array area. end; the second signal path is coupled to the first antifuse array, and the second signal path is also coupled to the first latch area and the second latch area in the second array area respectively. storage area; the third signal path is provided at the fourth end of the first array area; the third signal path is coupled to the second antifuse array, and the third signal path is also coupled to the The first latch area and the second latch area in the first array area; the fourth signal path is provided at the fourth end of the second array area; the fourth signal path is coupled The second antifuse array and the fourth signal path are also respectively coupled to the first latch area and the second latch area in the second array area.

In the above solution, the number of the array area is one; at least one anti-fuse array is disposed on a side close to the first end of the array area.

In the above solution, the number of the anti-fuse array is one; the number of the signal paths is one; the signal path is provided at the third end of the array area; the signal path is coupled to the anti-fuse Array, the signal path is further coupled to the first latch area and the second latch area in the array area respectively.

In the above solution, the number of the antifuse arrays is two, including: a first antifuse array and a second antifuse array; the number of the signal paths is two, including: a first signal path and a second antifuse array. Two signal paths; the first signal path is provided at the third end of the array area; the first signal path is coupled to the first antifuse array, and the first signal path is also coupled to the The first latch area and the second latch area in the array area; the second signal path is provided at the fourth end of the array area; the second signal path is coupled to the second inverter In the fuse array, the second signal path is also coupled to the first latch area and the second latch area in the array area respectively.

In the above solution, the fuse data sent by the antifuse array includes: 2 ⁱ fuse sub-data; the serializer includes: 2 ⁱ sub-data transmission paths; 2 ⁱ sub-data transmission paths , receiving 2 ⁱ fuse sub-data in one-to-one correspondence, and receiving 2 ⁱ sub-data control signals in one-to-one correspondence; each of the sub-data transmission paths is used to control the sub-data in response to its corresponding reception The signal is transmitted corresponding to the received fuse sub-data to the output end of the serializer, so as to convert the fuse data sent by the anti-fuse array into a serial state.

In the above solution, the serializer also includes: i D latches and 2 ⁱ AND gate units; wherein, the clock input end of the first D latch receives a serial clock signal; each The inverting output terminal of the D latch is electrically connected to its data input terminal; the non-inverting output terminal of each D latch is electrically connected to the clock input terminal of the next D latch; each AND gate The i input terminals of the unit are correspondingly coupled to i output terminals among the non-inverting output terminals and the inverting output terminals of i D latches; at least one input terminal between each two AND gate units is connected to the corresponding Different output terminals of the D latches; 2 ⁱ AND gate units output 2 ⁱ sub-data control signals in one-to-one correspondence.

In the above solution, the serializer further includes: 2 ⁱ sub-data latches; the output terminals of the 2 ⁱ sub-data latches are coupled to the input terminals of the 2 ⁱ sub-data transmission paths in one-to-one correspondence. ; 2 ⁱ sub-data latches, used to receive 2 ⁱ fuse sub-data in one-to-one correspondence, latch and transmit the 2 ⁱ fuse sub-data to 2 ⁱ sub-data transmission path.

In the above solution, the memory is a dynamic random access memory (DRAM).

It can be seen that the embodiment of the present disclosure provides a memory, including at least one array area; the array area includes: a memory bank area, a first latch area and a second latch area; wherein the first latch area is coupled to The first end of the memory bank area and the second latch area are coupled to the second end of the memory bank area; the first end and the second end of the memory bank area are two opposite ends along the first direction; the first latch area and a second latch area for latching and transmitting fuse data to the memory bank area. It can be understood that a part of the memory bank area close to the first end can obtain fuse data from the first latch area, and a part of the memory bank area close to the second end can obtain fuse data from the second latch area. In this way, each part of the memory bank area can obtain the fuse data from a relatively nearby latch area, thereby saving wiring settings, reducing the delay and loss of the fuse data during the transmission process, and saving power consumption. .

Description of drawings

Figure 1 is an illustration of antifuse technology;

Figure 2 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure;

Figure 3 is a schematic structural diagram of a memory bank area in a memory provided by an embodiment of the present disclosure;

Figure 4 is a schematic structural diagram 2 of a memory provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram three of a memory provided by an embodiment of the present disclosure;

Figure 6 is a schematic structural diagram 4 of a memory provided by an embodiment of the present disclosure;

Figure 7 is a schematic structural diagram 5 of a memory provided by an embodiment of the present disclosure;

Figure 8 is a schematic structural diagram 6 of a memory provided by an embodiment of the present disclosure;

Figure 9 is a schematic structural diagram of a memory provided by an embodiment of the present disclosure;

Figure 10 is a schematic structural diagram 8 of a memory provided by an embodiment of the present disclosure;

Figure 11 is a schematic structural diagram 9 of a memory provided by an embodiment of the present disclosure;

Figure 12 is a schematic structural diagram of a serializer in a memory provided by an embodiment of the present disclosure;

Figure 13 is a schematic structural diagram 2 of a serializer in a memory provided by an embodiment of the present disclosure;

Figure 14 is a schematic structural diagram three of a serializer in a memory provided by an embodiment of the present disclosure;

Figure 15 is a signal schematic diagram 1 of a serializer in a memory provided by an embodiment of the present disclosure;

Figure 16 is a schematic structural diagram 4 of a serializer in a memory provided by an embodiment of the present disclosure;

Figure 17 is a second signal schematic diagram of a serializer in a memory provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated below in conjunction with the accompanying drawings and examples. The described embodiments should not be regarded as limiting the present disclosure. Those of ordinary skill in the art will All other embodiments obtained without creative efforts belong to the scope of protection of this disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

If a similar description of "first/second" appears in the invention document, add the following explanation. In the following description, the terms "first\second\third" involved are only used to distinguish similar objects and do not mean Regarding the specific ordering of objects, it is understood that "first\second\third" may interchange the specific order or sequence where permitted, so that the embodiments of the disclosure described here can be used in other ways than those shown in the figures here. may be performed in any order other than that shown or described.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

One-time programmable (OTP, One Time Programmable) devices based on antifuse technology (hereinafter referred to as antifuse devices) can change the electrical characteristics from a high resistance state to a low resistance state, thereby adjusting the circuit and change. Referring to Figure 1, the antifuse transistor Mf is an antifuse device and has a high resistance in an unprogrammed state. When the anti-fuse transistor Mf receives the programming signal FsBln, the anti-fuse transistor Mf is broken down and then exhibits a lower resistance, that is, the state of the anti-fuse transistor Mf becomes programmed.

Antifuse devices are widely used in various types of chips. For example, antifuses can be used in DRAM (Dynamic Random Access Memory) chips to store defective memory cell address information, thereby achieving redundant replacement (including row replacement and column replacement); antifuses can also be programmed, This enables precise modification of various internal parameters of the chip (such as voltage, current, frequency, etc.). An antifuse array is installed in the chip. When the chip is powered on and started, the fuse data stored in the antifuse array will be sent through the built-in transmission circuit and latched where it needs to be used. Fuse data may include address information that represents redundant replacement, or code that adjusts parameters within the chip.

FIG. 2 is an optional structural schematic diagram of a memory provided by an embodiment of the present disclosure. As shown in FIG. 2 , the memory 80 includes at least one array area 30 . The array area 30 includes: a memory bank area 31, a first latch area 32 and a second latch area 33. The first latch area 32 is coupled to the first end of the memory bank area 31 , and the second latch area 33 is coupled to the second end of the memory bank area 31 . The first end and the second end of the memory bank area 31 are two opposite ends along the first direction Y. The first latch area 32 and the second latch area 33 are used to latch and transmit the fuse data to the memory bank area 31 .

It should be noted that coupling in the embodiments of the present disclosure includes direct electrical connection, or electrical connection through other components. No further details will be given below.

In the embodiment of the present disclosure, the first end of the memory bank area 31 is coupled to a first latch area 32, and the first latch area 32 can transmit fuse data to a partial area of the memory bank area 31 close to the first end; Correspondingly, the second end of the memory bank area 31 is coupled to a second latch area 33, and the second latch area 33 can transmit fuse data to a partial area of the memory bank area 31 close to the second end. Here, the fuse data may include address information representing redundant replacement, or a code for adjusting parameters within the chip.

It can be understood that each part in the memory bank area 31 can obtain the fuse data from a relatively close latch area, thereby saving wiring settings and reducing the delay and loss of the fuse data during the transmission process. , save power consumption.

In some embodiments of the present disclosure, with reference to FIG. 2 and FIG. 3 , the memory bank area 31 includes N memory bank groups 311 , the first latch area 32 includes N first latch units 321 , and the second latch area 33 N second latch units 331 are included. N memory bank groups (Bank Group) 311, N first latch units 321 and N second latch units 331 are respectively arranged in sequence along the second direction X, where the second direction X is perpendicular to the first direction Y . The N memory bank groups 311 are coupled to the N first latch units 321 in a one-to-one correspondence, and are coupled to the N second latch units 331 in a one-to-one correspondence.

In the embodiment of the present disclosure, referring to Figure 3, N memory bank groups 311 are arranged in sequence along the second direction X. Correspondingly, N first latch units 321 are also arranged in sequence along the second direction X, and N second The latch units 331 are also sequentially arranged along the second direction X. Each memory bank group 311 is coupled to a first latch unit 321 and a second latch unit 331 respectively.

It can be understood that the partial area of each memory bank group 311 close to the first latch unit 321 can obtain fuse data from its corresponding first latch unit 321; correspondingly, the fuse data in each memory bank group 311 In some areas close to the second latch unit 331, the fuse data can be obtained from its corresponding second latch unit 331, thereby making the layout (wiring design) simpler and easier; at the same time, the signal transmission line that transmits the fuse data The nearest connection avoids the signal transmission line passing through most areas of the memory bank 311, ensuring that the length of the signal transmission line will not be too long, thus reducing the delay and loss of the fuse data during the transmission process and saving power. Consumption.

In some embodiments of the present disclosure, the memory 80 shown in FIG. 2 further includes: at least one antifuse array and at least one signal path. At least one signal path extends along the first direction Y and is disposed at at least one end of two opposite ends of the memory body area along the second direction X. Among them, the anti-fuse array is used to store and send fuse data; the signal path is respectively coupled to the anti-fuse array, the first latch area and the second latch area, and is used to transmit the fuse data to the first latch area. storage area and the second latch area.

In some embodiments of the present disclosure, the memory 80 shown in FIG. 2 further includes: at least one serializer. The serializer is disposed between the antifuse array and the signal path, and the serializer is coupled to the antifuse array and the signal path respectively. The serializer is used to convert the fuse data from the antifuse array into a serial state and transmit it to the signal path.

In some embodiments of the present disclosure, the memory 80 shown in FIG. 2 further includes: at least one first parallelizer and at least one second parallelist. The first parallelizer is disposed between the signal path and the first latch area, and the first parallelist is coupled to the signal path and the first latch area respectively. The first parallelizer is used to convert the fuse data transmitted by the signal path into a parallel state and transmit it to the first latch area. The second parallelizer is disposed between the signal path and the second latch area, and the second parallelist is coupled to the signal path and the second latch area respectively. The second parallelizer is used to convert the fuse data transmitted by the signal path into a parallel state and transmit it to the second latch area.

Figures 4 to 11 are optional structural schematic diagrams of a memory provided by embodiments of the present disclosure, which will be described below with reference to Figures 4 to 11 .

It should be noted that Figures 4 to 11 illustrate the structure of the array area in the case of N=8. That is to say, in Figures 4 to 11, each array area includes 8 memory bank groups, 8 first latch units and 8 second latch units. In some embodiments, N can also be other values, which are not limited here.

In some embodiments of the present disclosure, referring to FIG. 4 or FIG. 5 , the number of array areas is two, including: a first array area 41 and a second array area 42 . The first array area 41 and the second array area 42 are arranged oppositely along the first direction Y. At least one antifuse array (AB1 and/or AB2) is disposed between the first array area 41 and the second array area 42 .

In the embodiment of the present disclosure, the antifuse array (AB1 and/or AB2) is disposed between the first array area 41 and the second array area 42, and can provide fuses for the first array area 41 and the second array area 42 at the same time. data. The fuse data is transmitted to the first latch area 32 and the second latch area 33 via the signal path, and then to each memory bank group BG0 to BG15.

It should be noted that the structure shown in Figure 4 or Figure 5 can be applied to DDR (double rate synchronous dynamic random access memory).

In some embodiments of the present disclosure, referring to Figure 4, the number of antifuse arrays is one, which is the antifuse array AB1; the number of signal paths is two, including: a first signal path P1 and a second signal path P2. The first signal path P1 is provided at the third end of the first array area 41 , and the third end of the first array area 41 is one side of the first array area 41 in the second direction X; the first signal path P1 is coupled to The antifuse array AB1 and the first signal path P1 are also coupled to the first latch area 32 and the second latch area 33 in the first array area 41 respectively. The second signal path P2 is provided at the third end of the second array area 42 , and the third end of the second array area 42 is one side of the second array area 42 in the second direction X, where the first array area 41 The third end of the second array area 42 and the third end of the second array area 42 are on the same side of the first array area 41 and the second array area 42 in the second direction X; the second signal path P2 is coupled to the antifuse array AB1, The second signal path P2 is also coupled to the first latch area 32 and the second latch area 33 in the second array area 42 respectively.

The arrow in Figure 4 shows the transmission path of fuse data. Referring to Figure 4, the anti-fuse array AB1 sends the fuse data, and the fuse data is transmitted to the first array area 41 via the first signal path P1. a latch area 32 and a second latch area 33; at the same time, the fuse data is transmitted to the first latch area 32 and the second latch area 33 in the second array area 42 via the second signal path P2.

In the embodiment of the present disclosure, referring to FIG. 4 , the eight memory bank groups BG0 to BG7 in the first array area 41 respectively obtain fuse data from the first latch unit 321 and the second latch unit 331 coupled thereto. Correspondingly, the eight memory bank groups BG8 to BG15 in the second array area 42 respectively obtain fuse data from the first latch unit 321 and the second latch unit 331 coupled thereto.

It can be understood that the signal transmission lines for transmitting fuse data in each part of the memory bank groups BG0 to BG15 can be electrically connected to the first latch unit 321 and the second latch unit 331 nearby to obtain the fuse data, so that the layout (Wiring design) is simpler and easier; at the same time, the nearby connection of the signal transmission line that transmits fuse data avoids the signal transmission line from passing through most areas of the memory bank group BG0 ~ BG15, ensuring that the length of the signal transmission line will not be too long. Therefore, the delay and loss during the transmission process of fuse data are reduced, and power consumption is saved.

In some embodiments of the present disclosure, referring to Figure 5, the number of antifuse arrays is two, including: a first antifuse array AB1 and a second antifuse array AB2; the number of signal paths is four, including: The first signal path P1, the second signal path P2, the third signal path P3 and the fourth signal path P4. The first signal path P1 is provided at the third end of the first array area 41 , and the third end of the first array area 41 is one side of the first array area 41 in the second direction X; the first signal path P1 is coupled to The first antifuse array AB1 and the first signal path P1 are also coupled to the first latch area 32 and the second latch area 33 in the first array area 41 respectively. The second signal path P2 is provided at the third end of the second array area 42 , and the third end of the second array area 42 is one side of the second array area 42 in the second direction X, where the first array area 41 The third end of the second array area 42 and the third end of the second array area 42 are on the same side of the first array area 41 and the second array area 42 in the second direction X; the second signal path P2 is coupled to the first antifuse array AB1 and the second signal path P2 are also respectively coupled to the first latch area 32 and the second latch area 33 in the second array area 42 . The third signal path P3 is provided at the fourth end of the first array area 41, and the fourth end of the first array area 41 is the other side of the first array area 41 in the second direction X; the third signal path P3 is coupled to The second antifuse array AB2 and the third signal path P3 are also coupled to the first latch area 32 and the second latch area 33 in the first array area 41 respectively. The fourth signal path P4 is provided at the fourth end of the second array area 42 , and the fourth end of the second array area 42 is the other side of the second array area 42 in the second direction X, where the first array area 41 The fourth end and the fourth end of the second array area 42 are the same side of the first array area 41 and the second array area 42 in the second direction X; the fourth signal path P4 is coupled to the second antifuse array AB2 , the fourth signal path P2 is also coupled to the first latch area 32 and the second latch area 33 in the second array area 42 respectively.

The arrow in Figure 5 shows the transmission path of fuse data. Referring to Figure 5, the first anti-fuse array AB1 sends fuse data, and the fuse data is transmitted to the first array area 41 via the first signal path P1. The first latch area 32 and the second latch area 33; at the same time, the fuse data sent by the first anti-fuse array AB1 is transmitted to the first latch area in the second array area 42 via the second signal path P2 32 and the second latch area 33. On the other hand, the second antifuse array AB2 sends fuse data, and the fuse data is transmitted to the first latch area 32 and the second latch area 33 in the first array area 41 via the third signal path P3; At the same time, the fuse data sent by the second antifuse array AB2 is transmitted to the first latch area 32 and the second latch area 33 in the second array area 42 via the fourth signal path P4.

In the embodiment of the present disclosure, referring to FIG. 5 , the first antifuse array AB1 and the second antifuse array AB2 simultaneously send and transmit fuse data when powered on. The memory bank groups BG0 to BG3 in the first array area 41 and the memory bank groups BG8 to BG11 in the second array area 42 will obtain the fuse data sent by the first antifuse array AB1. Correspondingly, the memory bank groups BG4 to BG7 in the first array area 41 and the memory bank groups BG12 to BG15 in the second array area 42 will obtain the fuse data sent by the second antifuse array AB2. In this way, the transmission of fuse data can be completed more quickly, reducing the delay and loss of fuse data during the transmission process, and saving power consumption.

In some embodiments of the present disclosure, with reference to Figures 4 and 6, strings are provided between the antifuse array AB1 and the first signal path P1, and between the antifuse array AB1 and the second signal path P2. Mobile device p2s. The fuse data sent by the antifuse array AB1 is in a parallel state; the serializer p2s can convert the fuse data in the parallel state into a serial state, and transmit the fuse data in the serial state to the first signal path P1 and the first signal path P1. Two signal paths P2.

Correspondingly, continuing to combine FIG. 4 and FIG. 6 , between the first signal path P1 and the first latch area 32 in the first array area 41 , and between the second signal path P2 and the first latch area 32 in the second array area 42 The first parallelizer s2p is disposed between the latch areas 32; between the first signal path P1 and the second latch area 33 in the first array area 41, and between the second signal path P2 and the second array area The second parallelizer s2p is arranged between the second latch areas 33 in 42. The first parallelizer and the second parallelizer s2p may convert the fuse data in the serial state transmitted in the signal path into the parallel state, and transmit the fuse data in the parallel state to the first latch area 32 and the second latch District 33.

In some embodiments of the present disclosure, in conjunction with Figures 5 and 7, between the first antifuse array AB1 and the first signal path P1, and between the first antifuse array AB1 and the second signal path P2, Furthermore, a serializer p2s is provided between the second antifuse array AB2 and the third signal path P3, and between the second antifuse array AB2 and the fourth signal path P4. The fuse data sent by the first antifuse array AB1 and the second antifuse array AB2 is in a parallel state; the serializer p2s can convert the fuse data in the parallel state into a serial state, and convert the fuse data in the serial state into a serial state. Data is transmitted to each signal path P1 to P4.

Correspondingly, continuing to combine FIG. 5 and FIG. 7 , between the first signal path P1 and the first latch area 32 in the first array area 41 , and between the second signal path P2 and the first latch area 32 in the second array area 42 between the latch area 32, and between the third signal path P3 and the first latch area 32 in the first array area 41, and between the fourth signal path P4 and the first latch in the second array area 42 The first parallelizer s2p is disposed between the areas 32; between the first signal path P1 and the second latch area 33 in the first array area 41, and between the second signal path P2 and the second array area 42 between the second latch area 33 in the first array area 41, and between the third signal path P3 and the second latch area 33 in the first array area 41, and between the fourth signal path P4 and the Between the two latch areas 33, a second parallelizer s2p is arranged. The first parallelizer and the second parallelizer s2p may convert the fuse data in the serial state transmitted in the signal path into the parallel state, and transmit the fuse data in the parallel state to the first latch area 32 and the second latch District 33.

It can be understood that through the serializer and parallelizer, the fuse data is transmitted in each signal path in a serial state, that is, the fuse data is transmitted in each signal path in a single-bit state. Since the data in the serial state is transmitted Fewer transmission lines are required, so the number of wirings at the edge of the chip can be reduced, thereby reducing the chip area and improving chip integration.

In some embodiments of the present disclosure, referring to FIG. 8 or FIG. 9 , the number of array areas is one, that is, array area 41 . At least one antifuse array (AB1 and/or AB2) is disposed on a side close to the first end of the array area 41 .

In the embodiment of the present disclosure, the antifuse array (AB1 and/or AB2) is disposed on a side close to the first end of the array area 41 and can provide fuse data for the array area 41 . The fuse data is transmitted to the first latch area 32 and the second latch area 33 via the signal path, and then to each memory bank group BG0 to BG7.

It should be noted that the structure shown in Figure 8 or Figure 9 can be applied to LPDDR (Low Power Consumption Double Rate Dynamic Random Memory).

In some embodiments of the present disclosure, referring to FIG. 8 , the number of antifuse arrays is one, which is the antifuse array AB1; the number of signal paths is one, which is the signal path P1. The signal path P1 is provided at the third end of the array area 41, and the third end of the array area 41 is one side of the array area 41 in the second direction X; the signal path P1 is coupled to the antifuse array AB1, and the signal path P1 is also The first latch area 32 and the second latch area 33 in the array area 41 are respectively coupled.

The arrow in Figure 8 shows the transmission path of fuse data. Referring to Figure 8, the anti-fuse array AB1 sends the fuse data, and the fuse data is transmitted to the first latch area in the array area 41 via the signal path P1. 32 and the second latch area 33.

In the embodiment of the present disclosure, referring to FIG. 8 , eight memory bank groups BG0 to BG7 in the array area 41 respectively obtain fuse data from the first latch unit 321 and the second latch unit 331 coupled thereto. In this way, the signal transmission lines that transmit fuse data in each part of the memory bank groups BG0 to BG7 can be electrically connected to the first latch unit 321 or the second latch unit 331 nearby to obtain the fuse data, so that the layout (wiring design) ) is simpler and easier to implement; at the same time, the nearby connection of the signal transmission line that transmits fuse data avoids the signal transmission line from passing through most areas of the memory bank group BG0 to BG7, ensuring that the length of the signal transmission line will not be too long, thereby reducing The delay and loss during the transmission process of fuse data are reduced, and power consumption is saved.

In some embodiments of the present disclosure, referring to FIG. 9 , the number of antifuse arrays is two, including: a first antifuse array AB1 and a second antifuse array AB2; the number of signal paths is two, including : first signal path P1 and second signal path P2. The first signal path P1 is provided at the third end of the array area 41, and the third end of the array area 41 is one side of the array area 41 in the second direction X; the first signal path P1 is coupled to the first antifuse array AB1, the first signal path P1 is also coupled to the first latch area 32 and the second latch area 33 in the array area 41 respectively. The second signal path P2 is provided at the fourth end of the array area 41. The fourth end of the array area 41 is the other side of the array area 41 in the second direction X; the second signal path P2 is coupled to the second antifuse. The array AB2 and the second signal path P2 are also coupled to the first latch area 32 and the second latch area 33 in the array area 41 respectively.

The arrow in Figure 9 shows the transmission path of fuse data. Referring to Figure 9, the first anti-fuse array AB1 sends the fuse data, and the fuse data is transmitted to the first anti-fuse array AB1 in the array area 41 via the first signal path P1. a latch area 32 and a second latch area 33. On the other hand, the second antifuse array AB2 sends fuse data, and the fuse data is transmitted to the first latch area 32 and the second latch area 33 in the array area 41 via the second signal path P2.

In the embodiment of the present disclosure, referring to FIG. 9 , the first antifuse array AB1 and the second antifuse array AB2 simultaneously send and transmit fuse data when powered on. The memory bank groups BG0˜BG3 in the array area 41 will obtain the fuse data sent by the first antifuse array AB1. Correspondingly, the memory bank groups BG4 to BG7 in the array area 41 will obtain the fuse data sent by the second antifuse array AB2. In this way, the transmission of fuse data can be completed more quickly, reducing the delay and loss of fuse data during the transmission process, and saving power consumption.

In some embodiments of the present disclosure, with reference to Figures 8 and 10, a serializer p2s is provided between the antifuse array AB1 and the signal path P1. The fuse data sent by the antifuse array AB1 is in a parallel state; the serializer p2s can convert the fuse data in the parallel state into a serial state and transmit the fuse data in the serial state to the signal path P1.

Correspondingly, continuing to combine Figures 8 and 10, a first parallelist s2p is provided between the signal path P1 and the first latch area 32 in the array area 41; the signal path P1 and the second latch in the array area 41 Between areas 33, a second parallelizer s2p is provided. The first parallelizer and the second parallelizer s2p may convert the fuse data in the serial state transmitted in the signal path into the parallel state, and transmit the fuse data in the parallel state to the first latch area 32 and the second latch District 33.

In some embodiments of the present disclosure, in conjunction with Figures 9 and 11, between the first antifuse array AB1 and the first signal path P1, and between the first antifuse array AB1 and the second signal path P2, Both have serializer p2s set up. The fuse data sent by the first antifuse array AB1 and the second antifuse array AB2 is in a parallel state; the serializer p2s can convert the fuse data in the parallel state into a serial state, and convert the fuse data in the serial state into a serial state. Data is transmitted to the first signal path P1 and the second signal path P2.

Correspondingly, continuing to combine FIG. 9 and FIG. 11 , between the first signal path P1 and the first latch area 32 in the array area 41 , and between the second signal path P2 and the first latch area 32 in the array area 41 between the first parallelizer s2p; between the first signal path P1 and the second latch area 33 in the array area 41, and between the second signal path P2 and the second latch area in the array area 41 33, there is a second parallelizer s2p. The first parallelizer and the second parallelizer s2p may convert the fuse data in the serial state transmitted in the signal path into the parallel state, and transmit the fuse data in the parallel state to the first latch area 32 and the second latch District 33.

In some embodiments of the present disclosure, the fuse data sent by the antifuse array includes 2 ⁱ fuse sub-data, and accordingly, the serializer includes 2 ⁱ sub-data transmission paths. Among them, the 2 ⁱ sub-data transmission paths correspond to the 2 ⁱ fuse sub-data in the receiving signal path one-to-one, and the 2 ⁱ sub-data transmission paths also receive the 2 ⁱ sub-data control signals in a one-to-one correspondence. Each sub-data transmission path is used to respond to its corresponding received sub-data control signal and transmit its corresponding received fuse sub-data to the output end of the serializer, so as to convert the fuse data sent by the anti-fuse array into serial status.

Referring to Figure 12, Figure 12 illustrates the 8 sub-data transmission paths Path0~Path7 included in the serializer when i=3. The 8 sub-data transmission paths Path0~Path7 receive 8 fuse sub-data one-to-one. DIN0~DIN7, the 8 sub-data transmission paths Path0~Path7 also receive 8 sub-data control signals SEL0~SEL7 in one-to-one correspondence. When the sub-data control signals SEL0~SEL7 are at high level respectively, the corresponding sub-data transmission paths Path0~Path7 can be in the on state one after another, thereby transmitting the corresponding parallel fuse sub-data DIN0~DIN7 to the serial port one after another. The output end of the device then outputs the serial fuse sub-data DIN0~DIN7.

In some embodiments of the present disclosure, the serializer further includes: i D latches and 2 ⁱ AND gate units. Among them, the clock input terminal of the first D latch receives the serial clock signal; the inverting output terminal of each D latch is electrically connected to its data input terminal, and the non-inverting output terminal of each D latch is electrically connected to The clock input terminal of a D latch; the i input terminals of each AND gate unit correspond to i output terminals coupled to the non-inverting output terminals and inverting output terminals of i D latches; each two AND At least one input terminal between the gate units is connected to different output terminals of the corresponding D latch; 2 ⁱ AND gate units output 2 ⁱ sub-data control signals in one-to-one correspondence.

Referring to Figure 13 and Figure 14, Figure 13 illustrates the eight AND gate units A0~A7 included in the serializer when i=3; Figure 14 illustrates the serializer when i=3. There are three D latches L1 ~ L3 included in the device. The clock input terminal C of the D latch L1 receives the serial clock signal ClkSer, the non-inverting output terminal Q of the D latch L1 is electrically connected to the clock input terminal C of the D latch L2, and the non-inverting output terminal Q of the D latch L2 Electrically connected to the clock input terminal C of the D latch L3. The inverting output terminals Q of the D latches L1 to L3 are electrically connected to their data input terminals D.

Continuing to refer to Figures 13 and 14, the non-inverting output terminal Q and the inverting output terminal Q of the D latch L1 are electrically connected to the transmission lines Q0 and Q0b respectively, and the non-inverting output terminal Q and the inverting output terminal Q of the D latch L2 are electrically connected respectively. To the transmission lines Q1 and Q1b, the non-inverting output terminal Q and the inverting output terminal Q of the D latch L2 are electrically connected to the transmission lines Q2 and Q2b respectively. The three input terminals of the AND gate unit A0 are electrically connected to the transmission lines Q0, Q1 and Q2 respectively. The AND gate unit A0 outputs the sub-data control signal SEL0; the three input terminals of the AND gate unit A1 are electrically connected to the transmission lines Q0b, Q1 and Q2 respectively. , the AND gate unit A1 outputs the sub-data control signal SEL1; the three input terminals of the AND gate unit A2 are electrically connected to the transmission lines Q0, Q1b and Q2 respectively, the AND gate unit A2 outputs the sub-data control signal SEL2; the three input terminals of the AND gate unit A3 The input terminals are electrically connected to the transmission lines Q0b, Q1b and Q2 respectively, and the AND gate unit A3 outputs the sub-data control signal SEL3; the three input terminals of the AND gate unit A4 are electrically connected to the transmission lines Q0, Q1 and Q2b respectively, and the AND gate unit A4 outputs the sub-data control signal SEL3. Data control signal SEL4; the three input terminals of the AND gate unit A5 are electrically connected to the transmission lines Q0b, Q1 and Q2b respectively, and the AND gate unit A5 outputs the sub-data control signal SEL5; the three input terminals of the AND gate unit A6 are electrically connected to the transmission lines respectively. Q0, Q1b and Q2b, the AND gate unit A6 outputs the sub-data control signal SEL6; the three input terminals of the AND gate unit A7 are electrically connected to the transmission lines Q0b, Q1b and Q2b respectively, and the AND gate unit A7 outputs the sub-data control signal SEL7.

Figure 15 is a schematic diagram of signals corresponding to Figures 13 and 14, which will be described with reference to Figures 13 to 15. Triggered by the serial clock signal ClkSer, the D latches L1~L3 output signals to the transmission lines Q0, Q0b, Q1, Q1b, Q2 and Q2b. It should be noted here that the signal waveform on the transmission line Q0b is different from that on the transmission line Q0. The signal waveform is inverted. The signal waveform on the transmission line Q1b is inverted with the signal waveform on the transmission line Q1. The signal waveform on the transmission line Q2b is inverted with the signal waveform on the transmission line Q2. The signal waveforms of Q0b, Q1b and Q2b are not shown in Figure 15. Shows.

Furthermore, referring to FIG. 15 , the waveforms of the sub-data control signals SEL0 to SEL7 output by the AND gate units A0 to A7 are pulses arranged in sequence. In this way, combining Figure 12 and Figure 15, the pulses in the sub-data control signals SEL0~SEL7 will control the corresponding sub-data transmission paths Path0~Path7 to be in a conductive state. Therefore, the sub-data transmission paths Path0~Path7 will be turned on in sequence. And only one sub-data transmission path is turned on at the same time, thus ensuring that each fuse sub-data can be transmitted independently, avoiding the simultaneous transmission of different fuse sub-data and mutual interference, ensuring the accuracy of the output serial data. Integrity.

In some embodiments of the present disclosure, the serializer further includes: 2 ⁱ sub-data latches. The output terminals of 2 ⁱ sub-data latches are coupled to the input terminals of 2 ⁱ sub-data transmission paths in one-to-one correspondence; the 2 ⁱ sub-data latches are used to receive 2 ⁱ fuse sub-data in one-to-one correspondence and convert the 2 ⁱ The fuse sub-data is latched and transmitted to 2 ⁱ sub-data transmission paths.

Referring to Figures 16 and 17, Figure 17 is a signal diagram corresponding to Figure 16. In FIG. 16, the serializer 50 includes 2 ⁱ sub-data latches 51, and the ^{2 i} sub-data transmission paths are represented by the serial module 52. Combining Figure 16 and Figure 17, in the case of i=3, the 8 sub-data latches 51 are triggered by the latch clock signal ClkLd, latching the 8 fuse sub-data DIN<7:0> and outputting it as Fuse sub-data Datacap<7:0> and transmit it to 8 sub-data transmission paths. Furthermore, under the control of the sub-data control signals SEL0˜SEL7, the eight sub-data transmission paths output serial state fuse data from the output terminal DOUT of the serializer 50 .

In some embodiments of the present disclosure, the memory 80 shown in FIG. 2 and FIGS. 4-11 may be a dynamic random access memory DRAM.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element qualified by the statement "comprises a..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. should be covered by the protection scope of this disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a memory, including at least one array area; the array area includes: a memory bank area, a first latch area and a second latch area; wherein the first latch area is coupled to the memory bank area. The first end and the second latch area are coupled to the second end of the memory bank area; the first end and the second end of the memory bank area are opposite ends along the first direction; the first latch area and the second latch area Storage area, used to latch and transfer fuse data to the memory bank area. It can be understood that a part of the memory bank area close to the first end can obtain fuse data from the first latch area, and a part of the memory bank area close to the second end can obtain fuse data from the second latch area. In this way, each part of the memory bank area can obtain the fuse data from a relatively nearby latch area, thereby saving wiring settings, reducing the delay and loss of the fuse data during the transmission process, and saving power consumption. .

Claims

A memory, the memory includes at least one array area; the array area includes: a memory bank area, a first latch area and a second latch area; wherein,

The first latch area is coupled to the first end of the memory bank area, the second latch area is coupled to the second end of the memory bank area; the first end of the memory bank area and The second end is the two opposite ends along the first direction;

The first latch area and the second latch area are used to latch and transmit fuse data to the memory bank area.
The memory according to claim 1, wherein the memory bank area includes: N memory bank groups; the first latch area includes: N first latch units; the second latch area includes: N second latch units;

N memory bank groups, N first latch units and N second latch units are respectively arranged in sequence along the second direction; the second direction is perpendicular to the first direction;

The N memory bank groups are coupled to the N first latch units in a one-to-one correspondence, and are coupled to the N second latch units in a one-to-one correspondence.
The memory of claim 1, wherein the memory further includes: at least one antifuse array and at least one signal path;

At least one of the signal paths extends along the first direction and is provided at at least one end of two opposite ends of the memory bank area along the second direction;

The antifuse array is used to store and send the fuse data;

The signal path is respectively coupled to the antifuse array, the first latch area and the second latch area, and is used to transmit the fuse data to the first latch area and the second latch area. Describe the second latch area.
The memory of claim 3, wherein the fuse data sent by the antifuse array is in a parallel state; the memory further includes: at least one serializer;

The serializer is disposed between the antifuse array and the signal path, is coupled to the antifuse array and the signal path respectively, and is used to transmit the Fuse data is converted to serial status and transferred to the signal path.
The memory of claim 4, wherein the memory further includes: at least one first parallelizer and at least one second parallelizer;

The first parallelizer is disposed between the signal path and the first latch area, is coupled to the signal path and the first latch area respectively, and is used to transmit all the data transmitted by the signal path. The fuse data is converted into a parallel state and transmitted to the first latch area;

The second parallelizer is disposed between the signal path and the second latch area, is coupled to the signal path and the second latch area respectively, and is used to transmit all the data transmitted by the signal path. The fuse data is converted into a parallel state and transmitted to the second latch area.
The memory according to claim 3, wherein the number of the array areas is two, including: a first array area and a second array area;

The first array area and the second array area are arranged oppositely along the first direction;

At least one antifuse array is disposed between the first array area and the second array area.
The memory according to claim 6, wherein the number of the antifuse array is one; the number of the signal paths is two, including: a first signal path and a second signal path;

The first signal path is provided at the third end of the first array area; the first signal path is coupled to the antifuse array, and the first signal path is also coupled to the first array area respectively. The first latch area and the second latch area in;

The second signal path is provided at the third end of the second array area; the second signal path is coupled to the antifuse array, and the second signal path is also coupled to the second array area respectively. The first latch area and the second latch area in .
The memory according to claim 6, wherein the number of the antifuse arrays is two, including: a first antifuse array and a second antifuse array; the number of the signal paths is four, including: a first signal path, a second signal path, a third signal path and a fourth signal path;

The first signal path is provided at the third end of the first array area; the first signal path is coupled to the first antifuse array, and the first signal path is also coupled to the first the first latch area and the second latch area in the array area;

The second signal path is provided at the third end of the second array area; the second signal path is coupled to the first antifuse array, and the second signal path is also coupled to the second the first latch area and the second latch area in the array area;

The third signal path is provided at the fourth end of the first array area; the third signal path is coupled to the second antifuse array, and the third signal path is also coupled to the first the first latch area and the second latch area in the array area;

The fourth signal path is provided at the fourth end of the second array area; the fourth signal path is coupled to the second antifuse array, and the fourth signal path is also coupled to the second antifuse array respectively. The first latch area and the second latch area in the array area.
The memory of claim 3, wherein the number of the array areas is one; at least one antifuse array is disposed on a side close to the first end of the array area.
The memory according to claim 9, wherein the number of the antifuse array is one; the number of the signal paths is one;

The signal path is provided at the third end of the array area; the signal path is coupled to the antifuse array, and the signal path is also coupled to the first latch area and the first latch area in the array area respectively. The second latch area.
The memory according to claim 9, wherein the number of the antifuse arrays is two, including: a first antifuse array and a second antifuse array; the number of the signal paths is two, including : the first signal path and the second signal path;

The first signal path is provided at the third end of the array area; the first signal path is coupled to the first antifuse array, and the first signal path is also coupled to the array area. the first latch area and the second latch area;

The second signal path is provided at the fourth end of the array area; the second signal path is coupled to the second antifuse array, and the second signal path is also coupled to the array area. the first latch area and the second latch area.
The memory according to claim 4, wherein the fuse data sent by the antifuse array includes: 2 i fuse sub-data; the serializer includes: 2 i sub-data transmission paths;

2 i sub-data transmission paths receive 2 i fuse sub-data in one-to-one correspondence, and receive 2 i sub-data control signals in one-to-one correspondence; each of the sub-data transmission paths is used to respond to Corresponding to the received sub-data control signal, it transmits the corresponding received fuse sub-data to the output end of the serializer, so as to convert the fuse data sent by the anti-fuse array into serial status.
The memory according to claim 12, wherein the serializer further includes: i D latches and 2 i AND gate units; wherein,

The clock input terminal of the first D latch receives a serial clock signal; the inverting output terminal of each D latch is electrically connected to its data input terminal; the non-inverting output of each D latch The terminal is electrically connected to the clock input terminal of the next D latch;

The i input terminals of each AND gate unit correspond to i output terminals of the non-inverting output terminals and inverting output terminals coupled to i D latches; there are at least one connection between each two AND gate units. One input terminal is connected to different output terminals of the corresponding D latch; 2 i AND gate units output 2 i sub-data control signals in one-to-one correspondence.
The memory of claim 12, wherein the serializer further includes: 2 i sub-data latches;

The output terminals of 2 i sub-data latches are coupled to the input terminals of 2 i sub-data transmission paths in one-to-one correspondence; the 2 i sub-data latches are used to receive 2 i in one-to-one correspondence 2 i fuse sub-data are latched and transmitted to 2 i sub-data transmission paths.
The memory according to any one of claims 1 to 14, wherein the memory is a dynamic random access memory (DRAM).