JP2005339733A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device permitting to freely decide a location of a place for arranging a redundancy fuse block. <P>SOLUTION: The semiconductor storage device is provided with: a memory cell array 100; a row decoder 12 and a column decoder 14; a row fuse block 24 and a column fuse block 26 which output redundancy replacement information on word lines and column selection lines; a replacement control circuits 20 and 22 for controlling spare replacement of the word lines and the column selection lines based on the redundancy replacement information; a clock generation circuit 70 for generating an internal clock signal FTCLK; a parallel-serial converter circuit 66 for rows and a serial-parallel converter circuit 62 for rows for performing serial conversion and parallel conversion of the redundancy replacement information of the word lines and sequentially transferring the information to the replacement control circuit 20; and a serial-parallel converter circuit 68 for columns and a serial-parallel converter circuit 64 for columns for performing serial conversion and parallel conversion of the redundancy replacement information of the column selection line and sequentially transferring the information to the replacement control circuit 22. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a configuration of a redundancy circuit and a semiconductor memory device characterized by the system.

  At the present time when high integration is advancing due to miniaturization of semiconductor manufacturing processes, a redundant memory array is provided in addition to a regular memory array from the viewpoint of improving yield, and for some reason a word line (WL) or column selection line is provided. When (CSL) breaks down, the importance of a redundancy circuit replaced with a spare WL or a spare CSL is increasing. The redundancy circuit is usually composed of a fuse circuit that selects a failed row or column address by fuse blow, a replacement control circuit that compares information from the fuse circuit with an external input address and controls replacement to a spare WL / spare CSL. Has been. The redundancy circuit having such a configuration is normally used as a row (row) and column (column) redundancy circuit, such as a row decoder for selecting and driving a normal WL and a spare WL for increasing the access speed, and a normal CSL. And spare column CSL are arranged in the vicinity of the column decoder for selecting and driving.

  When the memory cell array is divided into a plurality of parts and the row decoder and the column decoder are sandwiched between the memory cell arrays, a row redundancy circuit or a column redundancy circuit cannot be arranged in the vicinity of the row decoder and the column decoder. As a result, the wiring length of the output signal from the replacement control circuit is greatly increased, and the delay time until it is input to the row decoder and column decoder is greatly increased, resulting in a delay in access speed. In addition, the row fuse block constituting the row redundancy circuit or the column fuse block constituting the column redundancy circuit cannot be used as a wiring area on the block, and therefore causes an increase in layout area, that is, an increase in chip size. It has become.

  As described above, the conventional redundancy circuit has a limited layout location due to its circuit configuration. Therefore, there is no freedom in layout, and if the control signal line length from the redundancy circuit to the row decoder and column decoder is extended, the access is made. I have the problem of causing a drop in speed.

An integrated circuit having a redundant element includes a normal decoder for selecting a normal element in response to each address, and a flip-flop circuit connected to the normal decoder, and in a first state of the flip-flop circuit The normal decoder is enabled to respond to each address, the normal decoder is disabled in response to any address in the second state of the flip-flop circuit, and the flip-flop circuit is disabled in the normal operating state of the circuit. A circuit and a method characterized by not setting the state 2 are already disclosed (Patent Document 1 and Patent Document 2).
US Pat. No. 6,134,176 US Pat. No. 6,115,302

  The present invention provides a semiconductor memory device that can freely determine the location of a redundant fuse block without sacrificing access speed.

  The first feature of the embodiment of the present invention is that (a) row decoder and column decoder for selectively driving word lines and column select lines, respectively, and (b) redundancy replacement information for word lines and column select lines, respectively. And (c) row replacement control circuit for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines, and column replacement control. (D) a row parallel conversion circuit and a row serial conversion circuit for sequentially transferring redundancy replacement information of a word line to a row replacement control circuit in synchronization with an internal clock signal for row; The redundancy replacement information on the select line is synchronized with the internal clock signal for the column. And summarized in that a semiconductor memory device and a serial-parallel conversion circuit for parallel-serial conversion circuit and a column for column sequentially transferred to the replacement control circuit for use.

  The second feature of the embodiment of the present invention is that (a) a row decoder and a column decoder for selectively driving a word line and a column select line, and (b) redundancy replacement information for the word line and the column select line, respectively. And (c) row replacement control circuit for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines, and column replacement control. And a row parallel-serial conversion circuit and a row serial-parallel conversion circuit that serially and parallel-converts redundancy replacement information of a word line in synchronization with a clock signal to be externally input and sequentially transfers the data to a row replacement control circuit. (E) Redundancy replacement information for column select lines And summarized in that a semiconductor memory device and a column for parallel-serial conversion circuit and a column for serial-parallel conversion circuit sequentially transfers the replacement control circuit for the column to serial conversion and parallel conversion is synchronized with the clock signal to be.

  According to the semiconductor memory device of the present invention, the arrangement location of the redundancy fuse block can be freely determined without sacrificing the access speed.

  Next, first to fourth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the following first to fourth embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes components. The material, shape, structure, arrangement, etc. are not specified below. The technical idea of the present invention can be variously modified within the scope of the claims.

[Examination example]
First, as shown in FIG. 16A, the examination example examined as the basis of the embodiment of the present invention is composed of a plurality of memory cells selected by a matrix address signal, and includes a normal cell array 10 and a redundant cell array 101. , 102, a row decoder 12 and a column decoder 14 for selectively driving word lines and column select lines included in the memory cell array 100, a row redundancy circuit 16, and a column redundancy circuit 18, respectively. The row redundancy circuit 16 includes a row fuse block 24 that outputs word line redundancy replacement information, and a row replacement control circuit 20 that controls spare replacement of the word line based on the word line redundancy replacement information, and includes column redundancy. The circuit 18 includes a column fuse block 26 that outputs redundancy replacement information of the column select line, and a column replacement control circuit 22 that controls spare replacement of the column line based on the redundancy replacement information of the column line.

  Further, as shown in FIG. 16B, the low fuse block 24 includes m fuse sets 28 represented by FRS <1> to FRS <m>, and the column fuse block 26 includes ), M fuse sets 30 represented by FCS <1> to FCS <m> are provided.

  The row redundancy circuit 16 controls the replacement of the row decoder 12 with m spare word lines WL, and the column redundancy circuit 18 controls the replacement of the column decoder 14 with m spare column selection lines CSL. The row fuse block 24 constituting the row redundancy circuit 16 is divided into a total number m of fuse sets 28, and each divided fuse set 28 includes a total number of n + 1 fuses. Similarly, the column fuse block 26 constituting the column redundancy circuit 18 is divided by a total number m of fuse sets 30, and each divided fuse set 30 is configured by a total number of n + 1 fuses.

(Replacement control circuit)
As shown in FIG. 17A, the configuration of the replacement control circuit 20 according to the examination example is a spare control circuit block including m spare control circuits 44 represented by S_Ctrl <1> to S_Ctrl <m>. 42 and a normal control circuit 32 represented by N_Ctrl. Each spare control circuit 44 receives n + 1 fuse data represented by FD <n + 1> and outputs spare word line WL drive signals represented by Spare_en <1> to Spare_en <m>, respectively. . The entire spare control circuit block 42 receives m × (n + 1) fuse data FD <mx (n + 1>) and sets m spare word line WL drive signals Spare_en <1> to Spare_en <m> to low. The data is output to the decoder 12. The configuration of the replacement control circuit 22 is the same as that of the replacement control circuit 20 shown in FIG.

(Normal control circuit)
As shown in FIG. 17B, the normal control circuit 32 includes a NOR gate 36 that receives m spare word line drive signals Spare_en <1> to Spare_en <m>, an output signal of the NOR gate 36, and a row address. An AND gate 38 to which the enable signal RAE is input and an inverter 40 connected to the AND gate 38, and outputs a normal word line WL drive signal Normal_en to the row decoder 12.

  Further, in the replacement control circuit 20, the spare control circuit block 42 divided into m pieces and the m spare word lines WL correspond to each other one by one, and each spare replacement control is performed. Similarly, in the replacement control circuit 22, the spare control circuit block divided into m pieces and the m spare column selection lines CSL have a one-to-one correspondence, and each spare replacement control is performed.

  Spare_en <m> / Normal_en output from the replacement control circuit 20 and input to the row decoder 12 are the spare word line WL and normal word line WL output based on comparison with the external input address signal A <n>, respectively. This is a drive confirmation signal. Similarly, Spare_en <m> / Normal_en output from the replacement control circuit 22 and input to the column decoder 14 are the spare column selection line CSL and normal output output based on the comparison with the external input address signal A <n>, respectively. This is a drive confirmation signal for the column selection line CSL.

The memory cell array 100 includes 2 ⁿ normal word lines WL / normal column selection lines CSL, and m spare word lines WL / spare column selection lines CSL. The row decoder 12 and the column decoder 14 include n Selection and driving of 1/2 ⁿ normal word line WL / normal column selection line CSL and selection driving of 1 / m spare word line WL / spare column selection line CSL are performed by an external address of the bit.

(Overall operation)
Next, the overall operation will be described by taking as an example the case where the normal word line WL to be selectively driven is replaced with the spare word line SWL3 when the row address signals AR1 to ARn inputted externally are ALL = “H”. Of the row fuse blocks 24 divided into m fuse sets 28, the fuse belonging to FRS <3>, which is the fuse set 28 corresponding to the selection of the spare word line SWL3, is blown. In the fuse set 28 including n + 1 fuses, n fuses are address fuses FA1 to FAn corresponding to the row address signals AR1 to ARn, and the remaining one is an enable fuse FE that declares the use of the fuse set. . The address fuses FA1 to FAn and the enable fuse FE are blown to “H”, and if not blown, the “L” state is latched when the power is turned on, and the respective states are output. In the enable fuse FE, by blowing one fuse, the use of the fuse set is declared, and the replacement control circuit 20 compares the information FRm <n> from the address fuse with the external row address signal AR <n>. . Since the address to be replaced with a spare is ALL = “H”, the address fuses FA1 to FAn corresponding to the row address signals AR1 to ARn and all the fuses of the enable fuse FE are blown. As a result, the output signals F_AR1 to F_ARn of the address fuses FA1 to FAn from the fuse set 28 represented by FRS <3> and the output signal F_ARE of the enable fuse FE are input to the replacement control circuit 20 in the “H” state. The On the other hand, all the output signals from the fuse set 28 (other than FRS <3>) not performing the fuse blow are input to the replacement control circuit 20 in the “L” state. The same applies to the entire operation when the normal column selection line CSL selected and driven when the externally input column address signals AC1 to ACn are ALL = “H” is replaced with the spare column selection line CSL3. Description is omitted.

(Spare control circuit)
In the spare control circuit block 42, as shown in FIG. 18A, the internal configuration of the spare control circuit 44 divided into the same number m as the spare number m has the same number of Add_Cmp <1> to the external address number n. The address comparison circuit 46 represented by Add_Cmp <n> and one spare determination circuit 56 are included.

(Address comparison circuit)
As shown in FIG. 18B, the address comparison circuit 46 includes two inverters 50 and 52, one transfer switch (TRS) 48, and one clocked inverter (CINV) 54. In the address comparison circuit 46, AR <n> is an externally input row address signal, F_AR <n> is an address fuse output signal output from the row fuse block 24, and FHIT <n> is an output signal indicating an address comparison result. It is. If the externally input row address signal AR <n> and the address fuse output signal F_AR <n> are in the same state, the output signal FHIT <n> of the address comparison circuit 46 is in the “H” state. L ”state is output. For example, if AR <n> = “H” and F_AR <n> = “H” (fuse blown state), the clocked inverter circuit (CINV) 54 opens and the output signal FHIT <n> is “H”. The state of is output. If AR <n> = “L” and F_AR <n> = “L”, the transfer switch (TRS) 48 is now opened and the output signal FHIT <n> similarly goes to the “H” state. Output. On the other hand, when the address signal AR <n> inputted externally and the output signal F_AR <n> of the address fuse are different, for example, when AR <n> = “H” and F_AR <n> = “L”, transfer is performed. Since the switch (TRS) 48 opens, the output signal FHIT <n> outputs “L”. Similarly, when AR <n> = “L” and F_AR <n> = “H”, the clocked inverter circuit (CINV ) 54 opens, and the output signal FHIT <n> outputs “L”.

(Spare judgment circuit)
As shown in FIG. 18C, the spare determination circuit 56 includes a NAND gate 58 having n + 2 external address input numbers and an inverter 60. The n + 2 inputs to the NAND gate 58 include the output signals FHIT <1> to FHIT <n> of the n address comparison circuits 46, the output signal F_ARE of the enable fuse FE output from the row fuse block 24, and the row system. A row address enable signal RAE indicating an operating state is input. The row address enable signal RAE is generated by a peripheral circuit and is in the “H” state while the row system is operating. Since the row address enable signal RAE is in the “L” state when the row system is not in the operating state, the normal / spare drive determination signal Normal_en / Spare_en <that controls the normal / spare word line WL and the normal / spare column selection line CSL. Both n> are normally in the “L” state, and either signal is in the “H” state only when RAE = “H”.

  Here, when row address signals AR1 to ARn = “H” inputted externally are inputted to the replacement control circuit 20, address comparison in the spare control circuit 44 represented by S_Ctrl <3> corresponding to the spare word line SWL3. The output signals FHIT <1> to FHIT <n> of the circuit 46 are “H” because the addresses of the address fuse output signal F_AR <n> and the externally input row address signal AR <n> match. Output the status. This “H” output, the “H” state of the output signal F_ARE of the enable fuse FE of the fuse set 28 represented by FRS <3>, and the “H” state of the row address enable signal RAE are input to the spare determination circuit 56. Then, since the “H” state is input to all the inputs of the NAND gate 58, Spare_en <3> that is an output signal from the spare determination circuit 56 becomes “H”. Since this Spare_en <3> = “H” is input to the normal control circuit 32, the output signal Normal_en of the normal control circuit 32 outputs “L”. Therefore, Sapre_en <3> = “H” and Normal_en <3> = “L” are input to the row decoder 12.

  In addition, a row address signal AR <n> that can be externally input is input to the row decoder 12, the row decoder 12 becomes a row address enable signal RAE = “H”, a row-related operation is started, and replacement control is performed. Whether the normal word line WL is selected / driven or the spare word line WL is selected / driven is determined according to the Normal_en / Spare_en state output from the circuit 20. In the above example, Normal_en = “L” and Spare_en <3> = “H” are input to the row decoder 12, so that the spare word line SWL3 is selected and driven.

  Further, when row address signals AR0 to ARn ≠ “H” inputted externally in this state are inputted to the replacement control circuit 20, the output signal FR <n> of the address fuse and the row address signal AR inputted externally. The addresses of <n> do not match, and Spare_en <3> does not become “H”, but Normal_en becomes “H”. As a result, in the row decoder 12, the spare word line SWL3 is not selected / driven, and the normal word line WL is selectively driven according to the externally input row address signal.

  The above is the case of replacement of the word line WL, but the same applies to the replacement of the column selection line CSL. However, in this case, the column address enable signal CAE representing the column system operation state is input to the spare determination circuit 56.

  In order to increase the access speed, it is necessary to select and drive the word line WL / column selection line CSL as soon as possible by the row decoder 12 and the column decoder 14. That is, in the configuration of the row redundancy circuit 16 and the column redundancy circuit 18 of the examination example, the row redundancy circuit 16 and the column redundancy circuit 18 are arranged as close to the row decoder 12 and the column decoder 14 as possible, and the replacement control circuit 20, It is important to minimize the wiring length of the Spare_en / Normal_en signal that is an output signal from the output signal 22 and to reduce the delay time until these Spare_en / Normal_en signals are input to the row decoder 12 and the column decoder 14.

[First embodiment]
As shown in FIG. 1, the configuration of the semiconductor memory device according to the first embodiment of the present invention includes a plurality of memory cells selected by a matrix address signal, and includes a normal cell array 10, redundant cell arrays 101 and 102. A memory cell array 100, a row decoder 12 and a column decoder 14 for selectively driving word lines and column select lines included in the memory cell array, and a row fuse block 24 for outputting redundancy replacement information for the word lines and column select lines, respectively. And column fuse block 26, row replacement control circuit 20 for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines, column replacement control circuit 22, and chip, respectively. Internal signal generated internally The clock generation circuit 70 that generates the internal clock signal FTCLK using the signal as a trigger, and the redundancy replacement information of the word lines are serially and parallel converted in synchronization with the internal clock signal FTCLK, and sequentially transferred to the row replacement control circuit 20. The column serial conversion circuit 66 and the row serial conversion circuit 62 and the column select line redundancy replacement information are serially converted and parallel converted in synchronization with the internal clock signal FTCLK and sequentially transferred to the column replacement control circuit 22. A parallel-serial conversion circuit 68 and a column serial-parallel conversion circuit 64 are provided.

  The clock generation circuit 70 generates an internal clock signal FTCLK using the internal signal CHIP_READY generated when the power supply Vcc is raised as a trigger, and supplies the word line redundancy replacement information to the row replacement control circuit 20 during the power supply Vcc rise period. The operation of ending the transfer and ending the transfer of the redundancy replacement information of the column selection line to the column replacement control circuit 22 may be performed.

  According to the semiconductor memory device of the first embodiment of the present invention, the fuse information data group output from the redundancy fuse block is converted into serial data by parallel-serial data conversion, and the serial data is synchronized with the clock. By sequentially transferring the data to a replacement control circuit arranged in the vicinity of the row decoder and the column decoder, the arrangement location of the redundancy fuse block can be freely determined without sacrificing the access speed.

  In the semiconductor memory device according to the first embodiment of the present invention, the replacement control circuit 20 controls the replacement of the row decoder 12 with the m spare word lines WL by the replacement control circuit 22 in the same manner as the examination example. Thus, the replacement of the column decoder 14 with m spare column selection lines CSL is controlled. The low fuse block 24 is divided into a total number m of fuse sets 28, and each divided fuse set 28 includes a total number of n + 1 fuses. Similarly, the column fuse block 26 is divided into a total number m of fuse sets 30, and each divided fuse set 30 includes a total number of n + 1 fuses.

  However, unlike the example studied in the first embodiment of the present invention, (m × (n + 1)) pieces of fuse information data output in parallel from the low fuse block 24 are converted into one serial signal by the clock signal FTCLK. A parallel parallel conversion circuit (parallel conversion circuit) 66 for converting to a serial data signal on a data line, and serial data on one serial data line on (m × (n + 1)) parallel data signal lines by a clock signal FTCLK Serial-parallel conversion circuit (serial-parallel conversion circuit) 62 for converting the parallel information into the parallel data, and (m × (n + 1)) pieces of fuse information data output in parallel from the column fuse block 26 by means of the clock signal FTCLK. Parallel serial conversion times for columns that are converted to serial data transferred on the line Path (parallel-serial conversion circuit) 68 and a serial-parallel conversion circuit for column (serial-parallel) that converts serial data on one serial data line into parallel data on (m × (n + 1)) parallel data signal lines by a clock signal FTCLK. Conversion circuit) 64 and a clock generation circuit 70 for generating a clock signal FTCLK used for parallel-serial conversion and serial-parallel conversion.

  In FIG. 1, FR_out output from the row parallel-serial conversion circuit 66 is serial data on a serial data line obtained by serially converting parallel data on (m × (n + 1)) fuse information lines output from the row fuse block 24. On the other hand, FC_out is serial data on a serial data line obtained by serially converting parallel data on (m × (n + 1)) fuse information lines output from the column fuse block 26.

  FR_in <N> output from the row serial-parallel conversion circuit 62 to the replacement control circuit 20 is (m × (n + 1)) row fuse information data signals. FC_in <N> output from the column serial-parallel conversion circuit 64 to the replacement control circuit 22 is (m × (n + 1)) column fuse information data signals. Further, the FTCLK output from the clock generation circuit 70 includes a row-parallel conversion circuit 66 for row fuse information data, a serial-parallel conversion circuit 62 for row, a column-serial conversion circuit 68 for column fuse information data, and a column-serial conversion circuit 64 for columns. This is an internal clock signal to be controlled.

(Clock generation circuit)
An example of the clock generation circuit 70 applied to the semiconductor memory device according to the first embodiment of the present invention is a ring composed of an odd number of inverters as a basis for clock generation, as shown in FIG. The oscillator block 74 and a clock counter block 72 that counts the number of clocks and executes control to stop the ring oscillator block 74 are configured.

  As shown in FIG. 2B, the ring oscillator block 74 includes an odd-stage inverter 76 including a 2-input NAND gate 86 and an inverter 88, and a 2-input NAND gate 78 connected to the input side of the odd-stage inverter 76. , Inverters 80 and 82, and an inverter 84 connected to the output side of the odd-numbered inverter 76. As shown in FIG. 2B, the NAND gate 78 receives the CHIP_READY signal and the inverted signal of the CLKoff_R signal by the inverter 80, and the inverter 84 outputs the clock signal FTCLK.

  In FIG. 2A, the CHIP_READY signal input to the ring oscillator block 74 is a trigger signal for starting the operation of the ring oscillator. The CLKoff signal output from the clock counter block 72 and input to the ring oscillator block 74 is a trigger signal for stopping the operation of the ring oscillator. The clock signal FTCLK output from the ring oscillator block 74 is an internal clock that controls the parallel-serial conversion of the fuse information data and the serial-parallel conversion. The clock generation circuit 70 composed of such blocks can generate a necessary number of clock signals having a certain period with the CHIP_READY signal as a trigger. Here, the CHIP_READY signal serving as a trigger for clock generation will be described.

  In general, in a semiconductor memory device, various potentials (step-down potential, step-up potential, negative potential, etc.) used inside a chip are generated by a power supply circuit provided inside the chip. As shown in FIG. 2C, after the power is turned on, the power supply voltage Vcc rises to a predetermined potential with a certain slope, the power supply voltage rises to the predetermined potential, and the internal potential generated inside the chip. At time t1 indicating when the voltage reaches the desired potential, the signal CHIP_READY signal indicating that the chip is ready for operation transitions from the “L” state to the “H” state. The clock generation circuit 70 generates the clock signal FTCLK by using the transition of the CHIP_READY signal from “L” to “H” as a trigger after the power is turned on. Thereafter, at time t2, the CLKoff signal transits from the “L” state to the “H” state, whereby the operation of the ring oscillator is stopped, and the predetermined number of internal clocks FTCLK count the number of clocks.

(Parasi-li conversion circuit)
As shown in FIG. 3, the parallel-serial conversion circuit applied to the semiconductor memory device according to the first embodiment of the present invention includes parallel-serial conversion circuit blocks 94 and 96 for performing parallel-serial conversion and the parallel-serial control circuits 90 and 92. Has been. In FIG. 3, FTCLKi / bFTCLKi is an internal clock for controlling the parallel-serial conversion circuit blocks 94 and 96, FTCLKi is a clock having the same phase as that of FTCLK output from the clock generation circuit 70, and bFTCLKi is a clock having a phase opposite to that of FTCLKi. is there.

  Further, the FLAT signal transmitted from the parallel control circuits 90 and 92 to the parallel conversion circuit blocks 94 and 96, respectively, converts the fuse information data RSD output from the row fuse block 24 and the column fuse block 26 into row parallel conversion. This is a trigger signal for latching into the circuit 66 and the column parallel-serial conversion circuit 68. As a result, serial data FR_out and FC_out are output from the parallel-serial conversion circuit blocks 94 and 96, respectively.

―Parasiri conversion circuit block―
An example of the circuit configuration of the parallel-serial conversion circuit block 94 applied to the semiconductor memory device according to the first embodiment of the present invention is output from the fuse block (m × (n + 1) as shown in FIG. )) The same number of serial data transfer circuits 97 as the number of fuse data lines 104 and one serial data output circuit 98 are included. In the serial data transfer circuit 97, FI indicates input serial data, and FO and FO _{(mx (n + 1))} indicate output serial data. FD _{(1) to} FD _{( mx (n + 1))} are fuse data from the fuse block. The serial data transfer circuit 97 takes in the fuse data FD _{(1) to} FD _{(mx (n + 1))} from the fuse block in accordance with the input timing of the FLAT signal, and internal clock FTCLKi = “L” / bFTCLKi = The circuit configuration outputs output serial data FO, FO _{(mx (n + 1))} in synchronization with “H”.

On the other hand, the serial data output circuit 98 receives the output serial data FO _{(mx (n + 1))} as the input serial data FI and is synchronized with the internal clock FTCLKi = "H" / bFTCLKi = "L". In this circuit configuration, output serial data F_out is output.

The output serial data FO of the serial data transfer circuit 97 is input as the input serial data FI of the serial data transfer circuit 97 at the next stage. The (m × (n + 1)) serial data transfer circuits 97 are serially connected, and the output FO _{(mx (n + 1))} of the serial data transfer circuit 97 at the final stage is input to the serial data output circuit 98. Connected to FI.

  The output signal F_out of the serial data output circuit 98 is sequentially output in synchronization with the internal clock FTCLKi = “H” / bFTCLKi = “L”, and is input to the row serial-parallel conversion circuit 62 disposed in the vicinity of the row decoder 12. Serial data FR_out on the serial data line.

  The configuration of the parallel-serial conversion circuit block 96 in the column parallel-serial conversion circuit 68 shown in FIG. As a result, serial data FC_out on the serial data line input to the column serial-parallel conversion circuit 64 arranged in the vicinity of the column decoder 14 is obtained.

―Serial data transfer circuit―
The circuit configuration of the serial data transfer circuit 97 applied to the semiconductor memory device according to the first embodiment of the present invention is, for example, as shown in FIG. 4B, transfer switches 106 (Xfer1), 120 (Xfer3), 108 (Xfer2), an inverter 110, and inverters 112 and 114 and 116 and 118 that are bidirectionally connected.

  As apparent from FIG. 4B, the FLAT signal and its inverted signal by the inverter 110 are input to the gate of the transfer switch 106, and the internal clocks FTCLKi and bFTCLKi are input to the two gates of the transfer switch 120, respectively. . Similarly, internal clocks FTCLKi and bFTCLKi are input to the two gates of the transfer switch 108, respectively. The source / drain of the transfer switch 106 is connected to the fuse data line 104 and supplied with the fuse data FD, and the input serial data FI is supplied to the source / drain of the transfer switch 120. As a result, the output serial data FO is output from the inverter 118. Is output.

―Serial data output circuit―
The circuit configuration of the serial data output circuit 98 applied to the semiconductor memory device according to the first embodiment of the present invention is bidirectionally connected to the transfer switches 122 and 128 as shown in FIG. 4C, for example. It comprises inverters 124 and 126 and 130 and 132.

  As apparent from FIG. 4C, the internal clocks FTCLKi and bFTCLKi are input to the two gates of the transfer switch 122, respectively. Similarly, internal clocks FTCLKi and bFTCLKi are input to the two gates of the transfer switch 128, respectively. Input serial data FI is supplied to the source / drain of the transfer switch 122, and as a result, the output signal Fout is output from the inverter 130.

(Parasiri control circuit)
An example of the circuit configuration of the parallel control circuit 90 applied to the semiconductor memory device according to the first embodiment of the present invention is based on a clock signal FTCLK generated from a clock generation circuit 70 as shown in FIG. The control clock generation circuit 134 generates internal clock signals FTCLKi / bFTCLKi for controlling the parallel-serial conversion circuit, and the latch timing generation circuit 136 generates a FLAT signal for latching the fuse data FD into the serial data transfer circuit 97.

  As shown in FIG. 5B, the control clock generation circuit 134 includes an even-numbered stage inverter 142 and an odd-numbered stage inverter 140, receives the input signal FTCLK, and receives an FTCLKi, odd-numbered stage from the even-stage inverter 142. BFTCLKi is output from the inverter 140. FIG. 5A shows an operation timing waveform diagram of the control clock generation circuit 134 according to the present invention, and shows the timing waveforms of the clock signal FTCLK and the internal clock signals FTCLKi and bFTCLKi.

  As shown in FIG. 5D, the latch timing generation circuit 136 includes a delay circuit 138 including an inverter 148, a NAND gate 146, and an odd number of stages of inverters 144. As shown in FIG. 5E, the latch timing generation circuit 136 according to the present invention generates an “H” pulse having a pulse width tw equal to the delay time td when the CHIP_READY signal transitions from “L” to “H”. It is a pulse circuit having an operation timing waveform for outputting a FLAT signal.

(Sili-para conversion circuit)
As shown in FIG. 6, the row-serial conversion circuit 62 applied to the semiconductor memory device according to the first embodiment of the present invention includes a serial-parallel conversion circuit block 154 that performs serial-parallel conversion, and a serial-parallel conversion circuit block 154. It is comprised from the serial para control circuit 150 which controls. Similarly, the configuration of the column serial-parallel conversion circuit 64 applied to the semiconductor memory device according to the first embodiment of the present invention includes a serial-parallel conversion circuit block 156 that performs serial-parallel conversion, as shown in FIG. The serial block control circuit 152 controls the circuit block 156. In FIG. 6, FTCLKi / bFTCLKi is an internal clock for controlling the serial-parallel conversion circuit blocks 154 and 156, FTCLKi is an internal clock signal in phase with the clock signal FTCLK output from the clock generation circuit 70, and bFTCLK is opposite to FTCLK. Phase internal clock signal.

  As apparent from FIG. 6, the serial-para control circuit 150 receives the clock signal FTCLK and outputs internal clock signals FTCLKi and bFTCLKi and serial data FR_out to the serial-parallel conversion circuit block 154. The serial-parallel conversion circuit block 154 receives the internal clock signals FTCLKi and bFTCLKi and the serial data FR_out and supplies parallel data FR_in <N> to the replacement control circuit 20. Similarly, the serial-parallel control circuit 152 receives the clock signal FTCLK and outputs internal clock signals FTCLKi and bFTCLKi and serial data FC_out to the serial-parallel conversion circuit block 156. The serial-parallel conversion circuit block 156 receives the internal clock signals FTCLKi and bFTCLKi and the serial data FC_out, and supplies parallel data FC_in <N> to the replacement control circuit 22.

―Sili-para conversion circuit block―
One example of the circuit configuration of the serial-parallel conversion circuit block 154 applied to the semiconductor memory device according to the first embodiment of the present invention is serially connected to each other (m × (n + 1) as shown in FIG. ) Parallel data transfer circuits 158. The operation of the parallel data transfer circuit 158 is controlled by the internal clock signal FTCLKi / bFTCLKi, similarly to the serial data transfer circuit 97 and the serial data output circuit 98 shown in FIG. The first-stage parallel data transfer circuit 158 receives the serial data FR_out from the parallel-serial conversion circuit block 94 as the input serial data FI, and synchronizes with the internal clock signal FTCLKi / bFTCLKi and outputs FR_in <1> as the serial output data FO. Output. Similarly, the second-stage parallel data transfer circuit 158 receives the first-stage serial output data FR_in <1> as input serial data FI, and synchronizes with the internal clock signal FTCLKi / bFTCLKi to output the serial output data FR_in <2>. Is output. Similarly, the final stage parallel data transfer circuit 158 receives the output serial data FR_in <(mx (n + 1) -1>) as the input serial data FI and sets the internal clock FTCLKi = “H” / bFTCLKi = “L”. In synchronization, the circuit configuration is such that FR_in <(mx (n + 1)> is output as the output serial data FO The configuration of the parallel data transfer circuit 158 is the same as that of the serial data output circuit 98. The output serial data FO is output in synchronization with FTCLKi = "H" / bFTCLKi = "L" This parallel data transfer circuit 158 is serially connected in the same manner as the serial data transfer circuit 97. However, in the serial-parallel conversion circuit block 154, all (m × (n + 1)) parallel data transfer circuit 158 output signals are taken out, and this output becomes (m × (n 1)) Parallel data FR_in <1>, FR_in <2>, FR_in <3>, ..., FR_in <mx (n + 1)>, and parallel data FR_in <N> as row replacement control circuit 20 is input.

  The column-type serial-parallel conversion circuit block 156 is configured in the same manner, and outputs (m × (n + 1)) parallel data FC_in <1>, FC_in <2>, FC_in <3>,..., FC_in <mx ( n + 1)>, and is input to the column replacement control circuit 22 as parallel data FC_in <N>.

―Parallel data transfer circuit―
The circuit configuration of the parallel data transfer circuit 158 applied to the semiconductor memory device according to the first embodiment of the present invention is bi-directionally connected to transfer switches 162 and 168 as shown in FIG. 7B, for example. It comprises inverters 164, 166, 170, 171.

  As apparent from FIG. 7B, the internal clocks FTCLKi and bFTCLKi are input to the two gates of the transfer switch 162, respectively. Similarly, internal clocks FTCLKi and bFTCLKi are input to the two gates of transfer switch 168, respectively. Input serial data FI is supplied to the source / drain of the transfer switch 162, and as a result, the output signal FO is output from the inverter 171.

(Seripara control circuit)
The circuit configuration of the serial-parallel control circuit 150 applied to the semiconductor memory device according to the first embodiment of the present invention is that the serial-parallel conversion circuit control is performed from the clock signal FTCLK generated from the clock generation circuit 70, for example, as shown in FIG. And a control clock generation circuit 172 for generating an internal clock signal FTCLKi / bFTCLKi, which is a clock for use. The column-type serial para-control circuit 152 is similarly configured.

As shown in FIG. 8B, the control clock generation circuit 172 includes an even-numbered inverter 174 and an odd-numbered inverter 176, receives the clock signal FTCLK as an input signal, and receives an even-numbered inverter. The internal clock signal FTCLKi is output from 174, and the internal clock signal bFTCLKi is output from the odd-numbered stage inverter 176. FIG. 8C shows an operation timing waveform diagram of the control clock generation circuit 172 according to the present invention, and shows the timing waveforms of the clock signal FTCLK and the internal clock signals FTCLKi and bFTCLKi (overall operation). )
The overall operation will be described by taking as an example the case where the normal word line WL to be selectively driven is replaced with the spare word line SWL3 when the externally input row address signals AR1 to ARn are ALL = “H”.

  As shown in FIG. 9, FRS <3> corresponding to selection of the spare word line SWL3 in the row fuse block 24 which is divided into m and includes the fuse set 28 indicated by FRS <1> to FRS <m>. Blowing is performed on fuses belonging to. Since the replacement is performed when the row address signals AR1 to ARn are ALL = “H”, the n address fuses FA1 to FAn and the enable fuse FE are blown. As a result, all fuse information latched and output from FRS <3> when the power is turned on is in the “H” state.

  When the CHIP_READY signal transitions from “L” to “H” as shown in FIG. 10 in response to the fact that each potential in the chip has reached a desired potential after the power is turned on, first, in the parallel control circuit 90. The latch timing generation circuit 136 outputs a FLAT signal having an “H” pulse.

  As shown in FIG. 4A, the FLAT signal is input to the serial data transfer circuit 97 in the parallel-serial conversion circuit block 94. In response to the FLAT signal becoming “H”, FIG. The transfer switch (Xfer1) 106 in the serial data transfer circuit 97 shown in FIG. 2 is turned on, and the fuse information data FD from the fuse block is introduced into the serial data transfer circuit 97. At this time, the internal clock signals FTCLKi and bFTCLKi are in the “L” state, so that the FTCLKi = “L” and bFTCLKi = “H”, so that the fetched fuse information data FD is in the ON state. The output signal FO is output through the transfer gate (Xfer2) 108.

  When the “H” pulse of the FLAT signal is cut and FLAT = “L”, the transfer gate (Xfer1) 106 is turned off, and the fuse data FD introduced into the serial data transfer circuit 97 is latched. For example, in FIG. 4B, when the fuse is blown (FD = “H”), the node A in the serial data transfer circuit 97 is “H”, the node B is “L”, and the node C is “ L ", as a result, the output FO is latched at" H ".

  On the other hand, when the fuse is not blown (FD = “L”), the node A in the serial data transfer circuit 97 is “L”, the node B is “H”, and the node C is “H”. The output FO is latched at “L”.

  In this way, the serial data transfer circuit 97 corresponding to the blown fuse latches the “H” state, and the serial data transfer circuit 97 corresponding to the fuse not blown latches the “L” state.

  At a timing t1 when the “H” pulse of the FLAT signal is cut off and the fuse data FD from the low fuse block 24 is latched in the serial data transfer circuit 97, the ring oscillator block 74 in the clock generation circuit 70 starts operation. As shown in FIG. 10, a clock signal FTCLK having a period Tns is generated. The parallel-serial (PS) conversion started at time t1 is stopped at time t2, and at the same time, serial-parallel (SP) conversion is started.

  When the clock signal FTCLK is generated, the internal clock signal FTCLKi / bFTCLKi is generated by the control clock generation circuits 134 and 172 in the parallel control circuit 90 and the serial control circuit 150.

When the internal clock signal FTCLKi / bFTCLKi is generated and FTCLKi = “H” / bFTCLKi = “L”, the serial output data FR_out from the parallel-serial conversion circuit block 94 is first (m × (n + 1))-th serial. The fuse information FD _{(mx (n + 1))} taken in the data transfer circuit 97 is output.

At this time, the output FR_in <1> of the parallel data transfer circuit 158 in which the output FR_out from the parallel-serial conversion circuit block 94 is input as the input serial data FI is the data (the data (the data) that the serial data output circuit 98 has latched as the initial value ( “H” or “L” is acceptable). At this time, the clock counter block 72 in the clock generation circuit 70 counts “1” as the number of clocks. In synchronization with the next clock, the fuse information FD _{(mx (n + 1) -1)} fetched in the (m × (n + 1) −1) th serial data transfer circuit 97 is output from FR_out, and the serial parameter The output FR_in <1> of the parallel data transfer circuit 158 in the conversion circuit block 154 outputs fuse information FD _{(mx (n + 1))} fetched into the (m × (n + 1)) th parallel transfer circuit. At this time, the clock counter block 72 in the clock generation circuit 70 counts up by one and counts “2”. In this way, serial data FR_out from the parallel-serial conversion circuit block 94 is transmitted to the serial-parallel conversion circuit block 154 for each clock, but the number of clocks is the serial data transfer circuit 97 and serial-parallel conversion circuit in the parallel-serial conversion circuit block 94. When one more clock is generated than the number (m × (n + 1)) of the number of stages of the parallel data transfer circuit 158 in the block 154, and the total number of clocks becomes (m × (n + 1) +1), the total number (m × (n + 1)) ) The outputs FR_in <1> to FR_ <mx (n + 1)> of the parallel data transfer circuits 158 are output from the parallel-serial conversion circuit block 94 (m × (n + 1) -bit serial data FR_out is (m × (n + 1) -bit parallel data FR_in <N> is output, and at this time, the clock counter block 72 in the clock generation circuit 70 has a clock count of (m × (n + 1) +1). In response, the CLKoff signal is changed from “L” to “H”, the operation of the ring oscillator block 74 is stopped, and the generation of the subsequent clock is stopped.

  As described above, m × (n + 1) bits output from the row fuse block 24 by generating (m × (n + 1) +1) times of clocks in the chip using the CHIP_READY signal generated when the power is turned on as a trigger. The parallel data FD <N> can be converted as serial data FR_out once, and then converted again as m × (n + 1) -bit parallel data FR_in <N>.

  In this state, when the row address enable signal RAE indicating the row-related operation state becomes RAE = “H” and the row-related operation starts, the replacement control circuit 20 having the same circuit configuration as the examination example determines Normal_en / Spare_en, Normal word line WL or spare word line SWL is selectively driven.

  Since the address fuse information signal F_AR <n> of the spare control circuit S_Ctrl <3> corresponding to the spare word line SWL3 in the replacement control circuit 20 is inputted with the data subjected to the parallel-serial conversion, F_AR <n> is ALL = “H”. Therefore, now, when the external row address signals AR1 to Arn = “H” are input to the replacement control circuit 20, the spare_en <3> = “H” from the spare determination circuit 56 and from the normal control circuit 32, as in the examination example. Normal_en = “L” is output to the row decoder 12, and the row decoder 12 selects and drives the spare word line SWL3 in response to Spare_en <3> = “H”.

  Here, it is important that the replacement control circuit cannot be arranged in the vicinity of the row decoder when the memory cell array is divided into a plurality of parts and the row decoder and the column decoder are sandwiched between the memory cell arrays. On the other hand, in the semiconductor memory device according to the first embodiment of the present invention, the replacement control circuit 20 can be arranged in the vicinity of the row decoder 12. As a result, the length of the Spare_en / Normal_en signal output from the replacement control circuit 20 can be reduced, and the delay time until it is input to the row decoder 12 and the column decoder 14 can be minimized. Therefore, it is effective in increasing the access speed. The above is the case of replacement of the word line WL, but the same applies to the replacement of the column selection line CSL.

  From the above, in the study example, the location of the fuse block is limited due to the access speed, but in the semiconductor memory device according to the first embodiment of the present invention, the fuse output from the fuse block is limited. Information data is converted into one serial data by parallel-serial conversion, and the serial data is synchronized with a clock and sequentially transferred to the replacement control circuits 20 and 22 arranged in the vicinity of the row decoder 12 and the column decoder 14 to thereby access speed. The location of the redundant fuse block can be freely determined without sacrificing the cost.

  Furthermore, in the semiconductor memory device according to the first embodiment of the present invention, since the location of the fuse block can be freely determined, for example, the fuse block is provided on the outer periphery of the chip where the circuit block is hardly arranged. By arranging, the degree of freedom of the layout of the peripheral portion is increased and the layout area is reduced, that is, the chip size is reduced.

  As described above, according to the semiconductor memory device of the first embodiment of the present invention, the fuse information data group output from the redundancy fuse block is converted into serial data by parallel-serial data conversion, and the serial data By synchronizing the data with the clock and sequentially transferring the data to a replacement control circuit arranged in the vicinity of the row decoder and the column decoder, the location of the redundant fuse block can be freely determined without sacrificing the access speed.

[Second Embodiment]
The configuration of the semiconductor memory device according to the second embodiment of the present invention is composed of a plurality of memory cells selected by a matrix address signal, as shown in FIG. 11, and includes a normal cell array 10, redundant cell arrays 101 and 102. A memory cell array 100, a row decoder 12 and a column decoder 14 for selectively driving word lines and column select lines included in the memory cell array 100, and a row fuse for outputting redundancy replacement information for the word lines and the column select lines, respectively. A block 24 and a column fuse block 26; a row replacement control circuit 20 for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines; and a column replacement control circuit 22; , Word line reduction A row parallel-to-serial conversion circuit 66 and a row serial-to-parallel conversion circuit 62 that serially and parallel-convert the dance replacement information in synchronization with an externally input clock signal FTCLK and sequentially transfer it to the row replacement control circuit 20, and a column select line Are provided with a column parallel conversion circuit 68 and a column serial conversion circuit 64 which are serially and parallel converted in synchronization with the externally input clock signal FTCLK and sequentially transferred to the column replacement control circuit 22.

  In the semiconductor memory device according to the second embodiment of the present invention, as in the first embodiment, the replacement control circuit 20 controls the replacement of the row decoder 12 with m spare word lines WL, The replacement control circuit 22 controls replacement of the column decoder 14 with m spare column selection lines CSL. The low fuse block 24 is divided into a total number m of fuse sets 28, and each divided fuse set 28 includes a total number of n + 1 fuses. Similarly, the column fuse block 26 is divided into a total number m of fuse sets 30, and each divided fuse set 30 includes a total number of n + 1 fuses. Further, in the second embodiment of the present invention, as in the first embodiment, (m × (n + 1)) pieces of fuse information data output in parallel from the row fuse block 24 are converted by the clock signal FTCLK. A row parallel / serial conversion circuit (paraserial conversion circuit) 66 for converting serial data signals on one serial data line, and (m × (n + 1)) serial data on one serial data line by a clock signal FTCLK. Serial / parallel conversion circuit (serial-parallel conversion circuit) 62 for converting parallel data on the parallel data signal line, and (m × (n + 1)) pieces of fuse information data output in parallel from the column fuse block 26 by the clock signal FTCLK. Parallel serial conversion for column to convert to serial data transferred on one serial signal line Circuit (parallel-serial conversion circuit) 68 and a serial-parallel conversion circuit for column (serial-parallel) that converts serial data on one serial data line into parallel data on (m × (n + 1)) parallel data signal lines by a clock signal FTCLK. Conversion circuit) 64.

  However, unlike the first embodiment, the second embodiment of the present invention has a circuit configuration that does not include the clock generation circuit 70 that generates the clock signal FTCLK used for the parallel-serial conversion and the serial-parallel conversion in the chip. ing.

  Also in the semiconductor memory device according to the second embodiment, instead of not generating a clock inside the chip, by inputting the necessary number of clock signals FTCLK necessary for the parallel-serial / serial-parallel conversion from the outside of the chip, the first Similarly to the embodiment, fuse information data RSD <N> as parallel information output from the row fuse block 24 and the column fuse block 26 is converted into one serial data FR_out and FC_out by parallel-serial conversion, and the serial data FR_out , FC_out are sequentially transferred to the replacement control circuits 20 and 22 arranged in the vicinity of the row decoder 12 and the column decoder 14 in synchronization with the clock signal FTCLK.

  According to the semiconductor memory device of the second embodiment of the present invention, the fuse information data group output from the redundancy fuse block is converted into serial data by parallel-serial data conversion, and the serial data is synchronized with the clock. By sequentially transferring the data to a replacement control circuit arranged in the vicinity of the row decoder and the column decoder, the arrangement location of the redundancy fuse block can be freely determined without sacrificing the access speed.

  Further, unlike the first embodiment, since no clock generation circuit is provided in the chip, there is an effect of further reducing the layout area, that is, reducing the chip size.

[Third embodiment]
As shown in FIG. 12, the configuration of the semiconductor memory device according to the third embodiment of the present invention is composed of a plurality of memory cells selected by a matrix address signal, and comprises a normal cell array 10 and redundant cell arrays 101 and 102. A memory cell array 100; a row decoder 12 and a column decoder 14 for selectively driving word lines and column select lines included in the memory cell array 100; a row fuse block 24 for outputting redundancy replacement information for the word lines and column select lines; A column fuse block 26, a row replacement control circuit 20 for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines, a column replacement control circuit 22, and a chip internal Generated inside The clock generation circuit 71 for generating the row internal clock signal FRTCLK and the column internal clock signal FCTCLK using the signal as a trigger, and the redundancy replacement information of the word line are synchronized with the row internal clock signal FRTCLK for serial conversion and parallel The row parallel-serial conversion circuit 66 and the row serial-parallel conversion circuit 62 that convert and sequentially transfer to the row replacement control circuit 20 and the redundancy replacement information of the column select line are serially converted in synchronization with the internal clock signal FCTCLK for the column. And a column parallel-serial conversion circuit 68 and a column serial-parallel conversion circuit 64 that perform parallel conversion and sequentially transfer to the column replacement control circuit 22.

  The clock generation circuit 71 generates a row internal clock signal FRTCLK and a column internal clock signal FCTCLK separately, and synchronizes with the row internal clock signal FRTCLK for the row of the redundancy replacement information of the word line. As soon as the transfer to the replacement control circuit 20 is completed, the redundancy replacement information of the column select line may be transferred to the column replacement control circuit 22 in synchronization with the column internal clock signal FCTCLK. Alternatively, the transfer to the row replacement control circuit 20 may be performed after the transfer to the column replacement control circuit 22.

  In the semiconductor memory device according to the third embodiment of the present invention, as in the first and second embodiments, the replacement control circuit 20 replaces the row decoder 12 with m spare word lines WL. The replacement control circuit 22 controls the replacement of the column decoder 14 with m spare column selection lines CSL. The low fuse block 24 is divided into a total number m of fuse sets 28, and each divided fuse set 28 includes a total number of n + 1 fuses. Similarly, the column fuse block 26 is divided into a total number m of fuse sets 30, and each divided fuse set 30 includes a total number of n + 1 fuses.

  However, in the third embodiment of the present invention, unlike the first and second embodiments, (m × (n + 1)) pieces of fuse information data output in parallel from the row fuse block 24 are used for the row. A row parallel-serial conversion circuit (paraserial conversion circuit) 66 that converts a serial data signal on one serial data line by the clock signal FRTCLK, and serial data on one serial data line by the row clock signal FRTCLK (m X (n + 1)) serial / parallel conversion circuit (serial-parallel conversion circuit) 62 for converting parallel data on parallel data signal lines, and (m × (n + 1)) pieces of fuse information output in parallel from the column fuse block 26. Serial data that transfers data on one serial signal line by column clock signal FCTCLK Column serial / serial conversion circuit (parallel-serial conversion circuit) 68 for converting data into serial data on one serial data line by means of column clock signal FCTCLK and parallel on (m × (n + 1)) parallel data signal lines. A serial serial conversion circuit (serial conversion circuit) 64 for converting data into data is included. That is, unlike the first embodiment, the clock generation circuit 71 applied to the semiconductor memory device according to the third embodiment of the present invention has a circuit configuration for generating the row clock signal FRTCLK and the column clock signal FCTCLK. It has become.

(Clock generation circuit)
The clock generation circuit 71 applied to the semiconductor memory device according to the third embodiment of the present invention is composed of a row clock generation circuit 180 and a column clock generation circuit 182 as shown in FIG. The Further, the row clock generation circuit 180 includes a ring oscillator block 184 and a clock counter block 188, and the column clock generation circuit 182 includes a ring oscillator block 186 and a clock counter block 190.

  As shown in FIG. 13B, the ring oscillator block 184 includes an odd-stage inverter 192 composed of a 2-input NAND gate 196 and an inverter 194, and a 2-input NAND gate 200 connected to the input side of the odd-stage inverter 192. , Inverters 198 and 202, and an inverter 204 connected to the output side of the odd-numbered inverter 192. As shown in FIG. 13B, the NAND gate 200 receives the CHIP_READY signal and the inverted signal of the CLKoff_R signal by the inverter 198, and the row clock signal FRTCLK is output from the inverter 204.

  As shown in FIG. 13C, the ring oscillator block 186 includes an odd-stage inverter 206 including a 2-input NAND gate 210 and an inverter 208, and a 2-input NAND gate 214 connected to the input side of the odd-stage inverter 206. , Inverters 212 and 216, and an inverter 218 connected to the output side of the odd-numbered inverter 206. As shown in FIG. 13C, the CLKoff_R signal and the inverted signal of the CLKoff_C signal by the inverter 212 are input to the NAND gate 214, and the column clock signal FCTCLK is output from the inverter 218.

  In FIG. 13A, the CHIP_READY signal input to the ring oscillator block 184 is a trigger signal for starting the operation of the ring oscillator. The CLKoff_R signal output from the clock counter block 188 and input to the ring oscillator block 184 is a trigger signal for stopping the operation of the ring oscillator. The row clock signal FRTCLK output from the ring oscillator block 184 is an internal clock for controlling the parallel-serial conversion of the fuse information data and the serial-parallel conversion.

  Similarly, the CLKoff_R signal input to the ring oscillator block 186 in FIG. 13A is a trigger signal for starting the operation of the ring oscillator. The CLKoff_C signal output from the clock counter block 190 and input to the ring oscillator block 186 is a trigger signal for stopping the operation of the ring oscillator. A column clock signal FCTCLK output from the ring oscillator block 186 is an internal clock that controls the parallel-serial conversion of the fuse information data and the serial-parallel conversion.

  The clock generation circuit 71 composed of such blocks can generate a necessary number of clock signals having a certain period with the CHIP_READY signal and the CLKoff_R signal as triggers.

  In general, in a semiconductor memory device, various potentials (step-down potential, step-up potential, negative potential, etc.) used inside a chip are generated by a power supply circuit provided inside the chip. As shown in FIG. 14, after the power is turned on, the power supply voltage Vcc rises to a predetermined potential with a certain slope, the power supply voltage rises to the predetermined potential, and the internal potential generated inside the chip is a desired level. When the potential is reached, the signal CHIP_READY signal indicating that the chip is ready for operation transitions from the “L” state to the “H” state. In the clock generation circuit 71, after the power is turned on, the CHIP_READY signal is triggered by a transition from “L” to “H”, and the clock signal FRTCLK for the number of clocks [m × (n + 1) +1] is started from time t3. Is generated. Furthermore, when the CHIP_READY signal is in the “H” state, the CLKoff_R signal is used as a trigger, and when the CLKoff_R signal transitions from the “L” state to the “H” state, the row clock signal FRTCLK stops, and the time t4 is set as the start time. A column clock signal FCTCLK having the number of clocks [m × (n + 1) +1] is generated.

Next, at time t5, the CLKoff_C signal changes from the “L” state to the “H” state, and the column internal clock signal FCTCLK is stopped.

  In the clock generation circuit 71 applied to the semiconductor memory device according to the third embodiment of the present invention, as in the first embodiment, the CHIP_READY signal is used as a trigger to operate the ring oscillator circuit for rows first. A row clock signal FRTCLK is generated. As shown in FIG. 14, when the row clock signal FRTCLK is generated [m × (n + 1) +1] times as many times as necessary for parallel-to-serial conversion, the CLKoff_R signal changes from “L” to “H” and the ring oscillator for row The circuit is stopped, and thereafter the row clock signal FRTCLK is not generated. Next, in response to the transition of the CLKoff_R signal from “L” to “H”, the column ring oscillator circuit operates this time to generate the column clock signal FCTCLK. When the column clock signal FCTCLK is generated [m × (n + 1) +1] times as many times as necessary for parallel-to-serial conversion, the CLKoff_C signal changes from “L” to “H”, and the column ring oscillator circuit is stopped. The column clock signal FCTCLK is not generated. That is, the number of clocks required for parallel-serial conversion in the clock generation circuit 71 of this embodiment is 2 × [m, which is twice the [m × (n + 1) +1] times required in the first embodiment. × (n + 1) +1] times.

  In the semiconductor memory device according to the third embodiment of the present invention as described above, the fuse information data output from the fuse block is converted into one serial data by the parallel-serial conversion as in the first embodiment. The serial data is synchronized with the clock and sequentially transferred to the replacement control circuit arranged in the vicinity of the row decoder and column decoder, so that the location of the redundancy fuse block can be freely determined without sacrificing the access speed. . In the third embodiment of the present invention, the number of circuits operating simultaneously during the parallel-serial conversion is half that of the first exemplary embodiment, so that the peak power consumed during the parallel-serial conversion is reduced. There is also an effect of suppressing the halving.

[Fourth embodiment]
As shown in FIG. 15, the configuration of the semiconductor memory device according to the fourth embodiment of the present invention includes a plurality of memory cells selected by a matrix address signal, and includes a normal cell array 10 and redundant cell arrays 101 and 102. A memory cell array 100, a row decoder 12 and a column decoder 14 for selectively driving word lines and column select lines included in the memory cell array 100, and a row fuse block for outputting redundancy replacement information for the word lines and column select lines, respectively. 24, a column fuse block 26, a row replacement control circuit 20 for controlling spare replacement of word lines and column select lines based on redundancy replacement information of word lines and column select lines, and a column replacement control circuit 22, respectively. Word line redundancy A row parallel-serial conversion circuit 66 and a row serial-parallel conversion circuit 62, which serially and parallel-convert the serial replacement information in synchronization with the externally input row clock signal FRTCLK and sequentially transfer the row replacement information to the row replacement control circuit 20; The column replacement conversion circuit 68 and the column serial conversion are sequentially transferred to the column replacement control circuit 22 after serial conversion and parallel conversion of the redundancy replacement information of the column select line in synchronization with the column clock signal FCTCLK inputted externally. Circuit 64.

  As the external input clock signal, the external clock signal FRTCLK for row and the external clock signal FCTCLK for column are input independently, and the replacement for row of the redundancy replacement information of the word line is synchronized with the external clock signal FRTCLK for row. As soon as the transfer to the control circuit 20 is completed, the redundancy replacement information of the column select line may be transferred to the column replacement control circuit 22 in synchronization with the column external clock signal FCTCLK. Alternatively, the transfer to the replacement control circuit 20 for the row may be performed after the transfer to the replacement control circuit 22 for the column.

  In the semiconductor memory device according to the fourth embodiment of the present invention, as in the third embodiment, the replacement control circuit 20 controls the replacement of the row decoder 12 with m spare word lines WL, The replacement control circuit 22 controls replacement of the column decoder 14 with m spare column selection lines CSL. The low fuse block 24 is divided into a total number m of fuse sets 28, and each divided fuse set 28 includes a total number of n + 1 fuses. Similarly, the column fuse block 26 is divided into a total number m of fuse sets 30, and each divided fuse set 30 includes a total number of n + 1 fuses.

  Further, in the fourth embodiment of the present invention, as in the third embodiment, (m × (n + 1)) pieces of fuse information data output in parallel from the row fuse block 24 are converted into a row clock signal. A parallel serial conversion circuit (paraserial conversion circuit) 66 for converting to a serial data signal on one serial data line by FRTCLK, and serial data on one serial data line (m × ( n + 1)) serial / parallel conversion circuit (serial conversion circuit) 62 for converting parallel data on the parallel data signal lines, and (m × (n + 1)) pieces of fuse information data output in parallel from the column fuse block 26 The column clock signal FCTCLK is converted into serial data transferred on one serial signal line. A column that converts serial data on one serial data line into parallel data on (m × (n + 1)) parallel data signal lines by a parallel-to-serial conversion circuit (paraserial conversion circuit) 68 for the RAM and a column clock signal FCTCLK. And a serial-parallel conversion circuit (serial-parallel conversion circuit) 64.

  However, in the fourth embodiment of the present invention, unlike the third embodiment, the clock generation circuit 71 for generating the row clock signal FRTCLK and the column clock signal FCTCLK used for the parallel-serial conversion and the serial-parallel conversion is provided as a chip. It has a circuit configuration that is not provided inside.

  That is, unlike the third embodiment, the fourth embodiment of the present invention has a circuit configuration in which the row clock signal FRTCLK and the column clock signal FCTCLK are input from the outside of the chip. Also in the semiconductor memory device according to the fourth embodiment as described above, by inputting the necessary number of clock signals necessary for the parallel-serial conversion from the outside of the chip separately for each row / column, Similarly, the fuse information data output from the fuse block is converted into one serial data by parallel conversion, and the serial data is synchronized with the clock, and the replacement control circuit 20 sequentially arranged in the vicinity of the row decoder 12 and the column decoder 14. , 22 can freely determine the arrangement location of the redundancy fuse block without sacrificing the access speed. Further, unlike the first and third embodiments, the fourth embodiment does not have a clock generation circuit inside the chip, so that the layout area can be further reduced, that is, the chip size, as in the second embodiment. As well as the third embodiment, since the transfer clock is divided for the row and the column as in the third embodiment, there is also an effect of suppressing the power consumption during fuse information data transfer.

[Other embodiments]
As described above, the present invention has been described according to the first to fourth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, embodiments, and operational techniques will be apparent to those skilled in the art.

  In the description of the first to fourth embodiments, the example in which the redundancy circuit is implemented mainly on both sides of the row system and the column system has been described. However, the redundancy circuit is implemented on one side of the row system or the column system. Of course, it is also good.

  Furthermore, in the semiconductor memory device according to the first to fourth embodiments of the present invention, as the circuit configuration of the memory cell array, not only a normal DRAM but also other memory formats such as SRAM and EPROM can be applied. . For example, a nonvolatile semiconductor memory device such as a NAND type, a NOR type, and an AND type can be applied.

 As described above, the present invention naturally includes various embodiments not described herein. Accordingly, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. 1A is a block diagram illustrating a configuration of a clock generation circuit in FIG. 1, FIG. 2B is a block diagram illustrating a configuration of a ring oscillator block in FIG. 1A, and FIG. 2C is a clock generation timing diagram of the clock generation circuit in FIG. FIG. 2 is a block diagram showing a configuration of a row and column parallel-serial conversion circuit in FIG. 1. (A) Circuit configuration diagram of the parallel-serial conversion circuit block in FIG. 3, (b) Circuit configuration diagram of the serial data transfer circuit in (a), (c) Circuit configuration diagram of the serial data output circuit in (a). (A) Operation timing waveform diagram of control clock generation circuit, (b) Circuit configuration diagram of control clock generation circuit, (c) Circuit configuration diagram of paraserial control circuit in FIG. 3, (d) Circuit configuration diagram of latch timing generation circuit (E) Operation timing waveform chart of latch timing generation circuit. FIG. 2 is a block diagram showing a configuration of a row and column serial-parallel conversion circuit in FIG. 1. (A) The circuit block diagram of the serial-parallel conversion circuit block in FIG. 6, (b) The circuit block diagram of the parallel data transfer circuit in (a). 6A is a circuit configuration diagram of the serial para control circuit in FIG. 6, FIG. 6B is a circuit configuration diagram of a control clock generation circuit in FIG. 6A, and FIG. 7C is an operation timing waveform diagram of the control clock generation circuit in FIG. Explanatory drawing of operation | movement block to serial-parallel conversion in the 1st Embodiment of this invention. FIG. 5 is an operation timing waveform diagram up to serial-parallel conversion according to the first embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. FIG. 5 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention. In the third embodiment of the present invention, (a) a circuit configuration diagram of the clock generation circuit, (b) a circuit configuration diagram of the ring oscillator block 184 of (a), and (c) a configuration of the ring oscillator block 186 of (a). FIG. FIG. 11 is an operation timing waveform diagram of the clock generation circuit in the third embodiment of the present invention. FIG. 6 is a block diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention. (A) A block diagram showing a configuration of a semiconductor memory device according to a study example of an embodiment of the present invention, (b) a configuration diagram of a row fuse block of (a), and (c) a configuration of a column fuse block of (a). Figure. (A) The block diagram which shows the structure of the replacement control circuit in the examination example, (b) The circuit block diagram of the normal control circuit of (a). FIG. 17A is a block diagram of the spare control circuit in FIG. 17A, FIG. 17B is a circuit diagram of the address comparison circuit in FIG. 17A, and FIG. 17C is a circuit diagram of the spare determination circuit in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Normal cell array 12 ... Row decoder 14 ... Column decoder 16 ... Row redundancy circuit 18 ... Column redundancy circuit 20, 22 ... Replacement control circuit 24 ... Row fuse block 26 ... Column fuse block 62 ... Row serial-parallel conversion circuit 64 ... Column use Serial conversion circuit 66... Row parallel conversion circuit 68... Column parallel conversion circuits 70 and 71... Clock generation circuit 100... Memory cell array 101 and 102 .. redundant cell array 104.

Claims (5)

A row decoder and a column decoder for selectively driving a word line and a column select line, respectively;
A row fuse block and a column fuse block for outputting redundancy replacement information of the word line and the column select line, respectively;
A row replacement control circuit and a column replacement control circuit for controlling spare replacement of the word line and the column select line based on redundancy replacement information of the word line and the column select line, respectively;
A row parasitic conversion circuit and a row serial conversion circuit for sequentially transferring the redundancy replacement information of the word line to the row replacement control circuit in synchronization with an internal clock signal for row;
A semiconductor comprising: a column parallel conversion circuit and a column serial conversion circuit for sequentially transferring redundancy replacement information of the column select line to the column replacement control circuit in synchronization with an internal clock signal for the column Storage device.   The row internal clock signal and the column internal clock signal are generated separately, and in synchronization with the row internal clock signal, the row replacement control circuit for the redundancy replacement information of the word line Upon completion of transfer to the column, in synchronization with the internal clock signal for the column, transfer of redundancy replacement information of the column select line to the replacement control circuit for the column, or transfer to the replacement control circuit for the column The semiconductor memory device according to claim 1, further comprising a clock generation circuit that performs transfer to the row replacement control circuit next to the row.   The row internal clock signal is generated by using an internal signal generated when the power is turned on as a trigger, and the transfer of the word line redundancy replacement information to the row replacement control circuit is completed during the power-up period. The semiconductor memory device according to claim 1, further comprising a clock generation circuit that finishes transferring the redundancy replacement information of the column selection line to the replacement control circuit for the column. A row decoder and a column decoder for selectively driving a word line and a column select line, respectively;
A row fuse block and a column fuse block for outputting redundancy replacement information of the word line and the column select line, respectively;
A row replacement control circuit and a column replacement control circuit for controlling spare replacement of the word line and the column select line based on redundancy replacement information of the word line and the column select line, respectively;
A row-to-row serial conversion circuit and a row-to-row serial conversion circuit that serially and parallel converts the redundancy replacement information of the word line in synchronization with a clock signal to be input externally and sequentially transferred to the row replacement control circuit;
A column parallel conversion circuit and a column serial conversion circuit for serially converting and parallel converting the redundancy replacement information of the column select line in synchronization with a clock signal to be externally input and sequentially transferring to the column replacement control circuit; A semiconductor memory device. As the external input clock signal, an external clock signal for row and an external clock signal for column are input independently, and in synchronization with the external clock signal for row, the redundancy replacement information for the row for the word line is used. As soon as the transfer to the replacement control circuit is completed, the redundancy replacement information on the column select line is transferred to the replacement control circuit for the column or the replacement control circuit for the column in synchronization with the external clock signal for the column. 5. The semiconductor memory device according to claim 4, wherein the transfer to the row replacement control circuit is performed next to the transfer to the row.

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