CN210489253U - Test circuit and test jig for integrating USB2.0 and USB3.0 communication chips - Google Patents
Test circuit and test jig for integrating USB2.0 and USB3.0 communication chips Download PDFInfo
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- CN210489253U CN210489253U CN201921521474.5U CN201921521474U CN210489253U CN 210489253 U CN210489253 U CN 210489253U CN 201921521474 U CN201921521474 U CN 201921521474U CN 210489253 U CN210489253 U CN 210489253U
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Abstract
The utility model discloses a test circuit and test jig for integrating USB2.0 and USB3.0 communication chips, wherein, the test circuit for integrating USB2.0 and USB3.0 communication chips comprises a USB2.0 interface module, a USB3.0 interface module, a USB interface switching module, a signal input/output switching module, a flash memory control module and a flash memory module; the USB2.0 interface module and the USB3.0 interface module are respectively connected with the USB interface switching module, the USB interface switching module is connected with the signal input/output switching module, the signal input/output switching module is connected with the flash memory control module, the flash memory control module is connected with the flash memory module, and the flash memory control module is used for controlling the flash memory module to carry out data transmission with peripheral equipment through the USB2.0 interface module or the USB3.0 interface module according to the conduction condition of an internal circuit of the USB interface switching module. Compared with the prior art, when testers need to test the memory chips at different transmission speeds, the circuit board packaged with the memory chips to be tested does not need to be detached from the original test frame, and damage to pins or golden fingers of the circuit board is reduced.
Description
Technical Field
The utility model relates to memory chip test field especially involves a test circuit and test jig who integrates USB2.0 and USB3.0 communication chip.
Background
Before the memory chip is on the market, the memory chip needs to be tested, and the specific test contents are the data transmission speed of the memory chip, the error rate of file copying and the like. In the prior art test, a tester packages a memory chip to be tested on a circuit Board by a COB (chip on Board) method, and tests the memory chip by inserting the circuit Board loaded with the memory chip to be tested on a chip testing jig, wherein the chip testing jig includes a USB interface, a memory control chip, and the like. Only one USB interface is used on the existing test jig, if the memory chip to be tested needs to be tested at different transmission speeds, the test jig with different USB interfaces needs to be replaced, and the circuit board with the memory chip to be tested is repeatedly plugged from the test jig, so that pins or golden fingers of the circuit board are easily damaged.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing an integrate USB2.0 and USB3.0 communication chip's test circuit, aim at solving the circuit board that is packaged with the examination memory chip that awaits measuring and because of changing the USB interface, the plug has the circuit board that awaits measuring memory chip from the test jig repeatedly, causes the stitch of circuit board or the problem that the golden finger damaged.
The utility model provides a test circuit for integrating USB2.0 and USB3.0 communication chips, which comprises a USB2.0 interface module, a USB3.0 interface module, a USB interface switching module, a signal input/output switching module, a flash memory control module and a flash memory module;
the USB2.0 interface module and the USB3.0 interface module are respectively connected with the USB interface switching module, the USB interface switching module is connected with the signal input/output switching module, the signal input/output switching module is connected with the flash memory control module, the flash memory control module is connected with the flash memory module, and the flash memory control module is used for controlling the flash memory module to carry out data transmission with peripheral equipment through the USB2.0 interface module or the USB3.0 interface module according to the conduction condition of an internal circuit of the USB interface switching module.
Preferably, the USB2.0 interface module includes a USB2.0 interface, the USB3.0 interface module includes a USB3.0 interface, and the USB interface switching module is a power switch;
the input end of the power supply changeover switch comprises a first input end and a second input end;
the input end of the power supply changeover switch comprises a first output end and a second output end;
the first input end of the power supply change-over switch is connected with the power supply output end of the USB2.0 interface, and the first output end of the power supply change-over switch is connected with the first power supply input end of the signal input and output change-over module;
the second input end of the power supply change-over switch is connected with the power supply output end of the USB3.0 interface, and the second output end of the power supply change-over switch is connected with the second power supply input end of the signal input and output change-over module.
Preferably, the signal input/output switching module comprises a signal input/output switching control chip for switching a power supply voltage source received by the flash memory control module, and a USB signal and data source;
a USB2.0 signal input/output pin of the USB2.0 interface is used as a USB2.0 signal output end to be connected with a USB2.0 signal input end of the signal input/output switching chip, a ground wire of the USB2.0 interface is grounded at the same time, and a positive power supply pin of the USB2.0 interface is used as a power supply output end of the USB2.0 interface module to be connected with a first input end of the power supply switching switch;
a first input pin of the power supply change-over switch is used as a first input end of the power supply change-over switch and is connected with a first power supply output end of the USB2.0 interface, and a first output pin of the power supply change-over switch is used as a first output end and is connected with a first power supply input end of the signal input and output change-over chip;
a USB3.0 signal input/output pin of the USB3.0 interface is used as a USB3.0 signal output end to be connected with a USB3.0 signal input end of the signal input/output switching chip, a ground wire of the USB3.0 interface is grounded at the same time, and a positive power supply pin of the USB3.0 interface is used as a power supply output end of the USB3.0 interface module 3 to be connected with a second input end of the power supply switching switch;
a second input pin of the power supply change-over switch is used as a second input end of the power supply change-over switch and is connected with a power supply output end of the USB3.0 interface module, and a second output pin of the power supply change-over switch is used as a second output end and is connected with a second power supply input end of the signal input and output change-over control chip;
and a positive power supply pin of the signal input and output switching chip is used as a power supply output end of the signal input and output switching chip and is simultaneously connected with a power supply input end of the flash memory control module and a power supply input end of the flash memory module.
Preferably, the test circuit for integrating the USB2.0 and USB3.0 communication chips further includes a voltage stabilizing capacitor C1 and a voltage stabilizing capacitor C2;
a first output end of the power supply changeover switch is connected with a first power supply input end of the signal input and output changeover chip through a voltage stabilizing capacitor C2;
and a second output end of the power supply changeover switch is connected with a second power supply input end of the signal input and output changeover chip through a voltage stabilizing capacitor C1.
Preferably, the flash memory control module comprises a flash memory control chip, and the flash memory control chip is used for controlling the flash memory module to read and write data;
a USB2.0 signal input/output pin of the flash memory control chip is used as a USB2.0 signal input end to be connected with a USB2.0 signal output end of the signal input/output switching chip, and a USB3.0 signal input/output pin of the flash memory control chip is used as a USB3.0 signal input end to be connected with a USB3.0 signal output end of the signal input/output switching chip;
a power supply positive pin of the flash memory control chip is used as a power supply input end of the flash memory control chip and is connected with a power supply output end of the signal input and output switching chip;
the cathode of the power supply of the flash memory control chip is grounded at the same time.
Preferably, the flash memory module is a flash memory chip, and the flash memory chip is used for reading and writing data;
the signal input end of the flash memory is connected with the signal output end of the flash memory control chip;
the power supply anode pin of the flash memory chip is used as the power supply input end of the flash memory chip to be connected with the power supply output end of the signal input and output switching chip, and the power supply cathode of the flash memory chip is simultaneously grounded.
Preferably, the output voltage of the USB2.0 interface module and the output voltage of the USB3.0 interface module are both 5.0V.
The utility model also provides an integrate USB2.0 and USB3.0 communication chip's test jig contains foretell integrated USB2.0 and USB3.0 communication chip's test circuit.
The beneficial effects of the utility model reside in that: the USB2.0 interface module and the USB3.0 interface module are respectively electrically connected with the USB interface switching module, the USB interface switching module selects the conduction condition of an internal circuit of the USB interface switching module according to the operation of a tester, so that the USB2.0 interface module is electrically connected with the USB interface switching module, the signal input/output switching module, the flash memory control module and the flash memory module in sequence, or the USB3.0 interface module is electrically connected with the USB interface switching module, the signal input/output switching module, the flash memory control module and the flash memory module in sequence. Therefore, the memory chip to be tested can select the USB2.0 communication protocol or the USB3.0 communication protocol to transmit data with peripheral equipment in the test circuit according to the operation of workers, and the test of the memory chip is completed. Through the arrangement, when a tester needs to test the memory chips at different transmission speeds, the circuit board packaged with the memory chips to be tested does not need to be detached from the original test rack and is loaded to a new test rack with different USB interfaces, the tester only needs to operate the USB interface switching module, the memory chips to be tested can be tested at different transmission speeds (namely the new USB interfaces), the memory chips are tested, the process does not need to plug the circuit board with the memory chips to be tested, and damage to pins or golden fingers of the circuit board is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a test circuit for integrating USB2.0 and USB3.0 communication chips according to an embodiment of the present invention;
fig. 2 is an example of the circuit diagram of fig. 1.
Description of reference numerals:
1. a USB2.0 interface module; 2. a USB interface switching module; 3. a USB3.0 interface module; 4. a signal input/output switching module; 5. a flash memory control module; 6. a flash memory module.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the utility model provides a test circuit for integrating USB2.0 and USB3.0 communication chips, which comprises a USB2.0 interface module 1, a USB3.0 interface module 3, a USB interface switching module 2, a signal input/output switching module 4, a flash memory control module 5 and a flash memory module 6;
USB2.0 interface module 1 and USB3.0 interface module 3 are connected with USB interface switch module 2 respectively, USB interface switch module 2 connects signal input output switch module 4, signal input output switch module 4 and flash memory control module 5 connect, flash memory control module 5 and flash memory module 6 connect, flash memory control module 5 is used for switching on the condition according to the internal circuit of USB interface switch module 2, come control flash memory module 6 to carry out data transmission through USB2.0 interface module 1 or USB3.0 interface module 3 with peripheral equipment.
The embodiment of the utility model provides an in, USB2.0 interface module 1 and USB3.0 interface module 3 all are used for providing voltage to test circuit's components and parts to and carry out data transmission with peripheral equipment. The USB interface switching module 2 is used to switch the USB interface used when the test circuit performs data transmission with the external device. The signal input/output switching module 4 is used for switching the source of the supply voltage received by the flash memory control module 5, and the source of the USB signal and the data. The flash memory control module 5 is used for controlling the flash memory module 6 to read and write data. The flash memory module 6 is used for reading and writing data. The USB2.0 interface module 1 and the USB3.0 interface module 3 are respectively electrically connected with the USB interface switching module 2, the USB interface switching module 2 selects the conduction condition of the internal circuit of the USB interface switching module 2 according to the operation of a tester, so that the USB2.0 interface module 1 is electrically connected with the USB interface switching module 2, the signal input/output switching module 4, the flash memory control module 5 and the flash memory module 6 in sequence, or the USB3.0 interface module 3 is electrically connected with the USB interface switching module 2, the signal input/output switching module 4, the flash memory control module 5 and the flash memory module 6 in sequence. Therefore, the memory chip to be tested can select the USB2.0 communication protocol or the USB3.0 communication protocol to transmit data with peripheral equipment in the test circuit according to the operation of workers, and the test of the memory chip is completed. Through the arrangement, when a tester needs to test the memory chips at different transmission speeds, the circuit board packaged with the memory chips to be tested does not need to be detached from the original test rack and is loaded to a new test rack with different USB interfaces, the tester only needs to operate the USB interface switching module 2 to form different test circuits, the memory chips to be tested can use different transmission speeds (namely, the new USB interfaces) to test the memory chips, the process does not need to plug the circuit board with the memory chips to be tested, and pin or golden finger damage of the circuit board is reduced.
Referring to fig. 2, the USB2.0 interface module 1 includes a USB2.0 interface, the USB3.0 interface module 3 includes a USB3.0 interface, and the USB interface switching module 2 is a power switch;
the input end of the power supply changeover switch comprises a first input end and a second input end;
the input end of the power supply changeover switch comprises a first output end and a second output end;
the first input end of the power supply change-over switch is connected with the power supply output end of the USB2.0 interface, and the first output end of the power supply change-over switch is connected with the first power supply input end of the signal input and output change-over module 4;
the second input end of the power supply change-over switch is connected with the power supply output end of the USB3.0 interface, and the second output end of the power supply change-over switch is connected with the second power supply input end of the signal input and output change-over module 4.
In the embodiment of the present invention, the USB interface switching module 2 is a power switch. The first input terminal and the second input terminal of the power switch are pin In1 and pin In2, respectively. The first and second outputs of the power switch are pin Out1 and pin Out2, respectively. The first input end of the power supply change-over switch is connected with the power supply output end of the USB2.0 interface, the first output end of the power supply change-over switch is connected with the first power supply input end of the signal input and output change-over module 4, namely, the pin In1 and the pin Out1 form a first circuit channel, when the first circuit channel is conducted, the USB2.0 interface, the power supply change-over switch, the signal input and output change-over module 4, the flash memory control module 5 and the flash memory module 6 are sequentially electrically connected, and the test circuit can test the memory chip by using a USB2.0 communication protocol. The second input end of the power supply change-over switch is connected with the power supply output end of the USB3.0 interface, the second output end of the power supply change-over switch is connected with the second power supply input end of the signal input and output change-over module 4, namely, the pin In2 and the pin Out2 form a second circuit channel, when the second circuit channel is conducted, the USB3.0 interface, the power supply change-over switch, the signal input and output change-over module 4, the flash memory control module 5 and the flash memory module 6 are sequentially electrically connected, and the test circuit can test the memory chip by using a USB3.0 communication protocol. In other embodiments of the present invention, when only the USB2.0 interface or the USB3.0 interface is provided in the test circuit, the power switch only functions to connect and disconnect the USB interface, and cannot switch the USB2.0 interface or the USB3.0 interface.
Referring to fig. 2, the signal input/output switching module 4 includes a signal input/output switching control chip for switching a source of the received supply voltage of the flash memory control module 5 and a source of the USB signal and data;
a USB2.0 signal input/output pin of the USB2.0 interface is used as a USB2.0 signal output end to be connected with a USB2.0 signal input end of the signal input/output switching chip, a ground wire of the USB2.0 interface is grounded at the same time, and a positive power supply pin of the USB2.0 interface is used as a power supply output end of the USB2.0 interface module 1 to be connected with a first input end of the power supply switching switch;
a first input pin of the power supply change-over switch is used as a first input end of the power supply change-over switch and is connected with a first power supply output end of the USB2.0 interface, and a first output pin of the power supply change-over switch is used as a first output end and is connected with a first power supply input end of the signal input and output change-over chip;
a USB3.0 signal input/output pin of the USB3.0 interface is used as a USB3.0 signal output end to be connected with a USB3.0 signal input end of the signal input/output switching chip, a ground wire of the USB3.0 interface is grounded at the same time, and a positive power supply pin of the USB3.0 interface is used as a power supply output end of the USB3.0 interface module 3 to be connected with a second input end of the power supply switching switch;
a second input pin of the power supply change-over switch is used as a second input end of the power supply change-over switch and is connected with a power supply output end of the USB3.0 interface module 3, and a second output pin of the power supply change-over switch is used as a second output end and is connected with a second power supply input end of the signal input and output change-over control chip;
the positive power supply pin of the signal input and output switching chip is used as the power supply output end of the signal input and output switching chip and is simultaneously connected with the power supply input end of the flash memory control module 5 and the power supply input end of the flash memory module 6.
In the embodiment of the present invention, the USB2.0 signal input/output pins (pin VD-and pin VD +) of the USB2.0 interface are used as the USB2.0 signal output terminal to connect with the USB2.0 signal input terminal of the signal input/output switching chip, wherein the USB2.0 signal input terminal of the signal input/output switching chip is the first VD-pin and the first VD + pin; the ground GND of the USB2.0 interface is grounded at the same time, and the positive power pin VCC of the USB2.0 interface is connected to the first input terminal (i.e., pin In1) of the power switch as the power supply output terminal of the USB2.0 interface module 1. A pin In1 of the power switch serves as a first input terminal of the power switch and is connected to a first power supply output terminal (i.e., a positive power supply pin VCC) of the USB2.0 interface, and a pin Out1 of the power switch serves as a first output terminal and is connected to a first power supply input terminal (i.e., a first VCC pin) of the signal input/output switching chip. The USB3.0 signal input/output pin (including pins SSRX +, SSRX-, DM, AGND, DP, SSTX +, SSTX-) of the USB3.0 interface is connected with the USB3.0 signal input end (including pins first SSRX +, first SSRX-, first DM, first AGND, first DP, first SSTX +, and first SSTX-) of the signal input/output switching chip as the USB3.0 signal output end. The GND pin of the USB3.0 interface is grounded. The positive power supply pin VBUS of the USB3.0 interface is connected to the second input terminal (pin In2) of the power supply switch as the power supply output terminal of the USB3.0 interface module 3. A second input pin In2 of the power switch is connected to the power supply output terminal (pin VBUS) of the USB3.0 interface module 3. A second output pin Out2 of the power switch serves as a second output terminal to connect to a second power supply input terminal (pin VBUS) of the signal input/output switching control chip. The positive power pin (second VCC pin) of the signal input output switching chip is used as the power supply output terminal of the signal input output switching chip and is simultaneously connected to the power supply input terminal of the flash memory control module 5 and the power supply input terminal of the flash memory module 6. When the power switch is connected to the first circuit channel, the first positive power pin VCC of the signal input/output switching chip is connected to the first input terminal (i.e., Out1 pin) of the power switch as the first power input terminal of the signal input/output switching module 4, after the signal input/output switching chip recognizes a VCC power signal, the signal input/output pins (i.e., the first VD + pin and the first VD-pin) of the USB2.0 signal input terminal of the signal input/output switching chip are connected to the USB2.0 signal output terminals (i.e., the VD + pin and the VD-pin) of the USB2.0 interface, and the USB3.0 signal input terminal of the signal input/output switching chip is disconnected from the USB3.0 interface (i.e., the first SSRX +, the first SSRX-, the first DM, the first AGND, the first DP, the first SSTX +, the first SSTX-pin, and the SSRX +, SSRX-, and SSRX-, of the USB3.0 interface are disconnected, DM, AGND, DP, SSTX +, SSTX-pins), so that the test circuit cannot receive signals of the USB3.0 interface and cannot transmit data using the USB3.0 communication protocol. When the power switch switches on the second circuit channel, the second positive power pin VBUS of the signal input/output switching chip is connected to the second output terminal (i.e., pin Out2) of the power switch as the second power supply input terminal of the signal input/output switching module 4. After the signal input/output switching chip recognizes the VBUS power signal, the signal input/output pins (namely, the first SSRX +, the first SSRX-, the first DM, the first AGND, the first DP, the first SSTX +, and the first SSTX-pin) of the USB3.0 signal input end of the signal input/output switching chip are switched on, so that the signal input/output pins are connected with the USB3.0 signal input end (namely, the SSRX +, the SSRX-, the DM, the AGND, the SSDP, the SSTX +, and the X-pin) of the USB3.0 interface. Meanwhile, the USB2.0 signal input end of the signal input/output switching chip is disconnected from the USB2.0 interface (namely, the first VD + pin and the first VD-pin of the signal input/output switching chip are disconnected from the VD + pin and the VD-pin of the USB3.0 interface), so that the test circuit cannot receive signals of the USB2.0 interface and cannot transmit data by using a USB2.0 communication protocol. To sum up, when the power switch is connected to the first circuit channel, the signal input/output switching chip connects the USB2.0 communication protocol port, disconnects the USB3.0 communication protocol port, and performs data transmission using the USB2.0 communication protocol; when the power supply changeover switch is connected with the second circuit channel, the signal input and output changeover chip is connected with the USB3.0 communication protocol port and is disconnected with the USB2.0 communication protocol port, and data transmission is carried out by adopting the USB3.0 communication protocol.
Referring to fig. 2, the test circuit for integrating USB2.0 and USB3.0 communication chips further includes a voltage stabilizing capacitor C1 and a voltage stabilizing capacitor C2;
a first output end of the power supply changeover switch is connected with a first power supply input end of the signal input and output changeover chip through a voltage stabilizing capacitor C2;
and a second output end of the power supply changeover switch is connected with a second power supply input end of the signal input and output changeover chip through a voltage stabilizing capacitor C1.
In the embodiment of the present invention, the first output terminal of the power switch is connected to the first power input terminal of the signal input/output switching chip through the voltage-stabilizing capacitor C2; and a second output end of the power supply changeover switch is connected with a second power supply input end of the signal input and output changeover chip through a voltage stabilizing capacitor C1. In the embodiment of the present invention, the output voltage of the USB2.0 interface module 1 and the USB3.0 interface module 3 is 5.0V. Through the arrangement, the power supply voltage received by the power supply input end of the signal input/output switching chip is more stable.
Referring to fig. 2, the flash memory control module 5 includes a flash memory control chip for controlling the flash memory module 6 to read and write data;
a USB2.0 signal input/output pin of the flash memory control chip is used as a USB2.0 signal input end to be connected with a USB2.0 signal output end of the signal input/output switching chip, and a USB3.0 signal input/output pin of the flash memory control chip is used as a USB3.0 signal input end to be connected with a USB3.0 signal output end of the signal input/output switching chip;
a power supply positive pin of the flash memory control chip is used as a power supply input end of the flash memory control chip and is connected with a power supply output end of the signal input and output switching chip;
the cathode of the power supply of the flash memory control chip is grounded at the same time.
In the embodiment of the present invention, the USB2.0 signal input/output pins (VD-pin and VD + pin) of the flash memory control chip are used as the USB2.0 signal input terminal to connect with the USB2.0 signal output terminal (i.e. the second VD-pin and the second VD + pin) of the signal input/output switching chip; the USB3.0 signal input/output pin (i.e. the SSRX +, SSRX-, DM, AGND, DP, SSTX +, SSTX-) of the flash memory control chip is connected with the USB3.0 signal output terminal (i.e. the second SSRX +, second SSRX-, second DM, second AGND, second DP, second SSTX +, second SSTX-) of the signal input/output switching chip. The power supply positive electrode pin VCC of the flash memory control chip is used as a power supply input end of the flash memory control chip and is connected with a power supply output end (namely a second VCC pin) of the signal input and output switching chip, and the WP pin, the SE pin and the power supply negative electrode VSS pin of the flash memory control chip are grounded simultaneously.
Referring to fig. 2, the flash memory module 6 is a flash memory chip, and the flash memory chip is used for reading and writing data;
the signal input end of the flash memory is connected with the signal output end of the flash memory control chip;
the power supply anode pin of the flash memory chip is used as the power supply input end of the flash memory chip to be connected with the power supply output end of the signal input and output switching chip, and the power supply cathode of the flash memory chip is simultaneously grounded.
In the embodiment of the present invention, the signal input terminals (i.e., pins R/B, CLE, CE, ALE, WE, RE, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, and I/O7) of the flash memory chip are connected to the signal output terminals (i.e., pins R/B, CLE, CE, ALE, WE, RE, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, and I/O7) of the flash memory control chip. The power supply positive electrode pin VSS of the flash memory chip is used as a power supply input end of the flash memory chip and is connected with a power supply output end (namely a second VSS pin) of the signal input and output switching chip, and the power supply negative electrode (namely the VSS pin) of the flash memory chip is grounded at the same time.
The utility model also provides an integrate USB2.0 and USB3.0 communication chip's test jig contains foretell integrated USB2.0 and USB3.0 communication chip's test circuit.
The embodiment of the utility model provides an in, when the testing personnel need test storage chip with different transmission speed, the circuit board that need not to be packaged with the storage chip that awaits measuring is dismantled from former test jig, load the new test jig that has different USB interfaces, only need the testing personnel to operate USB interface switching module 2 in original test jig, the storage chip that awaits measuring can be with different transmission speed (new USB interface promptly), test storage chip, above-mentioned process need not the plug and has the circuit board that awaits measuring storage chip, reduce the stitch or the golden finger damage of circuit board.
The above only is the preferred embodiment of the present invention, not limiting the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the same way in the protection scope of the present invention.
Claims (8)
1. A test circuit for integrating USB2.0 and USB3.0 communication chips is characterized by comprising a USB2.0 interface module, a USB3.0 interface module, a USB interface switching module, a signal input/output switching module, a flash memory control module and a flash memory module;
the USB2.0 interface module and the USB3.0 interface module are respectively connected with the USB interface switching module, the USB interface switching module is connected with the signal input/output switching module, the signal input/output switching module is connected with the flash memory control module, the flash memory control module is connected with the flash memory module, and the flash memory control module is used for controlling the flash memory module to carry out data transmission with peripheral equipment through the USB2.0 interface module or the USB3.0 interface module according to the conduction condition of an internal circuit of the USB interface switching module.
2. The testing circuit of claim 1, wherein the USB2.0 interface module comprises a USB2.0 interface, the USB3.0 interface module comprises a USB3.0 interface, and the USB interface switching module is a power switch;
the input end of the power supply changeover switch comprises a first input end and a second input end;
the input end of the power supply changeover switch comprises a first output end and a second output end;
the first input end of the power supply change-over switch is connected with the power supply output end of the USB2.0 interface, and the first output end of the power supply change-over switch is connected with the first power supply input end of the signal input and output change-over module;
and the second input end of the power supply change-over switch is connected with the power supply output end of the USB3.0 interface, and the second output end of the power supply change-over switch is connected with the second power supply input end of the signal input and output change-over module.
3. The testing circuit of claim 2, wherein the signal input/output switching module comprises a signal input/output switching control chip for switching a power supply voltage source received by the flash memory control module and a USB signal and data source;
a USB2.0 signal input/output pin of the USB2.0 interface is used as a USB2.0 signal output end and connected with a USB2.0 signal input end of the signal input/output switching chip, a ground wire of the USB2.0 interface is grounded at the same time, and a positive power supply pin of the USB2.0 interface is used as a power supply output end of the USB2.0 interface module and connected with the first input end of the power supply switching switch;
a first input pin of the power supply changeover switch is used as the first input end of the power supply changeover switch and is connected with the first power supply output end of the USB2.0 interface, and a first output pin of the power supply changeover switch is used as the first output end and is connected with a first power supply input end of the signal input and output changeover chip;
a USB3.0 signal input/output pin of the USB3.0 interface is used as a USB3.0 signal output end and connected with a USB3.0 signal input end of the signal input/output switching chip, a ground wire of the USB3.0 interface is grounded at the same time, and a positive power supply pin of the USB3.0 interface is used as a power supply output end of the USB3.0 interface module and connected with a second input end of the power supply switching switch;
a second input pin of the power supply change-over switch is used as the second input end of the power supply change-over switch to be connected with the power supply output end of the USB3.0 interface module, and a second output pin of the power supply change-over switch is used as the second output end to be connected with a second power supply input end of the signal input and output change-over control chip;
and a positive power supply pin of the signal input and output switching chip is used as a power supply output end of the signal input and output switching chip and is simultaneously connected with a power supply input end of the flash memory control module and a power supply input end of the flash memory module.
4. The test circuit of claim 3, further comprising a voltage-stabilizing capacitor C1 and a voltage-stabilizing capacitor C2;
the first output end of the power supply changeover switch is connected with a first power supply input end of the signal input and output changeover chip through the voltage stabilizing capacitor C2;
the second output end of the power supply changeover switch is connected with the second power supply input end of the signal input and output changeover chip through the voltage stabilizing capacitor C1.
5. The test circuit of claim 4, wherein the flash memory control module comprises a flash memory control chip for controlling the flash memory module to read and write data;
a USB2.0 signal input/output pin of the flash memory control chip is used as a USB2.0 signal input end and connected with a USB2.0 signal output end of the signal input/output switching chip, and a USB3.0 signal input/output pin of the flash memory control chip is used as a USB3.0 signal input end and connected with a USB3.0 signal output end of the signal input/output switching chip;
a power supply positive electrode pin of the flash memory control chip is used as a power supply input end of the flash memory control chip and is connected with a power supply output end of the signal input and output switching chip;
and the cathode of the power supply of the flash memory control chip is grounded at the same time.
6. The test circuit of claim 5, wherein the flash memory module is a flash memory chip, and the flash memory chip is used for reading and writing data;
the signal input end of the flash memory is connected with the signal output end of the flash memory control chip;
the power supply positive electrode pin of the flash memory chip is used as the power supply input end of the flash memory chip to be connected with the power supply output end of the signal input and output switching chip, and the power supply negative electrode of the flash memory chip is simultaneously grounded.
7. The testing circuit of claim 1, wherein the output voltages of the USB2.0 interface module and the USB3.0 interface module are both 5.0V.
8. A test rack for integrating USB2.0 and USB3.0 communication chips, comprising the test circuit of any one of claims 1 to 7 for integrating USB2.0 and USB3.0 communication chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921521474.5U CN210489253U (en) | 2019-09-12 | 2019-09-12 | Test circuit and test jig for integrating USB2.0 and USB3.0 communication chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921521474.5U CN210489253U (en) | 2019-09-12 | 2019-09-12 | Test circuit and test jig for integrating USB2.0 and USB3.0 communication chips |
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| Publication Number | Publication Date |
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| CN210489253U true CN210489253U (en) | 2020-05-08 |
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| CN201921521474.5U Active CN210489253U (en) | 2019-09-12 | 2019-09-12 | Test circuit and test jig for integrating USB2.0 and USB3.0 communication chips |
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| CN (1) | CN210489253U (en) |
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