CN209785942U - 异质接面双极性晶体管 - Google Patents
异质接面双极性晶体管 Download PDFInfo
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Abstract
本实用新型为提供一种异质接面双极性晶体管，包含基板、半导体单元、电极单元，及介电层。所述半导体单元形成于所述基板上，具有自所述基板表面向上形成的集极层、基极层，及射极层。所述电极单元具有设置于所述集极层的集极金属层、设置于所述基极层的基极金属层，及设置于所述射极层的射极金属层。所述介电层覆盖所述射极层，并定义出开口，所述基极金属层经由所述开口与所述基极层相接触，并延伸覆盖至少部分与所述开口相邻的所述介电层。借此，在提高所述基极金属层的高度时，同时精确控制基极金属层的宽度，以有效提高异质接面双极性晶体管的输出频率。
Description
技术领域
本实用新型涉及一种晶体管，特别是涉及一种异质接面双极性晶体管。
背景技术
为了符合高速无线通信系统的要求，主动组件必须具备有良好的高频特性及高功率输出等特性。其中，以Ⅲ-Ⅴ族(如GaN、GaAs)半导体材料制成的异质接面双极性晶体管(HBT)及高速电子迁移率晶体管(HEMT)等功率放大器，由于具有高功率、线性度佳、高截止频率和低损耗功率等优点，是目前被视为用于制作可符合5G的超高频通讯需求的功率放大器的最佳材料。
参阅图1，以异质接面双极性晶体管(HBT)1的功率放大器而言，所述异质接面双极性晶体管1包含基板11，形成于所述基板11上，以Ⅲ-Ⅴ族半导体材料制成，且具有自所述基板11表面依序向上形成的集极层121、基极层122，及射极层123的半导体单元12、设置于所述集极层121的集极金属层131、设置于所述基极层122的基极金属层132，及设置于所述射极层123的射极金属层133。其中，所述异质接面双极性晶体管1的输出频率能以式(I)的公式表示：
其中，fmax为最大输出频率，Rb表示所述基极金属层132的电阻，而Cbc则是基极层32跟集极层31接面的电容。
由前述式(I)可知，当要提高所述异质接面双极性晶体管1的输出频率时，可以借由减小所述基极金属层132的电阻及/或减小所述基极层122与集极层121接面的电容Cbc来达成。
一般减小所述基极金属层132的电阻Rb的方式，可以利用增加所述基极金属层132的宽度CD(也就是增加所述基极金属层132与所述基极层122的接触面积)，或是增加所述基极金属层132的高度H来达成。然而，增加所述基极金属层132的宽度CD虽然可降低电阻Rb，但却也会同时增加所述基极层122与跟集极层121接面的电容Cbc，而不利于输出频率。因此，目前的方向是利用固定基极金属层132的宽度CD，利用增加所述基极金属层132的高度H来达成提升输出频率的目的。
配合参阅图2，然而，因为目前所述基极金属层132的制程是先利用光阻(PR)定义出所述基极金属层132所需的宽度后再沉积金属而得。但是，光阻因显影时有底切(undercut)的情形产生，且光阻厚度越大，显影后底切现象越明显，因此，当要通过光阻定义，增加所述基极金属层132的高度以减小所述基极金属层132的电阻Rb时，于沉积形成基极金属层132的过程中，会沿着光阻底切部分延伸形成金属毛边(metal foot)130，且当沉积的高度越高形成的金属毛边130越严重。所述金属毛边130不仅会影响最终形成的所述基极金属层132与所述基极层122接触的宽度CD，使得所述基极金属层132的宽度CD无法被精确控制，而不利高频输出，且当组件尺寸发展越来越细微，凸出的金属毛边130还有可能接触到所述射极金属层133导致组件短路。
发明内容
本实用新型目的在于提供一种异质接面双极性晶体管。
本实用新型的所述异质接面双极性晶体管包含基板、半导体单元、电极单元，及介电层。
所述半导体单元，形成于所述基板上，具有自所述基板表面向上形成的集极层、基极层，及射极层。
所述电极单元具有设置于所述集极层的集极金属层、设置于所述基极层的基极金属层，及设置于所述射极层的射极金属层。
所述介电层覆盖所述射极层，并定义出开口，所述基极金属层经由所述开口与所述基极层相接触，并延伸覆盖至少部分与所述开口相邻的所述介电层。
较佳地，所述异质接面双极性晶体管，其中，所述基极金属层的高度不小于
较佳地，所述异质接面双极性晶体管，还包含隔离层，所述隔离层覆盖所述半导体单元、所述电极单元，及所述介电层表面，并定义出分别令所述集极金属层、所述基极金属层，及所述射极金属层露出的通孔。
较佳地，所述异质接面双极性晶体管，其中，所述介电层会延伸覆盖至相邻的所述射极金属层的部分表面。
本实用新型的有益效果在于，通过将所述介电层设置在基极层并定义出所述开口，使后续沉积所述基极金属层时产生的金属毛边不会造成基极金属层的宽度增加的问题，且能避免金属毛边接触所述射极层，在提高所述基极金属层的高度时，同时精确控制基极金属层的宽度，以有效提高异质接面双极性晶体管的输出频率。
附图说明
本实用新型的其他的特征及功效，将于参照图式的实施方式中清楚地呈现，其中：
图1是部分剖面侧视示意图，说明现有异质接面双极性晶体管的结构；
图2是部分剖面侧视示意图，说明现有异质接面双极性晶体管的基极金属层的结构；
图3是部分剖面侧视示意图，说明本实用新型异质接面双极性晶体管的实施例；
图4是文字流程图，说明本实用新型异质接面双极性晶体管的实施例的制作方法；及
图5是流程示意图，辅助说明本实用新型异质接面双极性晶体管的实施例的制作方法。
具体实施方式
在本实用新型被详细描述之前，应当注意在以下的说明内容中，类似的组件是以相同的编号来表示。此外，图式中仅为表示组件及膜层间的空间关系，并非各组件及膜层的实质厚度、尺寸或相对比例关系。
参阅图3及图5，本实用新型异质接面双极性晶体管的实施例，包含基板2、半导体单元3、电极单元4、介电层5，及隔离层6。
所述基板2由半绝缘的半导体材料构成。
所述半导体单元3由III-V族半导体材料构成，设置在所述基板2上，具有自所述基板2表面21依序向上形成的集极层31、基极层32，及射极层33。
所述集极层31、所述基极层32，及所述射极层33是由III-V族的半导体材料构成，所述III-V族材料可为氮化镓(GaN)、砷化镓(GaAs)、砷化铟镓(InGaAs)、磷化铟(InP)，或磷化铟镓(InGaP)等，且所述集极层31、所述基极层32，及所述射极层33可以分别是单膜层或多膜层的堆栈结构。由于所述集极层31、所述基极层32，及所述射极层33的相关材料及膜层结构为本技术领域所知悉，因此不再多加说明。
所述电极单元4具有设置在所述集极层31上的集极金属层41、设置在所述基极层32上的基极金属层42，及设置在所述射极层33上的射极金属层43。所述集极金属层41、所述基极金属层42及所述射极金属层43由导电材料构成，且可为单层或多层结构，所述导电材料可选自导电性佳的金属或合金金属。图3中所述集极金属层41、所述基极金属层42及所述射极金属层43是以单层结构表示，然实际实施时并不以此为限。
此外，于一些实施例中，所述基极金属层42的高度H不小于
所述介电层5覆盖所述射极层33并延伸覆盖至相邻的所述射极金属层43的部分表面，且定义出让所述基极层32的表面露出并具有宽度CD的开口50，所述基极金属层42经由所述开口50与所述基极层32相接触，并延伸覆盖至少部分与所述开口50相邻的所述介电层5。
所述介电层5的目的是用于定义出所述基极金属层42与所述基极层32的接触面积，因此，只要是绝缘材料即可，并无特别限制。于一些实施例中，所述介电层5的材料可选自氮化物、氧化物、氮氧化物，或前述其中一组合，例如所述介电层5材料可选自氧化硅(SiOx)，氮化硅(SiNx)，氮氧硅化合物(SiNxOy)。在本实施例中，所述介电层5的材料是以氮化硅(Si3N4)为例做说明。
所述隔离层6覆盖所述半导体单元3、所述电极单元4，及所述介电层5表面，并定义出分别令所述集极金属层41、所述基极金属层42，及所述射极金属层43露出的通孔60。适用于构成所述隔离层6的材料可选用例如氮化硅、氧化硅，或聚酰亚胺等绝缘材料。
也就是说，本实用新型的所述异质接面双极性晶体管，通过在所述射极层33先沉积形成所述介电层5，并利用所述介电层5先定义出所述开口50，因此，可精准控制所述基极金属层42与所述基极层32的接触宽度CD；此外，当后续利用光阻定义并沉积的所述基极金属层42时，则可因为有所述介电层5的隔离，所以于增加所述基极金属层42高度H的同时，也不会因为沉积过程产生的金属毛边40而增加所述基极金属层42与所述基极层32的接触面积，从而可同时达到减少所述基极金属层42的电阻Rb值与降低所述基极层32与跟集极层31接面电容Cbc值的目的，而可有效提高制得的异质接面双极性晶体管的最大输出频率fmax。
较佳地，在本实施例中，所述基极金属层42的高度不小于更佳地，所述开口50的宽度CD不大于0.8μm。
于一些实施例，所述介电层5会形成在所述基极层32上并延伸覆盖至相邻的所述射极金属层43的部分表面。因此，于沉积形成所述基极金属层42时，可因为有所述介电层5将所述基极金属层42与相邻的所述射极金属层43与隔离，因此，可进一步预防沉积形成所述基极金属层42的过程所产生的金属毛边40与所述射极层33接触而短路的问题。
配合参阅图4与图5，兹将前述异质接面双极性晶体管的实施例的制作方法说明如下：
首先，提供具有所述半导体单元3的半导体半成品30。所述半导体半成品30是利用磊晶成长方式于所述基板2上依序成长所述集极层31、所述基极层32，及所述射极层33而得。其中，所述半导体层磊晶成长方式能使用例如金属有机化学气相沉积法(MOCVD)、分子束磊晶(MBE)，或液相磊晶(LPE)等，由于所述制程方法的相关原料及制程参数为本技术领域已知，因此，不再多加赘述。
接着，于所述射极层33上形成射极金属层43。
所述步骤是利用微影制程自所述半导体单元3的部分顶面沉积导电材料，而得到所述射极金属层43。
然后，于所述射极层33上形成介电层5。
详细地说，所述步骤是利用微影蚀刻制程自所述半导体单元3的部分顶面向下蚀刻以形成令所述基极层32露出的开口50。接着，于所述射极层33中除开口50外其余部分表面沉积覆盖介电层5，令所述基极层32的表面可自开口50对外裸露。较佳地，所述介电层5延伸覆盖至相邻的所述射极金属层43的表面。
随后，于所述介电层5上形成与所述基极层32接触的基极金属层42。
详细的说，所述步骤是利用光阻PR于对应所述介电层5的开口50位置定义后续用于形成具有预定高度及宽度的所述基极金属层42的开口区域，再将导电材料经由所述光阻PR的开口区域沉积形成具有预定高度的所述基极金属层42。其中，所述基极金属层42会覆盖至少部分与所述开口50相邻的所述介电层5，并经由所述开口50与所述基极层32相接触。之后，将所述光阻PR移除。
接着，于所述集极层31上沉积形成所述集极金属层41。
所述步骤是自所述半导体单元3的部分顶面向下蚀刻至令所述集极层31露出，再于所述集极层31上沉积导电材料，而制得所述集极金属层41。
最后，形成具有通孔60的所述隔离层6。
详细的说，所述步骤是于所述半导体单元3、所述集极金属层41、所述基极金属层42、所述射极金属层43，及所述介电层5表面沉积所述隔离层6，再利用微影蚀刻制程自所述隔离层6向下形成分别令所述集极金属层41、所述基极金属层42，及所述射极金属层43露出并可用以对外电连接的通孔60，即可制作完成如图3所示的所述异质接面双极性晶体管。
综上所述，本实用新型异质接面双极性晶体管利用在所述基极层32上形成具有预定宽度CD的开口50的所述介电层5，因此，后续经由沉积形成较高高度的所述基极金属层42时，因有所述介电层5的隔离，而可避免于沉积过程产生的所述金属毛边40与所述基极层32接触，而影响所述基极金属层42与所述基极层32的接触面积，而可达到同时减少所述基极金属层42的电阻Rb值与降低所述基极层32与跟集极层31接面的电容Cbc值的目的，进而有效提高制得的异质接面双极性晶体管的最大输出频率fmax，确实可达成本实用新型目的。
以上所述者，仅为本实用新型的实施例而已，当不能以此限定本实用新型实施的范围，即凡依本实用新型权利要求书及说明书内容所作的简单的等效变化与修饰，皆仍属本实用新型的范围。
Claims (4)
1.一种异质接面双极性晶体管，其特征在于：包含：
基板；
半导体单元，形成于所述基板上，具有自所述基板表面向上形成的集极层、基极层，及射极层；
电极单元，具有设置于所述集极层的集极金属层、设置于所述基极层的基极金属层，及设置于所述射极层的射极金属层；及
介电层，覆盖所述射极层，并定义出开口，所述基极金属层经由所述开口与所述基极层相接触，并延伸覆盖至少部分与所述开口相邻的所述介电层。
2.根据权利要求1所述的异质接面双极性晶体管，其特征在于：所述基极金属层的高度不小于
3.根据权利要求1所述的异质接面双极性晶体管，其特征在于：还包含隔离层，所述隔离层覆盖所述半导体单元、所述电极单元，及所述介电层表面，并定义出分别令所述集极金属层、所述基极金属层，及所述射极金属层露出的通孔。
4.根据权利要求1所述的异质接面双极性晶体管，其特征在于：所述介电层延伸覆盖至相邻的所述射极金属层的部分表面。
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| US5633179A (en) * | 1989-12-01 | 1997-05-27 | Kamins; Theodore I. | Method of forming silicon/silicon-germanium heterojunction bipolar transistor |
| US5846867A (en) * | 1995-12-20 | 1998-12-08 | Sony Corporation | Method of producing Si-Ge base heterojunction bipolar device |
| JP2003249503A (ja) * | 2002-02-26 | 2003-09-05 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| US10490639B2 (en) * | 2018-03-27 | 2019-11-26 | Qualcomm Incorporated | Low collector contact resistance heterojunction bipolar transistors |
| US10749017B1 (en) * | 2019-02-12 | 2020-08-18 | Qualcomm Incorporated | Heterojunction bipolar transistors with field plates |
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| US20200227540A1 (en) | 2020-07-16 |
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