TWI681511B - 整合場效電晶體與異質接面雙極電晶體的結構及其形成方法 - Google Patents

整合場效電晶體與異質接面雙極電晶體的結構及其形成方法 Download PDF

Info

Publication number
TWI681511B
TWI681511B TW106135759A TW106135759A TWI681511B TW I681511 B TWI681511 B TW I681511B TW 106135759 A TW106135759 A TW 106135759A TW 106135759 A TW106135759 A TW 106135759A TW I681511 B TWI681511 B TW I681511B
Authority
TW
Taiwan
Prior art keywords
layer
hbt
contact layer
heterojunction bipolar
field effect
Prior art date
Application number
TW106135759A
Other languages
English (en)
Other versions
TW201824459A (zh
Inventor
吳展興
Original Assignee
吳展興
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 吳展興 filed Critical 吳展興
Publication of TW201824459A publication Critical patent/TW201824459A/zh
Application granted granted Critical
Publication of TWI681511B publication Critical patent/TWI681511B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

本發明揭露一種用於整合場效電晶體與異質接面雙極電晶體的結構，包含一基板；一第一磊晶結構位於該基板的上方，該第一磊晶結構具有一異質接面雙極電晶體(HBT)的一部分；及一第二磊晶結構位於該第一磊晶結構的上方，該第二磊晶結構具有一場效電晶體(FET)的一部分。

Description

整合場效電晶體與異質接面雙極電晶體的結構及其形成方法
本發明係關於一種可將場效電晶體與異質接面雙極電晶體整合的磊晶結構，特別是垂直整合場效電晶體與異質接面雙極電晶體的結構。
發展異質接面雙極電晶體(HBT)已成很多應用中相當重要技術，尤其是用於無線通訊系統的功率放大器。假晶性高電子遷移率電晶體(pHEMT Pseudomorphic high electron mobility transistor)是形成在GaAs上的一種場效電晶體(FET)。為了提高HBT用於功率放大器的效能，已有將HBT與pHEMT組合形成開關與電路控制的整合元件，稱為雙極高電子遷移率電晶體(BiHEMT)。
典型的BiHEMT元件包括生長在pHEMT層頂上的HBT層。為了露出pHEMT層，必需蝕刻移除所有的HBT層。然而，由於pHEMT層表面和HBT層表面之間大的高度差，導致製程的難度大增。舉例而言，於高頻應用時pHEMT層的閘極長度可能需要低到0.15μm，而HBT層的厚度卻可能需要達到2.5μm。如此大的深寬比造成製程困難，影響平坦度並容易產生鄰近效應，進而迫使pHEMT元件不能擺在靠近HBT元件的地方，由此侷限電路設計的佈局與自由度，同時晶片的尺寸也增加導致成本增加。因此需要一種創新的BiHEMT以解決上述問題。
為解決上述之問題，本發明設想將關鍵尺寸(critical dimension)較小較難製作的FET，譬如pHEMT，置放在HBT上。HBT的關鍵尺寸最小約在1μm至3μm，比pHEMT約0.15μm至0.5μm的尺寸大很多。如果磊晶成長過程可以先成長HBT然後再作FET，如此使FET垂直整合在HBT上方，將有製程方便且效能最佳化的優點。當磊晶結構中FET(pHEMT)置於HBT上，在製造FET(pHEMT)過程中對關鍵尺寸(0.15μm至0.5μm)的控制就相當容易，同時因為FET(pHEMT)結構薄(厚度在0.5μm至1μm)，如此對HBT 1μm至3μm尺寸的製造與控制也很容易。也因為FET(pHEMT)的磊晶厚度比HBT的厚度(2μm至2.5μm)薄，在製造的過程中，本發明的FET(pHEMT)在HBT上面其表面的平坦度的結構會比一般的HBT在FET(pHEMT)上面的結構要好很多。如此也使製程容易、光阻材料使用變少、良率較好，製造成本也降低。
習知結構中FET位在下層，HBT位在上層，要將HBT改到下層而FET改到上層是難以達成的。習知HBT磊晶結構中最上層的射極接觸層為磊晶InGaAs，其與以GaAs為基底的各種磊晶層如GaAs,AlGaAs及InGaP晶格不匹配。所以，直接將以GaAs為基底的FET結構作在HBT的射極接觸層InGaAs的上方，將產生嚴重的晶格不匹配，導致界面差排，進而造成界面缺陷。(註：其磊晶InGaAs一般為高銦摩爾分數如n+In0.5Ga0.5As，其 主要是為了降低HBT射極的歐姆接觸電阻至10-8Ω-cm2的範圍。如果使用n+GaAs為接觸層則接觸電阻只能在10-6Ω-cm2的範圍，這將大大降低HBT的功率放大效率。
況且為了達到高效能低電阻，習知HBT結構通常含有晶格不匹配的漸變InGaAs層，此層非單晶結構而是多晶層。如果直接在這多晶層上長HEMT(或p-HEMT)則電性效能及結晶皆會降低，其容易產生電子深陷(deep trap)，碎差排(shredded dislocation)而有漏電電流且不穩定，無法達到開關及電路控制之元件規格的要求。
本發明於一方面係設想將FET垂直整合在HBT上方，以便於製程上不管是製造FET及HBT的關鍵尺寸或是擺設位置等困難度都會大大降低。於另一方面本發明進一步設想到使HBT的頂部接觸層與FET的基底兩者使用的材料晶格匹配。本發明更包含其他各方面，更進一步優選材料，在HBT元件的部份可以達到低串聯和低接觸射極電阻，同時達到低漏電流的pHEMT開關元件。並且本發明由於pHEMT結構擺在上面，所以可以使用超低接觸電阻(10-8Ω-cm2)的晶格不匹配的漸變的n+In0.5Ga0.5As的歐姆電阻層。如此可以降低開關的串聯電阻及Ron，進而改進開關(switch)的效能。如此使HBT成為高效能的功率放大器且FET(HEMT或pHEMT)也能符合開關及電路控制之元件規格的要求。
本發明尚包含其他實施例以解決其他問題並合併上述之實施例詳細揭露於以下實施方式中。
10‧‧‧結構
100‧‧‧基板
110‧‧‧第一磊晶結構
120‧‧‧第二磊晶結構
20‧‧‧結構
210‧‧‧接觸層
211‧‧‧蝕刻中止層
220‧‧‧已掺雜隔離層
30‧‧‧結構
321‧‧‧未掺雜層
40‧‧‧結構
410‧‧‧接觸層
420‧‧‧已掺雜隔離層
421‧‧‧未掺雜層
422‧‧‧未掺雜緩衝層
50‧‧‧結構
510‧‧‧接觸層
511‧‧‧蝕刻中止層
520‧‧‧已掺雜隔離層
521‧‧‧未掺雜層
522‧‧‧未掺雜緩衝層
圖1a及圖1b係依據本發明實施例顯示FET與HBT整合結構示意圖。
圖2係依據本發明其他實施例顯示FET與HBT整合結構示意圖。
圖3係依據本發明再其他實施例顯示FET與HBT整合結構示意圖。
圖4係依據本發明更再其它實施例顯示FET與HBT整合結構示意圖。
圖5係依據本發明又更再其他實施例顯示具有金屬接觸圖案之FET與HBT整合示意圖。
以下將參考所附圖式示範本發明之較佳實施例。所附圖式中相似元件係採用相同的元件符號。應注意為清楚呈現本發明，所附圖式中之各元件並非按照實物之比例繪製，而且為避免模糊本發明之內容，以下說明亦省略習知之原理、零組件、相關材料、及其相關處理技術。
如圖1a及圖1b所示，依據某些實施例，本發明提供一種用於整合場效電晶體與異質接面雙極電晶體的結構10，包含一基板100；一第一磊晶結構110位於基板100的上方，第一磊晶結構110具有一異質接面雙極電晶體(HBT)的一部分；及一第二磊晶結構120位於第一磊晶結構110的上方，第二磊晶結構120具有一場效電晶體(FET)的一部分。FET可以由各種磊 晶層組成，其包含pHEMT、HEMT、MESFET、MOSFET，或其他合適的結構。異質接面雙極電晶體HBT與場效電晶體FET組合可形成具有開關與電路控制功能的功率放大器整合元件，譬如雙極高電子遷移率電晶體(BiHEMT)。在結構10中，基板100通常為砷化鎵基板，但也可以是其他合適在上面製作HBT及FET的任何其他材料。形成在基板100上的第一磊晶結構110及第二磊晶結構120可用習知的技術形成，包含化學氣相沉積(chemical vapor deposition,CVD)，有機金屬化學氣相沉積CVD(MOCVD),或分子束磊晶(MBE)等等。參考圖1a及圖1b，結構10的製法可為先在基板100上形成含HBT所需各層的第一磊晶結構110；然後在第一磊晶結構110上形成含FET所需各層的第二磊晶結構120；接著蝕刻移除一部分的第二磊晶結構120曝露出底下的第一磊晶結構110。可接著透過習知微影技術，在結構10的基礎上完成HBT所需的圖案線路與金屬接觸等等。依據結構10，HBT元件的製程相對簡單，因為上層之FET所要求的厚度不高，所以第二磊晶結構120的表面與曝露出的第一磊晶結構110的表面差距h相對低，深寬比大為降低。完成HBT元件所需結構後以適當的遮罩將HBT元件覆蓋住，接著在第二磊晶結構120上，同樣再透過習知微影技術，完成FET所需的圖案線路與金屬接觸等等。相較於習知HBT在FET上層，本發明之結構10揭示FET在HBT上層，提供較低的製程深寬比使FET可以靠近HBT，使IC設計自由度增加且晶片尺寸也可縮小。由此可知使FET垂直整合在HBT上方，將有製程方便且效能最佳化的優點。也就是在製程方面更有彈性，可先製造pHEMT再造HBT，也可先製造HBT再造pHEMT，也可斟酌製程能力來同時製造pHEMT及HBT。圖5為本發明具有金屬接觸圖案之FET與HBT 垂直整合結構50示意圖。參考圖5，結構50包含基板100，第一磊晶結構110、第二磊晶結構120。第二磊晶結構120有一部份經圖案化及金屬沉積形成有源極S、閘極G及汲極D的FET結構，堆疊在第一磊晶結構110上方。第二磊晶結構120有另一部份被移除，露出第一磊晶結構110的一部分。此部分之第一磊晶結構110經圖案化及金屬沉積形成有基極B、集極C、及射極E的HBT結構。
參考圖2，依據某些其他實施例，本發明提供相似於上述之第二磊晶結構120位於第一磊晶結構110的上方的結構20，其第一磊晶結構110包含HBT的一接觸層210位於HBT頂部，第二磊晶結構120包含最接近接觸層210的一已掺雜隔離層220，用以電性隔離FET與HBT。接觸層210與已掺雜隔離層220之間可視需要含有其他層，例如蝕刻中止層211，或未掺雜緩衝層等。為使結構更加穩固，本發明進一步設想使接觸層210與已掺雜隔離層220晶格匹配，較佳的晶格匹配狀況為該接觸層210的晶格常數與該已掺雜隔離層220的晶格常數的差異相較於該接觸層210的晶格常數係小於等於0.15%。可依據此標準選擇合適的材料，譬如接觸層可為Ge、In0.5Ga0.5P、AlxGa1-xAs，x=0~1等但不以此為限；而已掺雜隔離層可為Ge、In0.5Ga0.5P、AlxGa1-xAs，x=0~1等，但不以此為限。接觸層210與已掺雜隔離層220之間可有其他功能的各層，其較佳也應與已掺雜隔離層220及接觸層210晶格匹配，譬如圖2蝕刻中止層211也可為Ge、In0.5Ga0.5P、AlxGa1-xAs，x=0~1，但不以此為限。
可同樣參考圖2，除了改善晶格差排以強壯結構外，本發明 更進一步要達到優良電性的要求，因此進一步研究各種材料的能隙、蕭特基能位障ΦB、及掺雜濃度。依據某些其他實施例提供相似於圖2之第二磊晶結構120位於第一磊晶結構110的上方的結構20，本發明發現接觸層210能隙小於等於0.7eV者將可有較佳的低歐姆電阻。又依據某些其他實施例提供相似於圖2之第二磊晶結構120位於第一磊晶結構110的上方的結構20，本發明更進一步發現接觸層具有蕭特基能位障ΦB小於等於0.65eV者，可使隧道效應容易彰顯。可依據上述在晶格匹配的各種材料中選擇更合適的材料製作接觸層。舉例而言，在晶格匹配的各種實施例中，以Ge作接觸層是比GaAs更佳的選擇。GaAs作HBT的接觸層雖是晶格匹配的，但GaAs的能帶大於0.7eV，蕭特基能位障ΦB也大於0.65eV，因此容易有串聯電阻及接觸電阻過大的缺點。
有關上述晶格常數、能隙及蕭特基能位障Φb的定義與測量可參見現有技術，譬如參見S.M.Sze的"Physics of Semiconductor Devices"第二版，其中第291頁表三"Measured Schottky Barrier Heights"；第848頁附件F"Lattice Constants"；第850頁附件H"Properties of Ge,Si,GaAs at 300K。
同樣參考圖2，依據某些其他實施例提供相似於圖2之第二磊晶結構120位於第一磊晶結構110的上方的結構20，本發明再進一步發現接觸層210其掺雜濃度(本文中掺雜濃度單位皆為cm-3)可在1019或1020的層級，舉例而言可在3 x 1019至2 x 1020範圍、較佳在5 x 1019至2 x 1020範圍、更佳在1 x 1020至2 x 1020範圍，可使其串聯及接觸電阻維持很小。同時，適當地增加接觸層210的厚度，可防止後續製作在接觸層210上的射 極歐姆接觸的金屬擴散到底下射極層區域中。除此以外，同樣參考圖2，依據某些其他實施例，本發明為使上層的FET與下層HBT有更好的電性隔絕，進一步發現使接觸層210的電性與已掺雜隔離層220的電性相反，且更優選為接觸層210與已掺雜隔離層220的掺雜質量(掺雜個數#/cm2)盡可能均等將可有效避免寄生電容。實務上可控制使接觸層210的掺雜質量與已掺雜隔離層220的掺雜質量的差異在兩者平均值的10%以內。此等實施例中，以NPN型為例，在以n+Ge為接觸層狀況下可以p-GaAs或p+GaAs為已掺雜隔離層，但不以此為限。在以n+Ge為接觸層狀況下，掺雜濃度達到1020 cm -3 是可以達成的，可參見：Slawomir Prucnal等人之著作“Ultra-doped n-type germanium thin films for sensing in the mid-infrared”,2016年6月10日刊登於Scientific Reports，其中陳述使用δ-doped分子束磊晶法(MBE)成長其n+Ge可達1020cm-3，如此接觸電阻可在10-8Ω-cm2之低範圍。同時可參考書本“Physics and Chemistry of III-V Compound Semiconductor Interfaces(1985),Editor：Carl W.Wilmsen,Chapter“Schottky Diodes and Ohmic Contacts for the III-V Semiconductors,page 135，裡面討論n+Ge/n+GaAs可達到10-8Ω-cm2範圍的接觸電阻。
於某些實施例，在以n+Ge為接觸層狀況下，掺雜濃度達到1020 cm -3 也可以採用MOCVD(有機金屬化學氣相沉積Metal-organic Chemical Vapor Deposition)的設備以原子層磊晶(Atomic Layer Epitaxy,ALE)方法來達成。
於某些其他實施例，接觸層210與已掺雜隔離層220之間有蝕 刻中止層211時，蝕刻中止層211使用與接觸層210及已掺雜隔離層220皆晶格匹配的材料，但蝕刻中止層211不掺雜。
參考圖3及表一及表二，依據某些其他實施例提供第二磊晶結構120位於第一磊晶結構110的上方的結構30，其中第一磊晶結構110包含HBT的接觸層210位於HBT頂部，第二磊晶結構120包含最接近接觸層210的已掺雜隔離層220。第二磊晶結構120除有已掺雜隔離層220外、更包含一未掺雜層321位在FET的底部之已掺雜隔離層220的上方。本發明發現未掺雜層321可有效防止FET產生漏電流。未掺雜層可為單層或多層，可包含超晶格層。未掺雜層整體的厚度較佳在5,000埃至10,000埃。舉例而言，以n+Ge作為接觸層210時，未掺雜層321可為未掺雜的GaAs、未掺雜的AlGaAs、未掺雜的GaAs及未掺雜的AlGaAs交替形成的超晶格層、或上述之各種組合。
參考圖4及表二，依據某些其他實施例提供第二磊晶結構120位於第一磊晶結構110的上方的結構40，其中第一磊晶結構110包含HBT的接觸層410位於HBT頂部，第二磊晶結構120包含最接近接觸層410的已掺雜隔離層420。接觸層410與已掺雜隔離層420電性相反。第二磊晶結構120除有已掺雜隔離層420外、更包含一未掺雜緩衝層422位在該接觸層410與已掺雜隔離層420之間，未掺雜緩衝層422有別於一般的蝕刻中止層211，在此實施例，未掺雜緩衝層422位於蝕刻中止層211上方。本發明發現未掺雜緩衝層422可有效防止FET產生漏電流。舉例而言，以n+Ge作為接觸層410且以P+GaAs為已掺雜隔離層時，未掺雜緩衝層422可為未掺雜AlGaAs，其厚度可在1,000埃~2,000埃。
可透過習知微影技術，在圖2或圖3的結構20/30的基礎上完成HBT/FET所需的圖案線路與金屬接觸等等，如圖5結構50所示。結構50包含有如上述之接觸層510、已掺雜隔離層520、蝕刻中止層511及未掺雜層521未掺雜緩衝層522。
表一為本發明整合場效電晶體與異質接面雙極電晶體的結構之第一較佳實施例其各層的詳細說明。
Figure 106135759-A0101-12-0010-1
如表一所示，接觸層(n+Ge)及射極傳輸層(n+-GaAs,n-GaAs)的厚度可適當地加厚，可防止後續製作在接觸層上的射極歐姆接觸金屬擴散到底下寬帶射極層(n-In0.5Ga0.5P)中。
表二為本發明整合場效電晶體與異質接面雙極電晶體的結構之第二較佳實施例其各層的詳細說明。
Figure 106135759-A0101-12-0011-9
如表二所示，接觸層(n+Ge,600-800Å)及射極傳輸層(n+-GaAs,1000-1200Å)的厚度已適當地加厚，可防止後續製作在接觸層上的射極歐姆接觸金屬擴散到底下寬帶射極層(n-In0.5Ga0.5P)。
本發明所提之方法也適用在其他需要垂直整合兩種元件的結構。整合的結構裡上下元件都需要低的歐姆接觸電阻。此整合的結構中所含之元件可含蓋如HBT,FET(HEMT,pHEMT),LED，雷射二極體(Laser Diode)，太陽電池(Solar Cell),PIN二極體等等。
以上所述僅為本發明之較佳實施例而已。本發明尚包含很多其他實施例係以如本發明之申請專利範圍所述。凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。
10‧‧‧結構
100‧‧‧基板
110‧‧‧第一磊晶結構
120‧‧‧第二磊晶結構

Claims (11)

  1. 一種用於整合場效電晶體與異質接面雙極電晶體的結構，包含：一基板；一第一磊晶結構位於該基板的上方，該第一磊晶結構具有一異質接面雙極電晶體(HBT)的一部分；及一第二磊晶結構位於該第一磊晶結構的上方，該第二磊晶結構具有一場效電晶體(FET)的一部分，其中該第一磊晶結構包含該HBT的一接觸層位於該HBT頂部，該接觸層為n+Ge，該第二磊晶結構包含最接近該接觸層的一已掺雜隔離層用以電性隔離該FET與該HBT。
  2. 如請求項1所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該接觸層的晶格常數與該已掺雜隔離層的晶格常數的差異相較於該接觸層的晶格常數係小於等於0.15%。
  3. 如請求項1及2中任一項所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該接觸層具有能隙小於等於0.7eV。
  4. 如請求項1及2中任一項所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該接觸層具有蕭特基能位障ΦB小於等於0.65eV。
  5. 如請求項1及2中任一項所述之整合場效電晶體與異質接面雙極電晶體的 結構，其中該接觸層之掺雜濃度在3 x 1019至2 x 1020cm-3範圍中。
  6. 如請求項1所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該已掺雜隔離層為砷化鎵(GaAs)。
  7. 如請求項1及2中任一項所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該接觸層的電性與該已掺雜隔離層的電性相反。
  8. 如請求項7所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該接觸層的掺雜質量與該已掺雜隔離層的掺雜質量的差異在兩者平均值的10%以內。
  9. 如請求項7所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該第二磊晶結構包含一未掺雜層位在該FET的底部且於該已掺雜隔離層的上方，該未掺雜層為單層或多層，該未掺雜層具有厚度在5,000埃至10,000埃。
  10. 如請求項7所述之整合場效電晶體與異質接面雙極電晶體的結構，其中該第二磊晶結構包含一未掺雜緩衝層位在該已掺雜隔離層與該接觸層之間，該未掺雜緩衝層具有厚度在1,000埃至2,000埃。
  11. 一種形成如請求項1至10中任一項之整合場效電晶體與異質接面雙極電 晶體的結構的方法，其中該接觸層係藉由有機金屬化學氣相沉積(MOCVD)的設備以原子層磊晶(ALE)方法來形成。
TW106135759A 2016-10-18 2017-10-18 整合場效電晶體與異質接面雙極電晶體的結構及其形成方法 TWI681511B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
PCT/CN2016/102344 WO2018072075A1 (zh) 2016-10-18 2016-10-18 整合场效晶体管与异质接面双极晶体管的结构
WOPCT/CN2016/102344 2016-10-18
??PCT/CN2016/102344 2016-10-18

Publications (2)

Publication Number Publication Date
TW201824459A TW201824459A (zh) 2018-07-01
TWI681511B true TWI681511B (zh) 2020-01-01

Family

ID=62019107

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106135759A TWI681511B (zh) 2016-10-18 2017-10-18 整合場效電晶體與異質接面雙極電晶體的結構及其形成方法

Country Status (4)

Country Link
US (1) US20200043913A1 (zh)
CN (1) CN109923664A (zh)
TW (1) TWI681511B (zh)
WO (1) WO2018072075A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI747565B (zh) * 2020-10-22 2021-11-21 華特 吳 異質接面雙載子電晶體
CN113130478A (zh) * 2021-04-13 2021-07-16 厦门市三安集成电路有限公司 一种射频芯片及制备方法
US20230402549A1 (en) * 2022-06-09 2023-12-14 Macom Technology Solutions Holdings, Inc. Monolithic pin and schottky diode integrated circuits

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228784A (ja) * 2005-02-15 2006-08-31 Hitachi Cable Ltd 化合物半導体エピタキシャルウェハ
TWI315100B (en) * 2005-03-03 2009-09-21 Cree Inc High electron mobility transistor
TW201225287A (en) * 2010-09-17 2012-06-16 Kopin Corp Method and layer structure for preventing intermixing of semiconductor layers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009081284A (ja) * 2007-09-26 2009-04-16 Hitachi Cable Ltd トランジスタ素子
US20120293813A1 (en) * 2010-11-22 2012-11-22 Kopin Corporation Methods For Monitoring Growth Of Semiconductor Layers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006228784A (ja) * 2005-02-15 2006-08-31 Hitachi Cable Ltd 化合物半導体エピタキシャルウェハ
TWI315100B (en) * 2005-03-03 2009-09-21 Cree Inc High electron mobility transistor
TW201225287A (en) * 2010-09-17 2012-06-16 Kopin Corp Method and layer structure for preventing intermixing of semiconductor layers

Also Published As

Publication number Publication date
US20200043913A1 (en) 2020-02-06
TW201824459A (zh) 2018-07-01
WO2018072075A1 (zh) 2018-04-26
CN109923664A (zh) 2019-06-21

Similar Documents

Publication Publication Date Title
US11239348B2 (en) Wafer bonded GaN monolithic integrated circuits and methods of manufacture of wafer bonded GaN monolithic integrated circuits
Xing et al. Gallium nitride based transistors
US7550784B2 (en) Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses
US8716756B2 (en) Semiconductor device
US20120326211A1 (en) Bipolar high electron mobility transistor and methods of forming same
US5283448A (en) MESFET with indium gallium arsenide etch stop
US9269784B2 (en) Gallium arsenide based device having a narrow band-gap semiconductor contact layer
TWI681511B (zh) 整合場效電晶體與異質接面雙極電晶體的結構及其形成方法
US7915640B2 (en) Heterojunction semiconductor device and method of manufacturing
US20240088284A1 (en) High electron mobility transistor (hemt) with a back barrier layer
JP6242678B2 (ja) 窒化物半導体素子及びその製造方法
US7518165B2 (en) Epitaxial nucleation and buffer sequence for via-compatible InAs/AlGaSb HEMTs
TWI222750B (en) Voltage adjustable multi-stage extrinsic transconductance amplification HEMT
US5381027A (en) Semiconductor device having a heterojunction and a two dimensional gas as an active layer
JP2005005646A (ja) 半導体装置
US20190006173A1 (en) Epitaxies of a Chemical Compound Semiconductor
US20230290834A1 (en) ENHANCEMENT-MODE GaN HFET
US5258631A (en) Semiconductor device having a two-dimensional electron gas as an active layer
JP2002009253A (ja) 半導体装置およびその製造方法
JPH11251328A (ja) 化合物半導体装置
US20240063292A1 (en) Semiconductor structures and fabrication using sublimation
CN209785942U (zh) 异质接面双极性晶体管
CN116936645B (zh) 一种p沟道肖特基势垒二极管及其制作方法
Tang et al. Hetero-epitaxy of III-V Compounds lattice-matched to InP by MOCVD for Device Applications
US20240363344A1 (en) Epitaxies of a Chemical Compound Semiconductor

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees