CN207676903U - 一种双芯片横向串联型高耐压表面贴装的二极管封装结构 - Google Patents

一种双芯片横向串联型高耐压表面贴装的二极管封装结构 Download PDF

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CN207676903U
CN207676903U CN201720978091.5U CN201720978091U CN207676903U CN 207676903 U CN207676903 U CN 207676903U CN 201720978091 U CN201720978091 U CN 201720978091U CN 207676903 U CN207676903 U CN 207676903U
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李成军
王成森
薛治祥
姚霜霜
张松
倪亮亮
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Agile Semiconductor Ltd
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Agile Semiconductor Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型公开了一种双芯片横向串联型高耐压表面贴装的二极管封装结构和制造方法,包括内引线、由外引线A、外引线B以及两个凸台组成的引线框架,外引线A、外引线B分别与载片台连为一体,两个载片台上均设有凸台,内引线底面设有两个凸台,两个载片台上的两个凸台与内引线底面的两个凸台之间设置第一芯片与第二芯片,本实用新型提高了二极管的电压值及TVS等器件的功率,芯片厚度变化无需修改内引线,可容芯片的厚度尺寸大,本实用新型为双芯片横向串联二极管,作为整流器件若其中一个芯片被击穿,另一个芯片仍可继续工作。

Description

一种双芯片横向串联型高耐压表面贴装的二极管封装结构
技术领域
本实用新型涉及一种半导体器件技术领域,具体是一种双芯片横向串联型高耐压表面贴装的二极管封装结构。
背景技术
随着电子应用技术的不断发展,电子电路的集成度越来越高,集成电路板上的空间越来越有限,二极管所需承受的反向工作电压越来越高。但二极管内部PN结所能承受的电压有限,因此需要采用两只或以上二极管串联分压的模式来实现。在此基础上,若将两个或以上二极管通过内串联的方式集成到一个产品里,则可以有效的减少空间。
目前市场销售的大部分二极管为单芯片二极管,此类二极管为单芯片二极管,体积小,结构简单,但所能达到的电压值较小。
实用新型内容
本实用新型的目的在于提供一种双芯片横向串联型高耐压表面贴装的二极管封装结构。
本实用新型采用的技术方案是:
一种双芯片横向串联型高耐压表面贴装的二极管封装结构,其特征在于:包括内引线、由外引线A、外引线B以及两个凸台组成的引线框架,所述外引线A、外引线B分别与载片台连为一体,所述两个载片台上均设有凸台,所述内引线底面设有两个凸台,所述两个载片台上的两个凸台与内引线底面的两个凸台之间设置第一芯片与第二芯片。
所述第一芯片的阳极面与内引线底面左侧的凸台焊接在一起,其阴极面与外引线A的载片台顶面的凸台焊接在一起。
所述第二芯片的阴极面与内引线底面右侧的凸台焊接在一起,其阳极面与外引线B的载片台顶面的凸台焊接在一起。
所述第一芯片和第二芯片是两个具有相同功能和尺寸的TVS、半导体放电管或普通整流二极管芯片。
本实用新型的优点:用两个相同额定电压值的TVS等二极体芯片,采用串联方式的封装结构和制造方法,提高了二极管的电压值以及TVS等器件的功率;内引线为底面设有两个共面凸台的电极片分别与两芯片的阴极和阳极焊接,芯片厚度变化无需修改内引线;结构为双芯片横向串联,相同封装体厚度可容芯片的厚度尺寸大;本实用新型为双芯片横向串联二极管,作为整流器件若其中一个芯片被击穿,另一个芯片仍可继续工作。
附图说明
下面结合附图和具体实施方式对本实用新型作进一步详细叙述。
图1为本实用新型的结构示意图;
图2为本实用新型引线框架的立体结构图;
图3为本发内引线的结构图;
图4为本实用新型内引线的立体图;
图5为本实用新型芯片的结构图。
其中:1、外引线A; 2、外引线B;3、第一芯片;4、第二芯片;5、内引线;6凸台;7、载片台;8、引线框架。
具体实施方式
如图1-5所示,一种双芯片横向串联型高耐压表面贴装的二极管封装结构,包括内引线5、由外引线A1、外引线B2以及两个凸台6组成的引线框架8,外引线A1、外引线B2分别与载片台7连为一体,两个载片台7上均设有凸台6,内引线5底面设有两个凸台6,两个载片台7上的两个凸台6与内引线5底面的两个凸台6之间设置第一芯片3与第二芯片4。
第一芯片3的阳极面与内引线5底面左侧的凸台6焊接在一起,其阴极面与外引线A1的载片台7顶面的凸台6焊接在一起。
第二芯片4的阴极面与内引线5底面右侧的凸台6焊接在一起,其阳极面与外引线B2的载片台7顶面的凸台6焊接在一起。
第一芯片3和第二芯片4是两个具有相同功能和尺寸的TVS、半导体放电管或普通整流二极管芯片。
本实用新型用两个相同额定电压值的TVS等二极体芯片,采用串联方式的封装结构和制造方法,提高了二极管的电压值以及TVS等器件的功率;内引线为底面设有两个共面凸台的电极片分别与两芯片的阴极和阳极焊接,芯片厚度变化无需修改内引线;结构为双芯片横向串联,相同封装体厚度可容芯片的厚度尺寸大;本实用新型为双芯片横向串联二极管,作为整流器件若其中一个芯片被击穿,另一个芯片仍可继续工作。

Claims (2)

1.一种双芯片横向串联型高耐压表面贴装的二极管封装结构,其特征在于:包括内引线、由外引线A、外引线B以及两个凸台组成的引线框架,所述外引线A、外引线B分别与载片台连为一体,所述两个载片台上均设有凸台,所述内引线底面设有两个凸台,所述两个载片台上的两个凸台与内引线底面的两个凸台之间设置第一芯片与第二芯片,所述第一芯片与内引线底面左侧的凸台焊接在一起的为阳极面,其阴极面与外引线A的载片台顶面的凸台焊接在一起,所述第二芯片与内引线底面右侧的凸台焊接在一起的为阴极面,其阳极面与外引线B的载片台顶面的凸台焊接在一起。
2.所述第一芯片和第二芯片是两个具有相同功能和尺寸的TVS、半导体放电管或普通整流二极管芯片。
CN201720978091.5U 2017-08-07 2017-08-07 一种双芯片横向串联型高耐压表面贴装的二极管封装结构 Active CN207676903U (zh)

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