CN208077957U - 三片式外置电容式同步整流二极管 - Google Patents

三片式外置电容式同步整流二极管 Download PDF

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CN208077957U
CN208077957U CN201721879409.0U CN201721879409U CN208077957U CN 208077957 U CN208077957 U CN 208077957U CN 201721879409 U CN201721879409 U CN 201721879409U CN 208077957 U CN208077957 U CN 208077957U
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李明芬
吴南
吕敏
李联勋
马东平
王鹏
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Shandong core electronic Polytron Technologies Inc
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SHANDONG DIYI ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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Abstract

本实用新型公开了三片式外置电容式同步整流二极管，三片式外置电容式同步整流二极管，包括第一框架、MOSFET芯片、控制IC芯片、第二框架、第三框架，所述第二框架设有一个外置引脚，控制IC芯片固定在第二框架上，第二框架一侧设有第三框架，第三框架设有一个外置引脚，第一框架设有一个外置引脚，MOSFET芯片固定在第一框架上；所述MOSFET芯片与控制IC芯片之间、控制IC芯片与第三框架之间、MOSFET芯片与第二框架之间、控制IC芯片与第一框架之间通过键合线连接。三片式外置电容式同步整流二极管，优化了结构，整合PAD可利用面积，排除了易造成不良的结构缺陷。

Description

三片式外置电容式同步整流二极管
技术领域
本实用新型涉及芯片生产领域，尤其是一种三片式外置电容式同步整流二极管。
背景技术
肖特基整流管的结构原理与PN结整流管有很大的区别通常将PN结整流管称作结整流管，而把金属-半导管整流管叫作肖特基整流管。现有的整流元件肖特基二极管存在整流损耗大转换效率低的问题。
同步整流二极管是由控制IC、功率MOSFET及其附属电路组成，从而实现低损耗整流的新技术。现有同步整流结构元件拙而不巧，尺寸较大，散热困难、引脚纤细反复，对安装使用造成一定的困扰。
实用新型内容
为了解决现有技术的不足，本实用新型提出了三片式外置电容式同步整流二极管，优化了结构，整合PAD可利用面积，排除了易造成不良的结构缺陷。
本实用新型采用如下技术方案：
三片式外置电容式同步整流二极管，包括第一框架、MOSFET芯片、控制IC芯片、第二框架、第三框架，所述第二框架设有一个外置引脚，控制IC芯片固定在第二框架上，第二框架一侧设有第三框架，第三框架设有一个外置引脚，第一框架设有一个外置引脚，MOSFET芯片固定在第一框架上；
所述MOSFET芯片与控制IC芯片之间、控制IC芯片与第三框架之间、MOSFET芯片与第二框架之间、控制IC芯片与第一框架之间通过键合线连接。
进一步地，所述第三框架的外置引脚连接电容。
进一步地，所述第一框架、第二框架为铜合金框架。
进一步地，所述第一框架、MOSFET芯片、控制IC芯片、第二框架、内置电容通过键合线焊接成型后封装于塑封体内，构成一个整体的同步整流二极管。
更进一步地，所述第一框架的外置引脚为同步整流二极管的阴极，第二框架的外置引脚为同步整流二极管的阳极。
采用如上技术方案取得的有益技术效果为：
顺应半导体整流器件向轻薄化、小型化、表面贴装的发展趋势，本实用新型研发的紧凑型同步整流结构及其制作方法，通过元件集成、优化结构，排除易造成不良的结构缺陷等手段，达到缩小元件尺寸，简化安装工艺，提高散热性之目的，因此该同步整流结构具有极大的优越性。
三片式外置电容式同步整流二极管，优化了结构，整合PAD可利用面积(PCB或印刷电路板中的焊盘放入面积)，排除了易造成不良的结构缺陷。
附图说明
图1为三片式外置电容式同步整流二极管结构示意图。
图2为三片式外置电容式同步整流二极管制作过程示意图。
图3为三片式外置电容式同步整流二极管产品封装示意图。
图4为三片式外置电容式同步整流二极管产品内部控制原理图。
图5为本实用新型正向整流应用电路图。
图6为本实用新型反向整流应用电路图。
图中，1、第一框架；2、MOSFET芯片；3、控制IC芯片；4、第二框架；5、第三框架。
具体实施方式
结合附图1至6对本实用新型的具体实施方式做进一步说明：
实施例1：
如图1所示，三片式外置电容式同步整流二极管，包括第一框架1、MOSFET芯片2、控制IC芯片3、第二框架4、第三框架5，所述第二框架设有一个外置引脚，控制IC芯片固定在第二框架上，第二框架一侧设有第三框架，第三框架设有一个外置引脚，第一框架设有一个外置引脚，MOSFET芯片固定在第一框架上；所述MOSFET芯片与控制IC芯片之间、控制IC 芯片与第三框架之间、MOSFET芯片与第二框架之间、控制IC芯片与第一框架之间通过键合线连接。
第三框架的外置引脚连接电容，电容称之为外置电容，外置电容与同步整流二极管匹配。外置电容可以选用MLCC电容。
第一框架、第二框架为铜合金框架。第一框架1、MOSFET芯片2、控制IC芯片3、第二框架4、第三框架5通过键合线焊接成型后封装于塑封体内，构成一个整体的同步整流二极管。
第一框架的外置引脚为同步整流二极管的阴极，第二框架的外置引脚为同步整流二极管的阳极。
三片式外置电容式同步整流二极管通过集成IC及MOSFET技术，简化同步整流器件的结构，缩小安装尺寸，方便客户端安装使用。
实施例2：
三片式外置电容式同步整流二极管采用如下流程制备：
(1)原物料准备：定制第一框架、第二框架、第三框架的铜合金框架，准备MOSFET芯片、控制IC芯片；器件安装前检验外观及电性剔出不良。
(2)芯片装片及焊接：用自动焊接机将MOSFET芯片与第一框架结合，控制IC芯片第二框架贴合，并焊接成型。
(3)引线键合：通过自动打线机键合各器件构成回路。
(4)塑封成型：将已键合完成的器件通过压模工序塑封成型。
(5)电镀及切粒：去残胶、引脚镀锡(若框架采用镍钯金或镍金表面处理后则不需镀锡)、烘烤、切粒。
(6)印测：将切粒后元件经测试机测试合格后印字装盒。
(7)目检：显微镜下观察，剔除外观不良。
(8)包装及入库。
采用如上流程制作成如图3所示的三片式外置电容式同步整流二极管。
实施例3：
如实施例1所述，三片式外置电容式同步整流二极管，第一框架的外置引脚为同步整流二极管的阴极，第二框架的外置引脚为同步整流二极管的阳极，第三框架的外置引脚连接电容。如图4所示，当阴极电压大于阳极时内置电容充能为控制IC芯片供电；当控制IC芯片检测到元件端电压大于开通电压Von时，开通MOSFET芯片，当检测到元件端电压趋于零时，关闭MOSFET芯片。
实施例4：
三片式外置电容式同步整流二极管在正向整流应用、反向整流应用如图5、图6所示。在正向整流应用中，交流输入先经桥式整流电路，再经滤波、脉宽调制，由变压器变压，变压器的高压端连接三片式外置电容式同步整流二极管的阳极，第三框架的外置引脚连接电容，再经稳压接负载。
在反向整流应用中，交流输入先经桥式整流电路，再经滤波、脉宽调制，由变压器变压，变压器的低压端连接三片式外置电容式同步整流二极管的阴极，第三框架的外置引脚连接电容，再经稳压接负载。
当然，以上说明仅仅为本实用新型的较佳实施例，本实用新型并不限于列举上述实施例，应当说明的是，任何熟悉本领域的技术人员在本说明书的指导下，所做出的所有等同替代、明显变形形式，均落在本说明书的实质范围之内，理应受到本实用新型的保护。

Claims (5)

1.三片式外置电容式同步整流二极管，其特征在于，包括第一框架(1)、MOSFET芯片(2)、控制IC芯片(3)、第二框架(4)、第三框架(5)，所述第二框架(4)设有一个外置引脚，控制IC芯片(3)固定在第二框架(4)上，第二框架(4)一侧设有第三框架(5)，第三框架(5)设有一个外置引脚，第一框架(1)设有一个外置引脚，MOSFET芯片(2)固定在第一框架(1)上；
所述MOSFET芯片(2)与控制IC芯片(3)之间、控制IC芯片(3)与第三框架(5)之间、MOSFET芯片(2)与第二框架(4)之间、控制IC芯片(3)与第一框架(1)之间通过键合线连接。
2.根据权利要求1所述的三片式外置电容式同步整流二极管，其特征在于，所述第三框架(5)的外置引脚连接电容。
3.根据权利要求1所述的三片式外置电容式同步整流二极管，其特征在于，所述第一框架(1)、第二框架(4)、第三框架(5)为铜合金框架。
4.根据权利要求1所述的三片式外置电容式同步整流二极管，其特征在于，所述第一框架(1)、MOSFET芯片(2)、控制IC芯片(3)、第二框架(4)、第三框架(5)通过键合线焊接成型后封装于塑封体内，构成一个整体的同步整流二极管。
5.根据权利要求1所述的三片式外置电容式同步整流二极管，其特征在于，所述第一框架(1)的外置引脚为同步整流二极管的阴极，第二框架(4)的外置引脚为同步整流二极管的阳极。
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