CN206595248U - 半导体器件的封装结构 - Google Patents

半导体器件的封装结构 Download PDF

Info

Publication number
CN206595248U
CN206595248U CN201720168090.4U CN201720168090U CN206595248U CN 206595248 U CN206595248 U CN 206595248U CN 201720168090 U CN201720168090 U CN 201720168090U CN 206595248 U CN206595248 U CN 206595248U
Authority
CN
China
Prior art keywords
chip
side pin
metal pad
pin
several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201720168090.4U
Other languages
English (en)
Inventor
张春尧
彭兴义
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Jiangsu Salt Core Microelectronics Co Ltd
Original Assignee
Jiangsu Salt Core Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Salt Core Microelectronics Co Ltd filed Critical Jiangsu Salt Core Microelectronics Co Ltd
Priority to CN201720168090.4U priority Critical patent/CN206595248U/zh
Application granted granted Critical
Publication of CN206595248U publication Critical patent/CN206595248U/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开一种半导体器件的封装结构,包括芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚和环氧树脂包覆体,环氧树脂包覆体包覆于芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚上,所述金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部;若干根第一金线两端分别与芯片和左侧引脚电连接,若干根第二金线两端分别与芯片和右侧引脚电连接;所述金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域。本实用新型有利于将引脚和金属焊盘更加牢固的固定,提高了与PCB之间焊接的可靠性,也以便芯片在工作时快速传导热量。

Description

半导体器件的封装结构
技术领域
本实用新型涉及一种芯片封装结构,涉及半导体技术领域。
背景技术
SOP封装是一种元件封装形式,常见的封装材料有:塑料、陶瓷、玻璃、金属等,现在基本采用塑料封装.,应用范围很广,主要用在各种集成电路中。如图1所示,现有的SOP封装结构中的焊盘一般为对应于电子元器件的信号引脚独立设置的单个的独立的小焊盘。但是随着产品耗电流越来越大,有些SOP封装芯片也被用于大电流电路中,起电流转换的作用给某些模块供电,但是这些传统的SOP封装在PCB中对应的焊盘设计越来越不符合要求,因为焊盘尺寸面积太小,在承载大电流时瞬间电流非常大,电流产生的脉冲在极短时间内会将芯片击穿,很有可能烧毁整个电路,损失非常大。传统的SOP封装焊盘无法承载更大电流,导致芯片的散热不行、电路功能的不稳定、极短的时间大电流的冲击容易损坏芯片,从而影响产品的质量。
发明内容
本实用新型目的是提供一种半导体器件的封装结构,该半导体器件的封装结构有利于将引脚和金属焊盘更加牢固的固定,提高了与PCB之间焊接的可靠性,也以便芯片在工作时快速传导热量,散热效果好。
为达到上述目的,本实用新型采用的技术方案是:一种半导体器件的封装结构,包括芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚和环氧树脂包覆体,所述芯片通过绝缘胶层固定于金属焊盘上表面的中央区域,若干个所述左侧引脚并排间隔地设置于芯片的左侧,若干个所述右侧引脚并排间隔地设置于芯片的右侧,所述金属焊盘下部边缘处开有第一缺口槽,所述左侧引脚与金属焊盘相向的内侧端下部开有左梯形凹槽,所述右侧引脚与金属焊盘相向的内侧端下部开有右梯形凹槽,所述环氧树脂包覆体包覆于芯片、金属焊盘、若干个左侧引脚、若干个右侧引脚上,所述金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部;
若干根第一金线两端分别与芯片和左侧引脚电连接,若干根第二金线两端分别与芯片和右侧引脚电连接,所述左侧引脚和右侧引脚各自的内侧端面分别开有供填充环氧树脂的左梯形凹槽和右梯形凹槽;所述金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域。
上述技术方案中进一步改进的方案如下:
1. 上述方案中,所述左侧引脚、右侧引脚的下表面镀覆有金属镀层。
2. 上述方案中,所述金属镀层为锡层或者镍钯金层。
3. 上述方案中,所述金属镀层与左侧引脚或者右侧引脚的厚度比为1:6~12。
4. 上述方案中,所述左侧引脚和右侧引脚的数目均为3~10根。
由于上述技术方案运用,本实用新型与现有技术相比具有下列优点:
1. 本实用新型半导体器件的封装结构,其金属焊盘下部边缘处开有第一缺口槽,左侧引脚和右侧引脚各自的内侧端面分别开有左梯形凹槽和右梯形凹槽,位于引脚内侧端面的中间区域填充有环氧树脂,既有利于将引脚和金属焊盘更加牢固的固定,也相应的增加引脚底部的面积,从而提高了与PCB之间焊接的可靠性和降低接触电阻;其次,其芯片通过绝缘胶层固定于金属焊盘上表面的中央区域,金属焊盘、左侧引脚和右侧引脚各自的下表面裸露出环氧树脂包覆体的底部,裸露的金属焊盘,以便芯片在工作时快速传导热量,散热效果好。
2. 本实用新型半导体器件的封装结构,其金属焊盘上表面沿边缘开有一闭合的环形储膏槽,此环形储膏槽的截面形状为倒梯形,此环形储膏槽位于芯片正下方并靠近芯片的边缘区域,有效避免了导热绝缘胶外溢而引起的短路故障,提高了产品成品率,使得加工生产更为简单方便,提高了集成芯片的稳定性和可靠性;其次,其左侧引脚、右侧引脚的下表面镀覆有金属镀层,既降低了器件与PCB的导电接触电阻,也有利于与PCB之间的焊接强度的提高。
附图说明
附图1为本实用新型半导体器件的封装结构结构示意图。
以上附图中:1、芯片;2、金属焊盘;3、左侧引脚;4、右侧引脚;5、环氧树脂包覆体;6、绝缘胶层;7、第一缺口槽;8、左梯形凹槽;9、右梯形凹槽;15、第一金线;16、第二金线;17、金属镀层;18、环形储膏槽。
具体实施方式
下面结合附图及实施例对本实用新型作进一步描述:
实施例1:一种半导体器件的封装结构,包括芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4和环氧树脂包覆体5,所述芯片1通过绝缘胶层6固定于金属焊盘2上表面的中央区域,若干个所述左侧引脚3并排间隔地设置于芯片1的左侧,若干个所述右侧引脚4并排间隔地设置于芯片1的右侧,所述金属焊盘2下部边缘处开有第一缺口槽7,所述左侧引脚3与金属焊盘2相向的内侧端下部开有左梯形凹槽8,所述右侧引脚4与金属焊盘2相向的内侧端下部开有右梯形凹槽9,所述环氧树脂包覆体5包覆于芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4上,所述金属焊盘2、左侧引脚3和右侧引脚4各自的下表面裸露出环氧树脂包覆体5的底部;
若干根第一金线15两端分别与芯片1和左侧引脚3电连接,若干根第二金线16两端分别与芯片1和右侧引脚4电连接,所述左侧引脚3和右侧引脚4各自的内侧端面分别开有供填充环氧树脂的左梯形凹槽8和右梯形凹槽9;所述金属焊盘2上表面沿边缘开有一闭合的环形储膏槽18,此环形储膏槽18的截面形状为倒梯形,此环形储膏槽18位于芯片1正下方并靠近芯片1的边缘区域。
上述左侧引脚3、右侧引脚4的下表面镀覆有金属镀层17;上述金属镀层17为锡层或者镍钯金层。
上述金属镀层17与左侧引脚3或者右侧引脚4的厚度比为1:8;上述左侧引脚3和右侧引脚4的数目均为8根。
实施例2:一种半导体器件的封装结构,包括芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4和环氧树脂包覆体5,所述芯片1通过绝缘胶层6固定于金属焊盘2上表面的中央区域,若干个所述左侧引脚3并排间隔地设置于芯片1的左侧,若干个所述右侧引脚4并排间隔地设置于芯片1的右侧,所述金属焊盘2下部边缘处开有第一缺口槽7,所述左侧引脚3与金属焊盘2相向的内侧端下部开有左梯形凹槽8,所述右侧引脚4与金属焊盘2相向的内侧端下部开有右梯形凹槽9,所述环氧树脂包覆体5包覆于芯片1、金属焊盘2、若干个左侧引脚3、若干个右侧引脚4上,所述金属焊盘2、左侧引脚3和右侧引脚4各自的下表面裸露出环氧树脂包覆体5的底部;
若干根第一金线15两端分别与芯片1和左侧引脚3电连接,若干根第二金线16两端分别与芯片1和右侧引脚4电连接,所述左侧引脚3和右侧引脚4各自的内侧端面分别开有供填充环氧树脂的左梯形凹槽8和右梯形凹槽9;所述金属焊盘2上表面沿边缘开有一闭合的环形储膏槽18,此环形储膏槽18的截面形状为倒梯形,此环形储膏槽18位于芯片1正下方并靠近芯片1的边缘区域。
上述左侧引脚3、右侧引脚4的下表面镀覆有金属镀层17。
上述金属镀层17与左侧引脚3或者右侧引脚4的厚度比为1:10;上述左侧引脚3和右侧引脚4的数目均为4根。
采用上述半导体器件的封装结构时,其既有利于将引脚和金属焊盘更加牢固的固定,也相应的增加引脚底部的面积,从而提高了与PCB之间焊接的可靠性和降低接触电阻;其次,其以便芯片在工作时快速传导热量,散热效果好;再次,其既降低了器件与PCB的导电接触电阻,也有利于与PCB之间的焊接强度的提高。
上述实施例只为说明本实用新型的技术构思及特点,其目的在于让熟悉此项技术的人士能够了解本实用新型的内容并据以实施,并不能以此限制本实用新型的保护范围。凡根据本实用新型精神实质所作的等效变化或修饰,都应涵盖在本实用新型的保护范围之内。

Claims (5)

1.一种半导体器件的封装结构,其特征在于:包括芯片(1)、金属焊盘(2)、若干个左侧引脚(3)、若干个右侧引脚(4)和环氧树脂包覆体(5),所述芯片(1)通过绝缘胶层(6)固定于金属焊盘(2)上表面的中央区域,若干个所述左侧引脚(3)并排间隔地设置于芯片(1)的左侧,若干个所述右侧引脚(4)并排间隔地设置于芯片(1)的右侧,所述金属焊盘(2)下部边缘处开有第一缺口槽(7),所述左侧引脚(3)与金属焊盘(2)相向的内侧端下部开有左梯形凹槽(8),所述右侧引脚(4)与金属焊盘(2)相向的内侧端下部开有右梯形凹槽(9),所述环氧树脂包覆体(5)包覆于芯片(1)、金属焊盘(2)、若干个左侧引脚(3)、若干个右侧引脚(4)上,所述金属焊盘(2)、左侧引脚(3)和右侧引脚(4)各自的下表面裸露出环氧树脂包覆体(5)的底部;
若干根第一金线(15)两端分别与芯片(1)和左侧引脚(3)电连接,若干根第二金线(16)两端分别与芯片(1)和右侧引脚(4)电连接,所述左侧引脚(3)和右侧引脚(4)各自的内侧端面分别开有供填充环氧树脂的左梯形凹槽(8)和右梯形凹槽(9);所述金属焊盘(2)上表面沿边缘开有一闭合的环形储膏槽(18),此环形储膏槽(18)的截面形状为倒梯形,此环形储膏槽(18)位于芯片(1)正下方并靠近芯片(1)的边缘区域。
2.根据权利要求1所述的半导体器件的封装结构,其特征在于:所述左侧引脚(3)、右侧引脚(4)的下表面镀覆有金属镀层(17)。
3.根据权利要求2所述的半导体器件的封装结构,其特征在于:所述金属镀层(17)为锡层或者镍钯金层。
4.根据权利要求2所述的半导体器件的封装结构,其特征在于:所述金属镀层(17)与左侧引脚(3)或者右侧引脚(4)的厚度比为1:6~12。
5.根据权利要求2所述的半导体器件的封装结构,其特征在于:所述左侧引脚(3)和右侧引脚(4)的数目均为3~10根。
CN201720168090.4U 2017-02-23 2017-02-23 半导体器件的封装结构 Expired - Fee Related CN206595248U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720168090.4U CN206595248U (zh) 2017-02-23 2017-02-23 半导体器件的封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720168090.4U CN206595248U (zh) 2017-02-23 2017-02-23 半导体器件的封装结构

Publications (1)

Publication Number Publication Date
CN206595248U true CN206595248U (zh) 2017-10-27

Family

ID=60126785

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201720168090.4U Expired - Fee Related CN206595248U (zh) 2017-02-23 2017-02-23 半导体器件的封装结构

Country Status (1)

Country Link
CN (1) CN206595248U (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10861834B2 (en) 2018-03-08 2020-12-08 Kunshan New Flat Panel Display Technology Center Co., Ltd. Micro-LED chips, display screens and methods of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10861834B2 (en) 2018-03-08 2020-12-08 Kunshan New Flat Panel Display Technology Center Co., Ltd. Micro-LED chips, display screens and methods of manufacturing the same

Similar Documents

Publication Publication Date Title
WO2015043499A1 (zh) 一种半导体封装结构及其成型方法
CN104051363B (zh) 芯片封装和用于制造该芯片封装的方法
CN106783792A (zh) 一种塑封体侧面引脚具有侧边爬锡性能的封装结构
CN206282838U (zh) 无源器件与有源器件的集成封装结构
CN105244347B (zh) 一种嵌入式封装及封装方法
CN207269022U (zh) 一种引线框架及其芯片倒装封装结构
CN206532771U (zh) 散热型半导体器件
CN206595248U (zh) 半导体器件的封装结构
CN206789537U (zh) 表面贴装整流芯片
CN106684065A (zh) 一种集成式Mini整流桥新结构及其制作工艺
CN206595249U (zh) 承载大电流的sop器件封装结构
CN103985689B (zh) 电子装置及其封装结构
CN206789540U (zh) Sot封装结构的半导体器件
CN103715161B (zh) 芯片装置,芯片封装和用于制作芯片装置的方法
CN206789534U (zh) 高可靠性芯片封装结构
CN102403236B (zh) 芯片外露的半导体器件及其生产方法
CN206532770U (zh) 芯片封装的新型sop结构
CN206992085U (zh) 高导热功率器件
CN203733790U (zh) 一种内部去耦的集成电路封装
CN206789543U (zh) 高导热型半导体器件封装结构
CN206210834U (zh) 一种焊盘面积小的led支架、led器件及led显示屏
CN206789541U (zh) 超薄型贴装式半导体器件
CN108878391A (zh) 智能功率模块结构及其制造方法
CN208478329U (zh) 用于sot/tsot封装的引线框架
CN206672916U (zh) 大电流半导体器件

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20171027

CF01 Termination of patent right due to non-payment of annual fee