CN206516630U - 三维集成电路 - Google Patents
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Abstract
一种三维集成电路(3D IC),包括:上器件层,具有转移器件互连层,和与所述转移器件互连层相对的一侧上的分离表面;粘结氧化层;以及下器件层,包括下器件互连层,所述下器件互连层粘结在所述上器件层上并且与所述转移器件互连层连通。本申请提供了异质且非均匀层的三维堆叠和互连,例如,完全制成的集成电路。包括用于显著减小层间分离并且增加可用的层间连接密度,从而得到增加的信号带宽和系统功能。
Description
本案是分案申请,其母案为于2016年1月11日申请的申请号为 201620024133.7的题为“三维集成电路”的专利申请。
相关专利申请的交叉引用
本申请要求通过引用方式全部并入本申请中的以下临时申请的每个的优先权:于2015年1月9日提交的美国临时专利申请No.62/101,954以及于2015 年2月24日提交的美国临时专利申请No.62/120,265。
技术领域
本申请总体上涉及集成电路装置的制造。
背景技术
本申请总体上涉及集成电路装置的制造。更具体地讲,本实用新型提供了使用异质(heterogeneous)且非均匀层堆叠并互连三维(3D)装置的所得装置,例如,完全制成的集成电路。举例来说,集成电路除其他之外可以包括存储装置、处理器装置、数字信号处理装置、专用装置、控制装置、通信装置等。
发明内容
根据本实用新型,提供了总体上涉及集成电路装置的制造的技术。更具体地讲,本实用新型提供了使用异质且非均匀层堆叠并互连三维(3D)装置的装置,例如,完全制成的集成电路。举例来说,集成电路除其他之外可以包括存储装置、处理器装置、专用装置、控制装置、通信装置等。
提供了一种具有电介质结构(dielectric structures)和导电结构(conductivestructures)的第一衬底。离子(ions)注入到所述第一衬底中,所述离子穿过所述电介质结构和所述导电结构以限定所述第一衬底中的分离平面(cleave plane)。所述第一衬底在所述分离平面被分离以获得具有所述电介质结构和所述导电结构的分离层。所述分离层形成三维集成电路装置的多个堆叠集成电路(integrated circuit,IC)层之一。
提供了异质且非均匀层的三维堆叠和互连,例如,完全制成的集成电路。包括用于显著减小层间分离并且增加可用的层间连接密度,从而得到增加的信号带宽和系统功能。
在实例中,一种设备包括第一衬底,所述第一衬底具有电介质结构、导电结构和第一互连结构,所述第一衬底包括在与所述第一互连结构相对的一侧上的分离表面。所述设备进一步包括粘结氧化层和第二衬底,所述第二衬底包括第二互连结构,所述第二互连结构粘结在所述第一衬底上并且与所述第一互连结构连通以形成具有多个堆叠集成电路(IC)层的三维集成电路装置,所述第一衬底为所述堆叠集成电路层中的一个,并且所述第二衬底为所述堆叠集成电路层中的另一个。所述第二互连结构粘结在所述分离表面上或所述第一互连结构上。
附图说明
图1是转移器件的“底部”粘结在下方器件的“顶”层上的本实用新型的简化剖视图。
图2图示了包括一层晶体管器件和金属及低介电常数材料的上网络 (uppernetwork)的异质结构,在实例中考虑到穿过附加的图案化光致抗蚀剂层的注入所提供的层间冷却剂通道。
图3是示出了在适当位置并入冷却剂通道的图案化高导热率层的简化剖视图。
图4示出了粘结三维IC堆(3D IC stack)中的转移器件层和下器件层的“顶对顶”金属层的简化剖视图。
具体实施方式
根据本实用新型,提供了总体上涉及集成电路装置的制造的技术。更具体地讲,本实用新型提供了使用异质且非均匀层堆叠并互连三维(3D)装置的装置,例如,完全制成的集成电路。举例来说,集成电路除其他之外可以包括存储装置、处理器装置、数字信号处理装置、专用装置、控制装置、通信装置等。
在实例中,本实用新型建立并扩展了两大技术领域的能力,用于形成异质层的粘结堆叠的层转移(layer transfer),例如,形成当今使用的绝缘体上硅 (Silicon-on-Insulator,SOI)晶片,以及用于器件间连接的通过使用中介层 (interposer layers)与金属通路的稀疏阵列综合进行开发以形成电子装置的三维堆叠。
在实例中,本实用新型提供了具有简化的粘结及互连结构的多种电子及机电层的堆叠和互连,所述简化的粘结及互连结构具有比目前可用的中介层 /TSV方法小1/10或更多的物理量级并且提供用于极大增加的数量的器件间电子连接路径,从而得到极大扩展的数据传输带宽和三维装置功能。本实用新型还提供用于保护敏感器件层以避免与使用高能质子束线(proton beamlines) 相关的有害的紫外线辐射,并且用于构造用于去除来自有源的运行的三维装置堆(3-D device stack)的体积的热量的冷却剂流通道的层间网络(network)。通过本说明书以及下文的更具体的描述可以发现本实用新型的进一步细节。
实施例可以兼容多种IC制造方法,包括用于制造互补金属氧化物半导体 (CMOS)和随机存取存储器(RAM)装置等的方法。
使用MeV能量的注入允许穿过整个器件层(10ums)的注入更厚。因此,可以转移整个CMOS器件层,而不是部分层。
具体实施例可以利用具有对应的互连深度、位置和密度的前后堆叠和前前堆叠粘结的变型。
一些实施例可以使全部器件层元件(不需要中介层)变薄,甚至对于高密度器件间通路连接具有减小的RC损耗。
各种实施例可以通过具有大为减少的“避开(keep out)”区域的连接降低来自铜/硅应力(stress)的应力。
图1是本实用新型的实施例的简化剖视图。上器件层,包括形成在半导体材料(通常为硅)中的晶体管的异质层,以及金属(通常为铜与用于衬垫和通路的多种其他金属)的致密网络,由低介电常数的电绝缘材料分开的层,在通过氢注入形成及相关分离之后与半导体晶圆分开。在质子注入期间,转移器件结构覆盖有足够厚度和性能的均匀的光致抗蚀剂层以保护器件层免于因暴露于来自在质子束线等离子(proton beam line plasma)中的重组的紫外线辐射而受损。对于图1所示的情况,转移器件层还涂覆有第二光致抗蚀剂层,该第二光致抗蚀剂层被图案化以调节质子束的深度以及沿着冷却剂流通道的网络的路径的所得的分离表面(cleave surface),该冷却剂流通道被设计成从完整的三维装置堆的体积去除热量。导电结构包括衬底中的晶体管结 (transistor junctions)以及与晶体管层连接的金属互连网络(metal interconnect network)。
在将上器件层安装在临时粘结处理层上之后,转移器件的被分离的下表面经过处理以去除分离表面的区域中的注入受损并且调节转移器件衬底层的厚度。CVD氧化层沉积在下表面上以提供足够的粘结表面并且提供用于冷却剂流通道(如果存在)的绝缘的钝化表面。下器件表面然后经过蚀刻并且填满金属以通过衬底和沉积的氧化层形成通往转移器件互连层的层间电连接,沉积的氧化层厚度为1微米或更厚的数量级。上转移器件层中的层间金属线与金属粘结焊盘端接,该金属粘结焊盘具有与沉积的氧化物粘结层在同一平面上的粘结表面。
类似的沉积的氧化物形成在下器件顶表面上以提供足够的粘结,通路的网络经过蚀刻并且填满金属以提供与下器件互连层的电连接。下金属线端接与下沉积氧化物表面在同一平面上的金属粘结焊盘。
两组金属粘结焊盘在精确粘结设备中对齐并且经过粘结退火(bond annealing),从而完成图1所示的2层堆叠(具有冷却剂通道)。
图2示出了在层转移到下器件层上之后的图案化光致抗蚀剂(PR)层和器件层的视图。在图2中,包括一层晶体管器件和提供用于集成电路(IC) 的互连的金属及低介电常数材料的上网络的异质结构涂覆有均匀的光致抗蚀剂(PR)层,其中抗蚀剂的性能和厚度被选择成给敏感的IC层和界面提供充分的保护以避免暴露于在质子加速器束线等离子(protonaccelerator beamline plasma)中的重组事件中引起的紫外线(波长小于400nm)辐射。均匀的光致抗蚀剂层的厚度和阻止(stopping)也被选择成将质子束的范围调节到在IC 装置晶体管和耗尽层(depletion layers)以下的期望的深度。
在图2中,第二图案化光致抗蚀剂层叠加在均匀的光致抗蚀剂层上,第二光致抗蚀剂层的厚度和阻止被选择成局部调整注入的质子分布的深度以提供非平面材料分离表面。当转移器件层粘结在下器件层上时,在去除光致抗蚀剂层并且临时粘结在保持层上之后,非平面分离表面提供用于成品IC装置堆(IC device stack)中的冷却剂流的网络路径(反映上光致抗蚀剂层的图案化),该冷却剂用于在器件运行期间去除热量。
尽管吸收体在图2中图示为光致抗蚀剂(absorber),但这不是必要的。在替代实施例中,其他材料可以用作吸收体,包括但不限于氧化物和/或氮化物。
图1至图2还示出了层间金属通路和粘结附着焊盘以及氧化物粘结界面,该氧化物粘结界面在粘结到下器件层之前叠加在上转移器件层的下部。
一般来讲,高性能逻辑器件(logic devices)在逻辑核心(logic core)中的高开关活动(switching activity)的区域中产生热量。这些开关加热(switching heating)的来源在复杂片上系统(SOC)和中央处理器(CPU)装置中是众所周知的设计关注点。存储器件中的数据的保留通常随着温度升高而劣化,所以逻辑和存储器层的集成堆叠受到这些热关注点的挑战。随着三维器件堆叠的密度和多样性的增加,热控制变得更加重要。
尽管有益于热粘结效率,但是在粘结堆中使用氧化物层可能由于SiO2较低的导热率而被限制成热传递层。使用更高导热率的电绝缘材料作为层间结构可以增加从局部器件热源区域的热传递。
因此,在某些实施例中,可能有利的是,在产热器件层之间增加结构化的高导热率层,以便便于从器件堆散热和去除热量。特别地,使用高能质子注入、低热预算层(low-thermal budget layer)分离和转移粘结可以便于通过使用局部冷却剂流从局部器件结构“热点(hot spots)”散热并且高效地去除器件的热能。
以下列出了几种普通的半导体和绝缘膜的导热率(单位:W/m-K)。
Si:130(W/m-K)
SiO2:1.3(W/m-K)
SiC:120(W/m-K)
Ge:58(W/m-K)
GaAs:52(W/m-K)
Al2O3:30(W/m-K)
厚度≈0.5至2um的层间传热层可以被期望用于高效热流。图3示出了包括在适当位置并入冷却剂通道的高导热率层的简化剖视图。
包括半导体、电介质材料和金属材料的多个层的集成电路装置在制造期间可能形成相当大的内应力。尚未解决的是,这些应力可以足够高以使整个厚度的硅晶圆(具有大于700微米的厚度)扭曲成各种凹形、凸形和复杂的“炸土豆片”形状。这些变形可以足够大到在器件制造器件在精细线路光刻光学中导致问题。
如果分离的薄(例如,几微米)衬底上含应力的器件层以未被支撑的方式放置在平表面上,那么晶圆级组合的应力引起的变形可能对平衬底表面的粘结提出挑战。由于这些效应,薄器件层在将它们从它们的初始衬底晶圆分离之前可以附接到刚性粘结结构上,该粘结结构能够维持与应力层附接的平面粘结界面。
即使在使用刚性的临时粘结夹持器以使含应力的层形成为适用于粘结的平面形式,复杂粘结堆中未补偿的应力可能在后续制造步骤期间以及在器件运行期间由于热应力而导致粘结失效和IC装置退化。
因此,实施例可以提供用于添加应力补偿层到应力器件的薄转移层的背侧以便于粘结,包括改进的层间器件以及粘结焊盘对齐,并且补偿后续制造和器件运行热循环的有害效应。
背侧应力补偿材料可以被选择成由具有对器件层的补偿热膨胀性能以及具有足以抵消器件结构内应力的变形效应(distortion effect)的厚度的材料制成。
应力补偿层可以在将转移器件层附接到临时粘结结构上时通过直接层转移到转移器件层背侧来形成。在一些情况下,应力补偿层可以通过CVD或其他途径沉积。
要注意的是,平面的、应力补偿的转移层可以提供用于在晶圆级(wafer level)粘结期间实现高度的粘结焊盘对齐(三维IC制造的成功的晶圆级粘结的一种考虑)的令人满意的几何结构。
具体实施例可以采用单晶层转移到化学或机械“脆弱”的分离层。具体地讲,可以希望允许将高纯度单晶材料层附接到临时保持层上,该临时保持层足够坚固以承受IC或其他器件制造方法的热应力、化学应力和机械应力,但是足够“脆弱”以在定向的化学或机械作用下形成分离路径。
这些脆弱的临时分离层的实例可以包括但不限于以下实例:(1)通过热生长、CVD沉积或者通过直接氧注入(direct Oxygen implantation)及后续热处理形成的氧化物层,能够通过选择性蚀刻剂的化学作用(例如,HF攻击下方的SiO2层)而在上覆盖层下方形成分离路径;以及(2)在选择的化学或机械攻击下易于形成分离路径的多种形式的多晶材料或多孔形式的普通衬底材料。定向的机械攻击的形式可以包括但不限于:(1)施加于楔形分离工具的侧向定向的力引起的应力辅助裂缝形成(stress-assisted crack formation);以及 (2)通过到机械脆弱层(例如,多孔衬底材料区域)中的侧向定向的流体喷射的动能攻击(kinetic attack)。
一些形式的化学或机械脆弱的分离层可能缺乏可用于制造高性能半导体器件的高纯度和高质量晶体上层的外延生长所需的高水平晶体界面。
通过采用高能质子注入以形成用于沿着明确限定的分离表面的在室温下的机械分离的氢富含层,实施例可以用于分离和粘结整个器件结构(包括全部形成的晶体管层和多级金属互连网络)到适当选择的临时分离层上,用于随后的制造和器件集成制造。随后可以从载体衬底分离。
实施例也可以用于分离和粘结均匀的高纯度晶体层,所述晶体层将要形成为电子器件、机械器件或光学器件,随后从载体衬底分离。
实施例也可以提供可用于分离的质子注入以及高敏感性CMOS器件结构的层转移堆叠。如此前提及的,实施例利用高能质子注入以形成富含氢的分离表面,所述富含氢的分离表面在光致抗蚀剂或CVD电介质的顶层及多层金属互连网络和晶体管层的组合的结合厚度以及阻止力效果(stopping power effects)以下几微米。
穿过金属互连层和晶体管层的高剂量高能质子束的通过引起的辐射损伤效果可以是可管理的水平——在适中的温度通过标准退火循环可恢复。此外,当特定的辐射损伤效果有特别顾虑时,实施例可以包括以下实施方式:考虑绕过器件电介质层中的辐射损伤效果。
在高剂量高能质子注入到CMOS器件层及其相关的金属互连网络层中期间,与可能的辐射损伤相关的一个问题是多个电介质层中的粘结破坏效果。这可能是由于能量质子束通过引起的电子阻止事件(electronic stopping events)或者在加速器束线(accelerator beam line)中的重组事件之后的离子电子弛豫(ion-electronrelaxation)引起紫外线辐射。
当在CMOS器件制造期间在特定点进行高剂量高能质子注入时,可以显著避免质子束造成的辐射效果。CMOS制造中的一个点可以被认为是在完成与CMOS结(junctions)中的掺杂物(dopants)的激活相关的高温(例如,大于500℃)之后,并且在沉积敏感的栅极堆氧化物及后续在金属互连网络中并入层间电介质之前。
在CMOS制造中的这个点,器件晶圆中的主要材料是掺杂结(多晶硅填满侧向隔离区域)和衬底晶圆中的晶体硅。在主要的硅材料中唯一显著的长期辐射损伤效果与质子减速的核阻止元件(nuclear stopping components)引起的晶格损伤(lattice damage)相关。
高能质子束的晶格损伤事件可能局限在质子轮廓(proton profile)的峰值附近。根据实施例,该峰值可以位于晶体管层中的CMOS结以下几微米,并且为层分离期间的分离表面的定位提供关键的氢捕获点(hydrogen-trapping sites)。CMOS晶体管层及其相关的载体耗尽层之间的几微米间隔和后续的层分离的区域中的质子引起的晶格损伤可以足够避免质子晶格损伤层引起的有害的器件效果。
在许多先进的CMOS器件中,栅极堆区域最初由临时膜以及在完成高温热循环之后被“替换”成并入高介电常数(“高k值”)栅极氧化物和多层金属栅极电极的最终器件结构的结构限定。在“替换栅极”制造循环之后,最终栅极和金属层间(“低k值”)电介质的材料性能将最终CMOS器件制造的可允许的热循环限制成小于500℃。
刚好在“替换栅极”制造之前的点实施的高剂量质子注入可以避免对最终器件栅极和金属层间电介质的损伤风险并且不能暴露于500℃或更高的热循环,这可能导致在完成转移器件层的制造之后在层分离的所需的非热式分离之前自发的层分离。
利用根据实施例的设备可以允许通过堆叠顺序和层间厚度来调节层间带宽(bandwidth)。特别地,三维IC堆的主要目的是提供用于增加器件之间的信号处理通信(signal processing communications)的带宽的替代路径。
带宽是数据信号频率(通常接近CPU时钟频率)与外部通信通道的数量的乘积。对于IC的大部分历史,IC发展集中在增加CPU和其他数据处理芯片循环频率,可能的代价是增加芯片的功耗。沿着平面型器件周边可用的粘结焊盘的密度已经限制了通信通道的数量。
三维IC堆的发展增加了按照层间通信线的密度测量的垂直通道的可用数量。层间连接的密度的便捷测量是通信引脚间隔或“节距”的负二次方。具体地讲,输入输出密度(IOdensity)=1/(引脚节距)2。
最小金属通道或“引脚”节距取决于各种各样的器件考量。一个因素是层间金属通道的纵横比(AR):金属线直径与待填充的通路孔的长度的比值。常规的“硅通孔”(ThroughSilicon Via,TSV)结构通常可以表现出约5至 20的纵横比。这显著高于IC装置的高密度金属化中的通路的典型的设计规则——通常为小于2的纵横比。
影响常规的TSV结构的堆叠密度的一个器件考量是微米级铜柱体和硅器件材料的不同的热膨胀引起的器件内的应力。紧挨着铜通路线周围的不期望的局部应力可能导致限定微米级“避开”区域的设计规则,其中铜通路附着焊盘附近排除有源电路元件。这影响电路密度、性能和产量。
因此,具体实施例可以提供一个或多个程序来局部增加层间金属通道密度以及相邻器件层之间对应的通信带宽。使用高能高剂量质子注入穿过基本上完成的金属互连网络和完全形成的CMOS晶体管层用于形成用于非热式层分离层的氢富含区域并且粘结到三维IC堆上,提供了几微米(或者更小,对于掩埋氧化物的SOI上的器件层或具有最小载体耗尽层厚度的其他器件类型的情况)的层间间隔。这允许比当今的TSV和中介层堆叠(interposer stacking) 所特有的几十微米的层间间隔更小的层间间隔。实施例提供的更薄的器件间硅层以及消除中介层和相关粘合剂层允许制造更短且更薄的器件间金属信号连接并且极大地减小当今几微米厚的铜TSV通道的热应力引起的“死区”效应。
在需要高的层间带宽的情况中(例如,用于CMOS图像传感器层和信号装置的连接),一些实施例可以采用各种各样的层转移技术以使转移器件的金属互连网络的顶层对齐并粘结至三维IC堆中的下器件层的金属网络的顶层的层间连接通道。
由于这种特定的程序,可以预期层间通信通道密度类似于两个器件层中的顶层金属化层(具有在几微米或更小的数量级的引脚节距)中的引脚密度。这种“顶对顶”层粘结得到比现有的2.5维和三维芯片堆叠技术高100至1000 x的因子的层间连接密度以及相应增加的带宽。
图4示出了粘结三维IC堆中的转移器件层和下器件层的“顶对顶”金属层的简化剖视图。这种方法可以提供与CMOS器件的顶部金属层的通路密度类似的层间金属连接通道密度和相应增加的带宽。
根据实施例的三维IC结构的具体实例的特征可以是在1.0E+02至 1.0E+04nm的引脚节距范围内在约1.0E+06至1.0E+08之间的输入输出密度 (引脚/cm2)。在实例中,对于1μm的TSV深度,在约0.1μm至1μm的TSV 直径的范围内,纵横比(深度:最小宽度或直径)可以在1至10的范围内。
如上所述,根据实施例通过质子注入以形成三维IC结构可以在约1MeV 的能量进行,包括在约300keV至5MeV之间的能量,约500keV至3MeV 之间的能量,约700keV至2MeV之间的能量,或约800keV至1MeV之间的能量。
要注意的是,在这种较高能量范围内的氢离子的注入性能可以在用于SOI 晶圆制造的层转移所典型具有的能量40keV之间变化。第一级描述是反映“离散(straggling)”(<ΔX>)的质子轮廓的“半宽”与“投影射程(projected range)”轮廓(<X>)的深度的比值。
在实例中,这种<ΔX>/<X>的结果的比较如下:
●质子注入能量40keV:<ΔX>/<X>=0.196≈0.2
●质子注入能量1MeV:<ΔX>/<X>=0.048≈0.05
因此,1MeV质子轮廓约等于比40keV质子轮廓“尖(sharper)”4倍。
尽管上述是具体实施例的全部描述,但是可以使用多个修改、替代构造和等同形式。因此,上述描述和说明不应当被视为限制由所附权利要求书限定的本实用新型的范围。
Claims (10)
1.一种三维集成电路,包括:
上器件层,具有转移器件互连层,和与所述转移器件互连层相对的一侧上的分离表面;
粘结氧化层;以及
下器件层,包括下器件互连层,所述下器件互连层粘结在所述上器件层上并且与所述转移器件互连层连通。
2.根据权利要求1所述的三维集成电路,其中,所述下器件互连层粘结在所述分离表面上。
3.根据权利要求1所述的三维集成电路,其中,所述下器件互连层粘结在所述转移器件互连层上。
4.根据权利要求1所述的三维集成电路,其在1.0E+02至1.0E+04nm的引脚节距范围内的输入/输出密度在1.0E+06至1.0E+08引脚/cm2之间。
5.根据权利要求1所述的三维集成电路,其中,所述分离表面限定冷却剂流通道。
6.根据权利要求1所述的三维集成电路,其中,所述上器件层包括硅通孔TSV,所述硅通孔在直径为0.1至1μm的硅通孔的范围内具有的纵横比,即,深度:直径的最小宽度,在1至10之间。
7.根据权利要求1所述的三维集成电路,其中,所述分离表面富含氢。
8.根据权利要求7所述的三维集成电路,其中,所述氢反映离散与质子范围的比值为0.1或更小。
9.根据权利要求1所述的三维集成电路,进一步包括应力补偿层。
10.根据权利要求1所述的三维集成电路,进一步包括高导热率层。
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