CN205845961U - 集成电路 - Google Patents

集成电路 Download PDF

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CN205845961U
CN205845961U CN201620444286.7U CN201620444286U CN205845961U CN 205845961 U CN205845961 U CN 205845961U CN 201620444286 U CN201620444286 U CN 201620444286U CN 205845961 U CN205845961 U CN 205845961U
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J·希门尼斯
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STMicroelectronics Crolles 2 SAS
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Abstract

本公开涉及集成电路。根据本实用新型的用于制造BiCMOS类型的集成电路(CI)的方法包括制造至少一个垂直结场效应晶体管(T1)，其包括形成具有通过光刻控制的有源表面(D)的临界尺寸的沟道区域(ZC)。

Description

集成电路
技术领域
本实用新型各个实施例及其实施方式涉及集成电路，具体地，涉及在半导体衬底内制造结型场效应晶体管(JFET)，适用于双极技术和CMOS技术(BiCMOS)。
背景技术
JFET晶体管通常在输出处提供较低的电噪声，并且通常具有良好的高压性能。例如，JFET晶体管用于具有高输出阻抗的精密运算放大器的输入级。
双极晶体管显示出高增益、高输出阻抗并在高频下提供良好的性能，这使得它们有利地用于例如高频模拟放大器。
另一方面，使用CMOS技术制造的MOS晶体管通常显示出高输入阻抗并且尤其在数字电子的逻辑电路中使用时。
BiCMOS技术提供了两种类型的技术(双极和CMOS)的优势，并且有利地用于具有混合信号(模拟和数字)的应用。
然而，用于制造BiCMOS类型的电子电路的方法必须满足双极和CMOS技术的生产约束，尤其是因为两种技术之间不同的独特步骤。
当前，在BiCMOS集成电路中集成JFET晶体管涉及在已经经受显著约束的制造方法中引入附加步骤，这导致成本的缺陷。
此外，当前的JFET晶体管是平面的，其具有横向结。
JFET晶体管的夹断(pinch)电压直接取决于结的几何结构，并且尤其通过沟道的有源表面的临界尺寸来确定。
平面JFET晶体管的沟道区域通常通过掺杂半导体材料的交错层(形成JFET晶体管的源极、栅极和漏极区域的布置)来形成。
因此，平面JFET晶体管的沟道的大小(尤其是其有源表面的临界尺寸)通过掺杂物的扩散来确定，从而难以控制和调整。
此外，在用于制造平面JFET晶体管的相同工艺内，形成夹断电压相互不同的JFET晶体管要求附加的掩蔽和注入步骤。
实用新型内容
由于存在平面JFET晶体管的沟道的大小(尤其是其有源表面的临界尺寸)通过掺杂物的扩散来确定，从而难以控制和调整的问题，故需要提供如下半导体器件对上述技术问题进行解决。
根据一个实施例，提供了一种JFET晶体管，其沟道区域的沟道临界尺寸根据一个实施例及其实施方式而被更好地控制。
根据一个实施例，还提供了一种用于在BiCMOS类型的集成电路内制造JFET晶体管的方法，其不包括针对用于制造BiCMOS的制造电路的传统方法附加的任何步骤。
根据一个方面，提供了用于制造集成电路的方法，包括制造至少一个垂直结场效应晶体管，包括具有通过光刻控制的有源表面的临界尺寸的沟道区域的形成。
该方法可包括用于制造垂直结场效应晶体管的多个同步工艺，其中，在公共的光刻步骤期间控制根据晶体管而不同的沟道区域的有源表面的各个临界尺寸。
由于传统和已知的光刻工艺被良好控制、精确且可复制的，所以沟道的有源表面的临界尺寸根据方法的实施方式的不同而显出非常低的变化性。因此，通过该方法制造的晶体管的夹断电压也显示出非常低的变化性。
此外，光刻工艺是用于制造电子电路的方法中的公共步骤，并且容易修改。因此，根据本方面，可以在相同方法的实施期间制造夹断电压不同的多个JFET晶体管而不需要附加的工艺步骤或时间。
此外，JFET晶体管的垂直特性使得容易被插入到CMOS类型的制造工艺中。
根据该方法的一个实施例，所述沟道区域的形成包括：在第一导电类型的半导体阱中形成第二导电类型的两个栅极区域，所述沟道区域的有源表面的所述临界尺寸通过所述两个栅极区域之间的间隔来限定。
垂直结场效应晶体管的制造还可以包括：形成与所述两个栅极区域接触的第二导电类型的栅极接触区域。
垂直结场效应晶体管的制造还可以包括漏极区域的形成，包括：在所述阱下方形成比所述阱更重掺杂的第一导电类型的隐埋层以及形成第一导电类型且从半导体阱的表面向下延伸到所述隐埋层的接触阱。
垂直结场效应晶体管的制造还可以包括：形成与所述沟道区域接触的第一导电类型的源极区域。
还提供了根据本方面的方法的一种实施方式，其不包括针对用于制造BiCMOS类型的集成电路的传统方法添加任何步骤。
根据该实施例，该方法进一步包括：在适当导电类型的对应阱内，形成同时利用所述至少一个垂直结场效应晶体管的制造来形成的第一导电类型的至少一个双极晶体管、第二导电类型的至少一个双极晶体管、第一导电类型的至少一个绝缘栅型场效应晶体管和第二导电类型的至少一个绝缘栅型场效应晶体管。
用于制造垂直JFET晶体管的方法的每个步骤都可以有利地与用于制造N型(NPN)或P型(PNP)的双极晶体管的传统步骤和/或用于制造N型(NMPS)或P型(PMOS)的绝缘栅型场效应晶体管的传统步骤同时进行。
该方法可包括：与所述栅极区域的形成同时地，在第一导电类型的双极晶体管的阱内形成第二导电类型的场注入区域。
确实，例如在高压运算放大器的输入级上存在的BiMCOS类型的集成电路必须偶尔抵抗40伏特级别的电压。通过填充有重掺杂材料的沟槽形成的场注入使得场线进一步远离有源结而扩展，因此提高了集成电路的部件的电压能力。
该方法可包括：与JFET晶体管的栅极接触区域的形成同时地，形成第二导电类型的双极晶体管的发射极区域和/或第二导电类型的绝缘栅型场效应晶体管的源极/漏极区域。
该方法可包括：与垂直结场效应晶体管的漏极区域的形成同时地，形成第一导电类型的双极晶体管的集电极区域，包括形成第一导电类型的比所述双极晶体管的半导体阱更重掺杂的隐埋层以及形成从双极晶体管的阱的表面向下延伸到所述隐埋层的第一导电类型的接触阱。
该方法可包括：与垂直结场效应晶体管的源极区域的形成同时地，形成第一导电类型的双极晶体管的发射极区域和/或第一导电类型的绝缘栅型场效应晶体管的源极/漏极区域。
形成第一或第二导电类型的发射极区域、第一或第二导电类型的源极和漏极区域以及包括接触阱和隐埋层的第一导电类型的集电极区域是用于制造BiCMOS类型的集成电路的方法的传统步骤。
在该方面中，JFET晶体管的制造引入相对于传统方法增加的任何步骤。
根据另一方面，提供了一种集成电路，包括至少一个垂直结场效应晶体管，包括第一导电类型的半导体阱、漏极区域、接触阱、栅极区域和源极区域，其中，漏极区域包括第一导电类型的比所述阱更重掺杂的隐埋层，接触阱为第一导电类型且从阱的表面向下延伸到所述隐埋层，栅极区域包括约束沟道区域的填充有第二导电类型的半导体材料的两个沟槽，并且源极区域为所述第一导电类型且位于所述沟道区域的顶部上。
该集成电路还可以包括：第一导电类型的至少一个双极晶体管、第二导电类型的至少一个双极晶体管、第一导电类型的至少一个绝缘栅型场效应晶体管和第二导电类型的至少一个绝缘栅型场效应晶体管。
结场效应晶体管的隐埋层和漏极接触阱可位于与双极晶体管的集电极区域的隐埋层和接触阱相同的层级处。
垂直结场效应晶体管的栅极区域可位于与第一导电类型的双极晶体管的场注入区域相同的层级处。
垂直结场效应晶体管的源极区域可位于与第一导电类型的双极晶体管的发射极区域相同的层级处和/或与第一导电类型的绝缘栅型场效应晶体管的漏极/源极区域相同的层级处。
垂直结场效应晶体管可包括栅极接触区域，所述栅极接触区域为第二导电类型、与所述栅极区域接触并且可位于与第二导电类型的双极晶体管的发射极区域相同的层级处。
根据一个实施例，集成电路包括多个垂直结场效应晶体管，各个垂直结场效应晶体管具有相互不同的有源表面的临界尺寸。
集成电路可包括形成单元结构的多个结型场效应晶体管。
使用单元结构架构避免了扩展JFET晶体管的约束以及扩展JFET晶体管中出现的不可预测的边缘效应。
附图说明
本实用新型的其他优势和特征将根据非限制性实施例及其实施方式的详细描述以及附图而变得明确，其中：
图1至图8示出了本实用新型的实施例及其实施方式。
具体实施方式
为了清楚，如同集成电路的表示，图1至图8是示意图并且不按比例绘制，使用相同的参考标号来表示两幅图中的相同元件。
此外，在以下描述中，第一导电类型将表示为N型而第二导电类型被表示为P型，尽管相反的情况根据本实用新型也是可以的。
图1示出了垂直结型场效应晶体管T1的一个实施例，其形成为形成在具有P型掺杂的半导体衬底10上的集成电路CI的一部分。尤其在具有N型掺杂的半导体阱21内制造晶体管T1，并且该晶体管包括漏极区域、源极区域81、栅极区域46和沟道区域ZC。
漏极区域包括N+型(比所述阱21更重掺杂)的隐埋层11，并且接触阱31也是N+类型的重掺杂。接触阱31从阱21的表面向下延伸到所述隐埋层11。
栅极区域46包括两个相邻的垂直沟槽，它们填充有P+类型的重掺杂半导体材料。这些沟槽约束它们之前的垂直沟道区域ZC。这些沟槽之间的距离D限定晶体管的沟道的有源表面的临界尺寸。
P型的重掺杂栅极接触区域71设置在阱21的表面上并且与所述栅极区域46接触。
N+型的重掺杂源极区域81形成在所述沟道区域ZC的顶部上，也形成在阱21的表面上。
此外，在栅极接触区域71与源极区域81之间以及在栅极接触区域71与漏极接触阱31之间形成局部氧化区域50，以将这些区域相互绝缘。类似地，在阱的表面的横向端处形成局部氧化区域50以将晶体管T1与集成电路CI(该晶体管形成为该集成电路的一部分)的剩余部分绝缘。
这些区域50可以是LOCOS类型，或者是浅沟槽(STI：浅沟槽隔离)。
图2示出了根据本实用新型的用于制造集成电路CI的方法的一个实施例的初始步骤的结果。这里，集成电路CI包括在以下附图中由虚线约束的五个区域Z1、Z2、Z3、Z4和Z5，其中，将分别根据本实用新型的一个实施例制造JFET晶体管T1、NPN类型的双极晶体管T2、PMOS类型的绝缘栅型场效应晶体管T3、PNP类型的双极晶体管T4和NMOS类型的绝缘栅型场效应晶体管T5。
在具有P型掺杂的硅的衬底10内，通过在衬底10的对应区域Z1、Z2、Z3中进行浅注入来形成N+类型的重掺杂隐埋层11、12、13。具有N型掺杂的半导体阱21、22、23分别通过在这些隐埋层11、12、13的顶部上的外延来形成。
类似地，通过在对应的区域Z4、Z5中的浅注入形成P+类型的重掺杂隐埋层14、15，通过外延在其上形成具有n型掺杂的阱，然后通过掺杂物的离子注入和扩散将它们分别转换为具有P型掺杂的阱24、25。
还通过阱21、22中的注入来形成N+类型的重掺杂接触阱31、32。通过阱24中的注入来形成P+类型的重掺杂接触阱34。
每个接触阱31、32、34都从对应半导体阱的表面向下延伸到对应的隐埋层。
在以下步骤中，如图3所示，在阱21-25的表面上沉积掩蔽光刻胶层40，然后根据光刻预建立的图案进行蚀刻，露出所述阱21和22的表面上的蚀刻点40’。
在蚀刻点40’的位置处，浅沟槽被蚀刻到阱21和22中。
P+类型的重掺杂半导体材料被沉积到沟槽中，在对应的阱21、22中形成场注入区域41、42，并且未来的JFET晶体管的两个栅极区域46位于阱21中。
因此，JFET晶体管的未来沟道区域ZC形成在两个栅极区域46之间，通过光刻来控制其有源表面D的临界尺寸。
确实，阱21中的掺杂物的横跨扩散与尺寸D相比可忽略，因此尺寸D精确地通过转印到光刻胶的图案的对应部分来确定。
此外，同时利用用于制造集成电路的NPN晶体管的步骤来形成沟道区域ZC。
图4示出了未示出的步骤的结果，其中，实施第二掩蔽以在具有N型的重掺杂材料的阱24内形成场注入区域44。
例如，根据LOCOS(“硅局部氧化”的首字母缩写)类型的已知方法，通过局部氧化50在阱21-25的表面上约束集成电路CI的有源区域。
执行掺杂物的注入，在阱22内形成分别为P-掺杂和P+型的重掺杂的本征基底区域52和本征基底区域62，并且在阱24内形成分别为N掺杂和N+型的重掺杂的本征基底区域54和本征基底区域64。
图5所示的以下步骤是对于JFET、PMOS和PNP晶体管来说公共的光刻步骤。
在阱21-25的表面上沉积光刻胶层70，其中也根据预建立的图案通过光刻形成的开口露出阱21、23和24的表面上的注入点70’。
P型的掺杂物以高密度注入并且到达这些注入点70’的浅深度，同时在对应的阱24、21和23内形成未来PNP晶体管的发射极74、未来JFET晶体管的栅极接触区域71以及未来PMOS晶体管的源极和漏极区域73。
图6所示的以下步骤是对于JFET、NPN和NMOS晶体管的形成来说公共的光刻步骤。
在阱21-25的表面上沉积光刻胶层80，其中，也根据预建立的图案通过光刻形成的开口露出阱21、22和25的表面上的注入点80’。
N型的掺杂物以高密度注入并到达这些注入点80’中的浅深度，同时形成未来NPN晶体管的发射极82、未来JFET晶体管的源极81以及未来NMOS晶体管的源极和漏极区域85。
图7示出了根据本实用新型的一个实施例得到的集成电路，其包括垂直结场效应晶体管T1、NPN类型的双极晶体管T2、PNP类型的双极晶体管T4、PMOS晶体管T3和NMOS晶体管T5。PMOS晶体管T3和NMOS晶体管T5的绝缘栅极以传统方式形成，并且包括绝缘层93(例如，氧化硅)和栅极材料层95(例如，多晶硅)。
用于接触形成的以下步骤(例如，包括固化步骤和接触沉积步骤)以传统方式执行并且没有示出。
图8示意性示出了在平面P2中以“顶视图”方式观察的图1所示晶体管T1的类型的JFET晶体管的单元结构架构。
单元结构SCEL包括多个单位单元CELi，并且每个单位单元CELi都包括JFET晶体管，尤其包括漏极区域31、两个栅极区域71和源极区域81。
对于每个单位单元已知和控制饱和漏极电流。因此，饱和漏极电流可以通过并联连接多个单位单元来调整为期望值。
然后，单元结构的饱和漏极电流等于并联连接的每个单位单元的饱和漏极电流的总和。
JFET晶体管的单元结构架构避免了必须制造更加扩展的JFET 晶体管以得到更高的饱和漏极电流，其中扩展的JFET晶体管显示出难以控制和建模的边缘效应。
明显地，本实用新型能够实现对本领域技术人员来说显而易见的多种变化和修改。具体地，本实用新型可通过反转对应的导电类型而应用于具有P型沟道的JFET的制造。

Claims (8)

1.一种集成电路，其特征在于，包括至少一个垂直结场效应晶体管(T1)，包括第一导电类型的半导体阱(21)、漏极区域、接触阱(31)、栅极区域(46)和源极区域(81)，其中所述漏极区域包括所述第一导电类型的比所述阱(21)更重掺杂的隐埋层(11)，所述接触阱为所述第一导电类型且从所述阱(21)的表面向下延伸到所述隐埋层(11)，所述栅极区域包括约束沟道区域(ZC)的填充有第二导电类型的半导体材料的两个沟槽，并且所述源极区域为所述第一导电类型且位于所述沟道区域(ZC)的顶部上。
2.根据权利要求1所述的集成电路，其特征在于，还包括：第一导电类型的至少一个双极晶体管(T2)、第二导电类型的至少一个双极晶体管(T4)、第一导电类型的至少一个绝缘栅型场效应晶体管(T5)和第二导电类型的至少一个绝缘栅型场效应晶体管(T3)。
3.根据权利要求2所述的集成电路，其特征在于，所述结场效应晶体管(T1)的所述隐埋层(11)和所述漏极接触阱(31)位于与双极晶体管(T2、T4)的集电极区域的隐埋层(12、14)和接触阱(32、34)相同的层级处。
4.根据权利要求2或3所述的集成电路，其特征在于，所述垂直结场效应晶体管(T1)的栅极区域(46)位于与所述双极晶体管(T2、T4)的场注入区域(42)相同的层级处。
5.根据权利要求2或3所述的集成电路，其特征在于，所述垂直结场效应晶体管(T1)的源极区域(81)位于与所述第一导电类型的双极晶体管(T2)的发射极区域(82)相同的层级处和/或与所述第一导电类型的绝缘栅型场效应晶体管(T5)的漏极/源极区域(85)相同的层级处。
6.根据权利要求2或3所述的集成电路，其特征在于，所述垂直结场效应晶体管(T1)包括栅极接触区域(71)，所述栅极接触区域为所述第二导电类型、与所述栅极区域(46)接触并且位于与所述第二导电类型的双极晶体管(T4)的发射极区域(74)相同的层级处和/或与所述第二导电类型的绝缘栅型场效应晶体管(T3)的漏极/源极区域(73)相同的层级处。
7.根据权利要求2或3所述的集成电路，其特征在于，包括多个垂直结场效应晶体管(T1)，各个垂直结场效应晶体管(T1)的沟道区域(ZC)具有根据晶体管不同的有源表面(D)的临界尺寸。
8.一种集成电路，其特征在于，包括形成单元结构的根据权利要求1至6中任一项所述的多个垂直结场效应晶体管(T1)。
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US10361188B2 (en) 2019-07-23
CN106898576A (zh) 2017-06-27

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