US20190296007A1 - Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit - Google Patents

Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit Download PDF

Info

Publication number
US20190296007A1
US20190296007A1 US16/436,289 US201916436289A US2019296007A1 US 20190296007 A1 US20190296007 A1 US 20190296007A1 US 201916436289 A US201916436289 A US 201916436289A US 2019296007 A1 US2019296007 A1 US 2019296007A1
Authority
US
United States
Prior art keywords
type
conductivity
integrated circuit
region
circuit according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/436,289
Inventor
Jean Jimenez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to US16/436,289 priority Critical patent/US20190296007A1/en
Publication of US20190296007A1 publication Critical patent/US20190296007A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8228—Complementary devices, e.g. complementary transistors
    • H01L21/82285—Complementary vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
    • H01L27/0826—Combination of vertical complementary transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H01L29/66909—Vertical transistors, e.g. tecnetrons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors

Definitions

  • JFET junction field-effect transistors
  • BiCMOS complementary metal-oxide-semiconductor
  • JFET transistors generally offer a low electrical noise at the output, and generally have a good high voltage performance.
  • JFET transistors are found in the input stages of precision operational amplifiers with a high input impedance.
  • Bipolar transistors exhibit a high gain, a high output impedance, and offer good performance at high frequencies, which allows them to be advantageously used, for example, in high-frequency analog amplifiers.
  • MOS transistors fabricated using a CMOS technology, generally exhibit a high input impedance and are notably used in logic circuits for digital electronics.
  • BiCMOS technology offers the advantages of the two types of technologies (bipolar and CMOS), and is advantageously used for applications with mixed signals (analog and digital).
  • the current JFET transistors are planar, having lateral junctions.
  • the pinch voltage of a JFET transistor is directly dependent on the geometry of the junction, and is notably determined by the critical dimension of the active surface of the channel.
  • the channel region of a planar JFET transistor is commonly formed by interleaved layers of doped semiconductor materials, forming an arrangement of the source, gate and drain regions of the JFET transistor.
  • the size of the channel of a planar JFET transistor notably its critical dimension of active surface, is determined by diffusions of dopants and is consequently difficult to control and adjust.
  • JFET transistors having pinch voltages that are different from one another requires additional masking and implantation steps.
  • a JFET transistor having a channel region whose channel critical dimension is better controlled.
  • a method is also provided for fabricating a JFET transistor within an integrated circuit of the BiCMOS type which does not include any step that is additional to a conventional method for fabricating integrated circuits of the BiCMOS type.
  • a method for fabricating an integrated circuit comprising the fabrication of at least one vertical junction field-effect transistor comprising the formation of a channel region having a critical dimension of active surface controlled by photolithography.
  • This method may comprise several simultaneous processes for fabrication of vertical junction field-effect transistors in which various critical dimensions of active surface of the channel region from one transistor to another are controlled during a common photolithography step.
  • the critical dimension of the active surface of the channel region exhibits a very low variability from one implementation of the method to another.
  • the pinch voltages of the transistors fabricated by this method therefore also exhibit a very low variability.
  • the vertical nature of the JFET transistor allows it to be easily inserted into a fabrication process of the CMOS type.
  • the formation of the channel region comprises the formation, in a semiconductor well of a first type of conductivity, of two gate regions of a second type of conductivity, the critical dimensions of active surface of the channel region being defined by the spacing between the two gate regions.
  • the fabrication of the vertical junction field-effect transistor may further comprise the formation of gate contact regions of the second type of conductivity in contact with the two gate regions.
  • the fabrication of the vertical junction field-effect transistor may further comprise the formation of a drain region comprising the formation under the well of a buried layer of the first type of conductivity, more highly doped than the well, and the formation of a contact well of the first type of conductivity and extending from the surface of the semiconductor well down to the buried layer.
  • the fabrication of the vertical junction field-effect transistor may further comprise the formation of a source region of the first type of conductivity in contact with the channel region.
  • One implementation of the method according to this aspect is also provided, which does not include any step additional to a conventional method for fabricating integrated circuits of the BiCMOS type.
  • the method further comprises the formation, in respective wells of the appropriate type of conductivity, of at least one bipolar transistor of a first type of conductivity, of at least one bipolar transistor of a second type of conductivity, of at least one insulated-gate field-effect transistor of a first type of conductivity and of at least one insulated-gate field-effect transistor of a second type of conductivity, formed simultaneously with the fabrication of the at least one vertical junction field-effect transistor.
  • Each step of the method for fabricating the vertical JFET transistor may be advantageously carried out simultaneously with a conventional step for fabricating a bipolar transistor of the N type (NPN) or of the P type (PNP) and/or with a conventional step for fabricating an insulated-gate field-effect transistor of the N type (NMOS) or of the P type (PMOS).
  • the method may comprise the formation of field implantation regions of the second type of conductivity within the wells of the bipolar transistors of the first type of conductivity, simultaneously with the formation the gate regions.
  • the method may comprise the formation of emitter regions of bipolar transistors of the second type of conductivity and/or of source/drain regions of insulated-gate field-effect transistors of the second type of conductivity, simultaneously with the formation of the gate contact regions of the JFET transistor.
  • the method may comprise the formation of a collector region of a bipolar transistor of the first type of conductivity comprising the formation of a buried layer of the first type of conductivity, more highly doped than the semiconductor well of the bipolar transistor, and the formation of a contact well of the first type of conductivity extending from the surface of the well of the bipolar transistor down to the buried layer, simultaneously with the formation of the drain region of the vertical junction field-effect transistor.
  • the method may comprise the formation of emitter regions of bipolar transistors of the first type of conductivity and/or of source/drain regions of insulated-gate field-effect transistors of the first type of conductivity, simultaneously with the formation of the source region of the vertical junction field-effect transistor.
  • emitter regions of a first or second type of conductivity, of source and drain regions of a first or of a second type of conductivity, and of collector regions of a first type of conductivity comprising a contact well and a buried layer are conventional steps of the methods for fabricating integrated circuits of the BiCMOS type.
  • an integrated circuit is provided with at least one vertical junction field-effect transistor, comprising a semiconductor well of a first type of conductivity, a drain region comprising a buried layer of the first type of conductivity, more highly doped than the well, and a contact well of the first type of conductivity extending from the surface of the well down to the buried layer, a gate region comprising two trenches filled with a semiconductor material of a second type of conductivity bounding a channel region, and a source region of the first type of conductivity on top of the channel region.
  • the integrated circuit may further comprise at least one bipolar transistor of a first type of conductivity and at least one bipolar transistor of a second type of conductivity, at least one insulated-gate field-effect transistor of a first type of conductivity and at least one insulated-gate field-effect transistor of a second type of conductivity.
  • the buried layer and the drain contact well of the junction field-effect transistor can be at the same levels as buried layers and contact wells of the collector regions of the bipolar transistors.
  • the gate region of the junction field-effect transistor can be at the same level as field implantation regions of bipolar transistors of the first type of conductivity.
  • the source region of the junction field-effect transistor can be at the same level as emitter regions of bipolar transistors of the first type of conductivity and/or at the same level as drain/source regions of insulated-gate field-effect transistors of the first type of conductivity.
  • the junction field-effect transistor may comprise gate contact regions of the second type of conductivity in contact with the gate regions, and which can be situated at the same level as emitter regions of bipolar transistors of the second type.
  • the integrated circuit comprises a plurality of vertical junction field-effect transistors, the various junction field-effect transistors having channel regions with critical dimensions of active surface different from one transistor to another.
  • the integrated circuit may comprise a plurality of junction field-effect transistors forming a cellular structure.
  • FIG. 1 illustrates one example of a vertical junction field-effect transistor forming part of an integrated circuit
  • FIGS. 2-7 illustrate steps of one example of a method for fabricating an integrated circuit
  • FIG. 8 schematically shows a cellular structure architecture for JFET transistors.
  • FIGS. 1 to 8 are shown schematically and are not to scale, the common elements from one figure to another being denoted using the same references.
  • the first type of conductivity will be denoted as being the N type and the second type of conductivity as being the P type, even though the reverse is also possible according to the invention.
  • FIG. 1 illustrates one example of a vertical junction field-effect transistor T 1 , forming part of an integrated circuit CI formed on a semiconductor substrate 10 with P-type doping.
  • This transistor T 1 is notably fabricated within a semiconductor well 21 with N-type doping and comprises a drain region, a source region 81 , a gate region 46 , and a channel region ZC.
  • the drain region comprises a buried layer 11 of the N + type, more highly doped than the well 21 , and a contact well 31 also highly-doped of the N + type.
  • the contact well 31 extends from the surface of the well 21 down to the buried layer 11 .
  • the gate region 46 comprises two neighboring vertical trenches filled with a highly-doped semiconductor material of the P + type. These trenches bound the vertical channel region ZC between them. The distance D between these trenches defines the critical dimension of active surface of the channel of the transistor.
  • Highly-doped gate contact regions 71 of the P type are disposed on the surface of the well 21 and in contact with the gate regions 46 .
  • the highly-doped source region 81 of the N + type is formed on top of the channel region ZC, also on the surface of the well 21 .
  • local regions of oxidation 50 are formed between the gate contact regions 71 and the source region 81 and between the gate contact regions 71 and the drain contact well 31 , in order to insulate these regions from one another.
  • local regions of oxidation 50 are formed at the lateral ends of the surface of the well in order to insulate the transistor T 1 from the rest of the integrated circuit CI of which it forms a part.
  • These regions 50 may be of the LOCOS type or else shallow trenches (STI: Shallow Trench Isolation).
  • FIG. 2 illustrates the result of initial steps of one example of a method for fabricating an integrated circuit CI.
  • the integrated circuit CI here comprises five regions Z 1 , Z 2 , Z 3 , Z 4 , and Z 5 , bounded in the following figures by dashed lines, in which a JFET transistor T 1 , a bipolar transistor of the NPN type T 2 , an insulated-gate field-effect transistor of the PMOS type T 3 , a bipolar transistor of the PNP type T 4 and an insulated-gate field-effect effect transistor of the NMOS type T 5 will respectively be fabricated according to one embodiment of the invention.
  • highly-doped buried layers 11 , 12 , 13 of the N + type have been formed by shallow implantation in the respective regions Z 1 , Z 2 , Z 3 of the substrate 10 .
  • Semiconductor wells 21 , 22 , 23 with N-type doping have been formed by epitaxy on top of these buried layers 11 , 12 , 13 , respectively.
  • highly-doped buried layers 14 , 15 of the P + type have been formed by shallow implantation in the respective regions Z 4 , Z 5 , on which wells with n-type doping have been formed by epitaxy, then respectively converted into wells 24 , 25 with P-type doping by ion implantation and diffusion of the dopants.
  • Highly-doped contact wells 31 , 32 of the N + type have also been formed by implantation into the wells 21 , 22 .
  • a highly-doped contact well 34 of the P + type has been formed by implantation into the well 24 .
  • Each contact well 31 , 32 , 34 extends from the surface of the respective semiconductor well down to the respective buried layer.
  • a layer of masking resist 40 is deposited on the surface of the wells 21 to 25 then etched according to a pattern pre-established by photolithography, exposing etch sites 40 ′ on the surface of the wells 21 and 22 .
  • Shallow trenches are etched into the wells 21 and 22 at the location of the etch sites 40 ′.
  • a highly-doped semiconductor material of the P + type is deposited into the trenches, forming field implantation regions 41 , 42 in the respective wells 21 , 22 , and two gate regions 46 of the future JFET transistor in the well 21 .
  • the future channel region ZC of the JFET transistor has thus been formed between the two gate regions 46 , whose critical dimension of active surface D is controlled by photolithography.
  • the lateral diffusion of the dopants in the well 21 is negligible compared with the dimension D and thus the dimension D is precisely determined by the corresponding part of the pattern transferred onto the resist.
  • channel region ZC has been formed simultaneously with steps for fabrication of the NPN transistors of the integrated circuit.
  • FIG. 4 illustrates the result of steps not shown, amongst which a second masking has been implemented in order to form field implantation regions 44 within the well 24 with a highly-doped material of the N type.
  • Active regions of the integrated circuit CI have been bounded by local oxidations 50 on the surface of the wells 21 to 25 , for example according to a known method of the LOCOS type (acronym coming from “LOCal Oxidation of Silicon”).
  • Implantations of dopants have also been carried out, forming an intrinsic base region 52 and an extrinsic base region 62 respectively P-doped and highly-doped of the P + type within the well 22 , and an intrinsic base region 54 and an extrinsic base region 64 respectively doped N and highly-doped of the N + type within the well 24 .
  • the following step, shown in FIG. 5 is a photolithography step common to all the formations of the JFET, PMOS and PNP transistors.
  • a layer 70 of resist is deposited onto the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 70 ′ on the surfaces of the wells 21 , 23 and 24 .
  • a dopant of the P type is implanted at high density and to a shallow depth into these implantation sites 70 ′, simultaneously forming an emitter 74 of the future PNP transistor, the gate contact regions 71 of the future JFET transistor, and the source and drain regions 73 of the future PMOS transistor, within the corresponding wells 24 , 21 and 23 .
  • the following step, shown in FIG. 6 is a photolithography step common to the formations of the JFET, NPN and NMOS transistors.
  • a layer 80 of resist is deposited on the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 80 ′ on the surface of the wells 21 , 22 and 25 .
  • a dopant of the N type is implanted at high density and to a shallow depth into these implantation sites 80 ′, simultaneously forming an emitter 82 of the future transistor NPN, the source 81 of the future JFET transistor, and the source and drain regions 85 of the future NMOS transistor.
  • FIG. 7 shows an integrated circuit obtained according to one embodiment, comprising a vertical junction field-effect transistor T 1 , a bipolar transistor of the NPN type T 2 , a bipolar transistor of the PNP type T 4 , a PMOS transistor T 3 and an NMOS transistor T 5 .
  • the insulated gates of the PMOS transistor T 3 and NMOS transistor T 5 have been formed in a conventional manner and comprise an insulating layer 93 , for example of silicon oxide, and a layer of gate material 95 , for example polycrystalline silicon.
  • steps for contact formation including for example steps for silicidation and for deposition of contacts, are carried out in a conventional manner and are not shown.
  • FIG. 8 shows schematically a cellular structure architecture for JFET transistors of the type of the transistor T 1 shown in FIG. 1 , in the plane P 2 , seen as “a top view”.
  • the cellular structure SCEL comprises several unitary cells CEL i , and each unitary cell CEL i , comprises a JFET transistor notably comprising a drain region 31 , two gate contact regions 71 and a source region 81 .
  • the saturation drain current is known and controlled for each unitary cell.
  • a saturation drain current may be adjusted to a desired value by connecting several unitary cells in parallel.
  • the saturation drain current of the cellular structure is then equal to the sum of the saturation drain currents of each unitary cell connected in parallel.
  • JFET transistors avoids having to fabricate the JFET transistors that are more extended in order to obtain a higher saturation drain current, extended JFET transistors exhibiting edge effects that are difficult to control and to model.
  • the present invention is capable of several variants and modifications which will be apparent to those skilled in the art.
  • the invention may be applied to the fabrication of a JFET transistor with a channel of the P type by reversing the corresponding types of conductivity.

Abstract

An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography. A gate region of the transistor is formed by two spaced apart first trenches in that are filled with a doped semiconductor material, wherein the two spaced apart first trenches bound the channel region and set the critical dimension.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 15/133,595 filed Apr. 20, 2016, which claims priority from French Application for Patent No. 1562956 filed Dec. 21, 2015, the disclosures of which are incorporated by reference.
    • TECHNICAL FIELD
  • Various embodiments and their implementation relate to integrated circuits, in particular the fabrication of junction field-effect transistors (JFET) within a semiconductor substrate adapted to bipolar technologies and CMOS technologies (BiCMOS).
    • BACKGROUND
  • JFET transistors generally offer a low electrical noise at the output, and generally have a good high voltage performance. For example, JFET transistors are found in the input stages of precision operational amplifiers with a high input impedance.
  • Bipolar transistors exhibit a high gain, a high output impedance, and offer good performance at high frequencies, which allows them to be advantageously used, for example, in high-frequency analog amplifiers.
  • On the other hand, MOS transistors, fabricated using a CMOS technology, generally exhibit a high input impedance and are notably used in logic circuits for digital electronics.
  • BiCMOS technology offers the advantages of the two types of technologies (bipolar and CMOS), and is advantageously used for applications with mixed signals (analog and digital).
  • However, the methods for fabricating electronic circuits of the BiCMOS type must satisfy the production constraints of both bipolar and CMOS technologies, notably owing to the different individual steps between the two technologies.
  • Currently, the integration of JFET transistors into a BiCMOS integrated circuit involves the introduction of additional steps into fabrication methods already subject to significant constraints, leading to drawbacks of cost.
  • Furthermore, the current JFET transistors are planar, having lateral junctions.
  • The pinch voltage of a JFET transistor is directly dependent on the geometry of the junction, and is notably determined by the critical dimension of the active surface of the channel.
  • The channel region of a planar JFET transistor is commonly formed by interleaved layers of doped semiconductor materials, forming an arrangement of the source, gate and drain regions of the JFET transistor.
  • Thus, the size of the channel of a planar JFET transistor, notably its critical dimension of active surface, is determined by diffusions of dopants and is consequently difficult to control and adjust.
  • Furthermore, within the same process for production of planar JFET transistors, forming JFET transistors having pinch voltages that are different from one another requires additional masking and implantation steps.
    • SUMMARY
  • According to one embodiment, a JFET transistor is provided having a channel region whose channel critical dimension is better controlled.
  • According to one embodiment, a method is also provided for fabricating a JFET transistor within an integrated circuit of the BiCMOS type which does not include any step that is additional to a conventional method for fabricating integrated circuits of the BiCMOS type.
  • According to one aspect, a method is provided for fabricating an integrated circuit comprising the fabrication of at least one vertical junction field-effect transistor comprising the formation of a channel region having a critical dimension of active surface controlled by photolithography.
  • This method may comprise several simultaneous processes for fabrication of vertical junction field-effect transistors in which various critical dimensions of active surface of the channel region from one transistor to another are controlled during a common photolithography step.
  • Since the conventional and known photolithography processes are well controlled, precise and reproducible, the critical dimension of the active surface of the channel region exhibits a very low variability from one implementation of the method to another. The pinch voltages of the transistors fabricated by this method therefore also exhibit a very low variability.
  • Furthermore, photolithographic processes are common steps in the methods for fabricating electronic circuits and are easily modifiable. Thus, according to this aspect, it is possible to fabricate several JFET transistors whose pinch voltages are different during the implementation of the same method, without any additional process step or time.
  • Furthermore, the vertical nature of the JFET transistor allows it to be easily inserted into a fabrication process of the CMOS type.
  • According to one embodiment of the method, the formation of the channel region comprises the formation, in a semiconductor well of a first type of conductivity, of two gate regions of a second type of conductivity, the critical dimensions of active surface of the channel region being defined by the spacing between the two gate regions.
  • The fabrication of the vertical junction field-effect transistor may further comprise the formation of gate contact regions of the second type of conductivity in contact with the two gate regions.
  • The fabrication of the vertical junction field-effect transistor may further comprise the formation of a drain region comprising the formation under the well of a buried layer of the first type of conductivity, more highly doped than the well, and the formation of a contact well of the first type of conductivity and extending from the surface of the semiconductor well down to the buried layer.
  • The fabrication of the vertical junction field-effect transistor may further comprise the formation of a source region of the first type of conductivity in contact with the channel region.
  • One implementation of the method according to this aspect is also provided, which does not include any step additional to a conventional method for fabricating integrated circuits of the BiCMOS type.
  • According to this embodiment, the method further comprises the formation, in respective wells of the appropriate type of conductivity, of at least one bipolar transistor of a first type of conductivity, of at least one bipolar transistor of a second type of conductivity, of at least one insulated-gate field-effect transistor of a first type of conductivity and of at least one insulated-gate field-effect transistor of a second type of conductivity, formed simultaneously with the fabrication of the at least one vertical junction field-effect transistor.
  • Each step of the method for fabricating the vertical JFET transistor may be advantageously carried out simultaneously with a conventional step for fabricating a bipolar transistor of the N type (NPN) or of the P type (PNP) and/or with a conventional step for fabricating an insulated-gate field-effect transistor of the N type (NMOS) or of the P type (PMOS).
  • The method may comprise the formation of field implantation regions of the second type of conductivity within the wells of the bipolar transistors of the first type of conductivity, simultaneously with the formation the gate regions.
  • Indeed, integrated circuits of the BiCMOS type, for example present on an input stage of a high-voltage operational amplifier, must occasionally withstand voltages of the order of 40 volts. Implementing field implantations formed by trenches filled with a highly-doped material allows the field lines to be spread out further away from the active junctions and thus the voltage capability of the components of the integrated circuit to be improved.
  • The method may comprise the formation of emitter regions of bipolar transistors of the second type of conductivity and/or of source/drain regions of insulated-gate field-effect transistors of the second type of conductivity, simultaneously with the formation of the gate contact regions of the JFET transistor.
  • The method may comprise the formation of a collector region of a bipolar transistor of the first type of conductivity comprising the formation of a buried layer of the first type of conductivity, more highly doped than the semiconductor well of the bipolar transistor, and the formation of a contact well of the first type of conductivity extending from the surface of the well of the bipolar transistor down to the buried layer, simultaneously with the formation of the drain region of the vertical junction field-effect transistor.
  • The method may comprise the formation of emitter regions of bipolar transistors of the first type of conductivity and/or of source/drain regions of insulated-gate field-effect transistors of the first type of conductivity, simultaneously with the formation of the source region of the vertical junction field-effect transistor.
  • The formation of emitter regions of a first or second type of conductivity, of source and drain regions of a first or of a second type of conductivity, and of collector regions of a first type of conductivity comprising a contact well and a buried layer, are conventional steps of the methods for fabricating integrated circuits of the BiCMOS type.
  • The fabrication of the JFET transistor does not introduce in this respect any additional step with respect to a conventional method.
  • According to another aspect, an integrated circuit is provided with at least one vertical junction field-effect transistor, comprising a semiconductor well of a first type of conductivity, a drain region comprising a buried layer of the first type of conductivity, more highly doped than the well, and a contact well of the first type of conductivity extending from the surface of the well down to the buried layer, a gate region comprising two trenches filled with a semiconductor material of a second type of conductivity bounding a channel region, and a source region of the first type of conductivity on top of the channel region.
  • The integrated circuit may further comprise at least one bipolar transistor of a first type of conductivity and at least one bipolar transistor of a second type of conductivity, at least one insulated-gate field-effect transistor of a first type of conductivity and at least one insulated-gate field-effect transistor of a second type of conductivity.
  • The buried layer and the drain contact well of the junction field-effect transistor can be at the same levels as buried layers and contact wells of the collector regions of the bipolar transistors.
  • The gate region of the junction field-effect transistor can be at the same level as field implantation regions of bipolar transistors of the first type of conductivity.
  • The source region of the junction field-effect transistor can be at the same level as emitter regions of bipolar transistors of the first type of conductivity and/or at the same level as drain/source regions of insulated-gate field-effect transistors of the first type of conductivity.
  • The junction field-effect transistor may comprise gate contact regions of the second type of conductivity in contact with the gate regions, and which can be situated at the same level as emitter regions of bipolar transistors of the second type.
  • According to one embodiment, the integrated circuit comprises a plurality of vertical junction field-effect transistors, the various junction field-effect transistors having channel regions with critical dimensions of active surface different from one transistor to another.
  • The integrated circuit may comprise a plurality of junction field-effect transistors forming a cellular structure.
  • Using cellular structure architectures avoids constraining and unpredictable edge effects appearing in extended JFET transistors.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other advantages and features of the invention will become apparent upon examining the detailed description of non-limiting embodiments and their implementation and from the appended drawings in which:
  • FIG. 1 illustrates one example of a vertical junction field-effect transistor forming part of an integrated circuit;
  • FIGS. 2-7 illustrate steps of one example of a method for fabricating an integrated circuit; and
  • FIG. 8 schematically shows a cellular structure architecture for JFET transistors.
    •  DETAILED DESCRIPTION
  • For the sake of clarity, as is common in the representation of integrated circuits, FIGS. 1 to 8 are shown schematically and are not to scale, the common elements from one figure to another being denoted using the same references.
  • Furthermore, in the following, the first type of conductivity will be denoted as being the N type and the second type of conductivity as being the P type, even though the reverse is also possible according to the invention.
  • FIG. 1 illustrates one example of a vertical junction field-effect transistor T1, forming part of an integrated circuit CI formed on a semiconductor substrate 10 with P-type doping. This transistor T1 is notably fabricated within a semiconductor well 21 with N-type doping and comprises a drain region, a source region 81, a gate region 46, and a channel region ZC.
  • The drain region comprises a buried layer 11 of the N+ type, more highly doped than the well 21, and a contact well 31 also highly-doped of the N+ type. The contact well 31 extends from the surface of the well 21 down to the buried layer 11.
  • The gate region 46 comprises two neighboring vertical trenches filled with a highly-doped semiconductor material of the P+ type. These trenches bound the vertical channel region ZC between them. The distance D between these trenches defines the critical dimension of active surface of the channel of the transistor.
  • Highly-doped gate contact regions 71 of the P type are disposed on the surface of the well 21 and in contact with the gate regions 46.
  • The highly-doped source region 81 of the N+ type is formed on top of the channel region ZC, also on the surface of the well 21.
  • Furthermore, local regions of oxidation 50 are formed between the gate contact regions 71 and the source region 81 and between the gate contact regions 71 and the drain contact well 31, in order to insulate these regions from one another. Similarly, local regions of oxidation 50 are formed at the lateral ends of the surface of the well in order to insulate the transistor T1 from the rest of the integrated circuit CI of which it forms a part.
  • These regions 50 may be of the LOCOS type or else shallow trenches (STI: Shallow Trench Isolation).
  • FIG. 2 illustrates the result of initial steps of one example of a method for fabricating an integrated circuit CI. The integrated circuit CI here comprises five regions Z1, Z2, Z3, Z4, and Z5, bounded in the following figures by dashed lines, in which a JFET transistor T1, a bipolar transistor of the NPN type T2, an insulated-gate field-effect transistor of the PMOS type T3, a bipolar transistor of the PNP type T4 and an insulated-gate field-effect effect transistor of the NMOS type T5 will respectively be fabricated according to one embodiment of the invention.
  • Within a substrate 10 of silicon with P-type doping, highly-doped buried layers 11, 12, 13 of the N+ type have been formed by shallow implantation in the respective regions Z1, Z2, Z3 of the substrate 10. Semiconductor wells 21, 22, 23 with N-type doping have been formed by epitaxy on top of these buried layers 11, 12, 13, respectively.
  • Similarly, highly-doped buried layers 14, 15 of the P+ type have been formed by shallow implantation in the respective regions Z4, Z5, on which wells with n-type doping have been formed by epitaxy, then respectively converted into wells 24, 25 with P-type doping by ion implantation and diffusion of the dopants.
  • Highly-doped contact wells 31, 32 of the N+ type have also been formed by implantation into the wells 21, 22. A highly-doped contact well 34 of the P+ type has been formed by implantation into the well 24.
  • Each contact well 31, 32, 34 extends from the surface of the respective semiconductor well down to the respective buried layer.
  • In the following step, illustrated by FIG. 3, a layer of masking resist 40 is deposited on the surface of the wells 21 to 25 then etched according to a pattern pre-established by photolithography, exposing etch sites 40′ on the surface of the wells 21 and 22.
  • Shallow trenches are etched into the wells 21 and 22 at the location of the etch sites 40′.
  • A highly-doped semiconductor material of the P+ type is deposited into the trenches, forming field implantation regions 41, 42 in the respective wells 21, 22, and two gate regions 46 of the future JFET transistor in the well 21.
  • The future channel region ZC of the JFET transistor has thus been formed between the two gate regions 46, whose critical dimension of active surface D is controlled by photolithography.
  • Indeed, the lateral diffusion of the dopants in the well 21 is negligible compared with the dimension D and thus the dimension D is precisely determined by the corresponding part of the pattern transferred onto the resist.
  • Furthermore, the channel region ZC has been formed simultaneously with steps for fabrication of the NPN transistors of the integrated circuit.
  • FIG. 4 illustrates the result of steps not shown, amongst which a second masking has been implemented in order to form field implantation regions 44 within the well 24 with a highly-doped material of the N type.
  • Active regions of the integrated circuit CI have been bounded by local oxidations 50 on the surface of the wells 21 to 25, for example according to a known method of the LOCOS type (acronym coming from “LOCal Oxidation of Silicon”).
  • Implantations of dopants have also been carried out, forming an intrinsic base region 52 and an extrinsic base region 62 respectively P-doped and highly-doped of the P+ type within the well 22, and an intrinsic base region 54 and an extrinsic base region 64 respectively doped N and highly-doped of the N+ type within the well 24.
  • The following step, shown in FIG. 5, is a photolithography step common to all the formations of the JFET, PMOS and PNP transistors.
  • A layer 70 of resist is deposited onto the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 70′ on the surfaces of the wells 21, 23 and 24.
  • A dopant of the P type is implanted at high density and to a shallow depth into these implantation sites 70′, simultaneously forming an emitter 74 of the future PNP transistor, the gate contact regions 71 of the future JFET transistor, and the source and drain regions 73 of the future PMOS transistor, within the corresponding wells 24, 21 and 23.
  • The following step, shown in FIG. 6, is a photolithography step common to the formations of the JFET, NPN and NMOS transistors.
  • A layer 80 of resist is deposited on the surface of the wells 21 to 25 in which openings, also formed by photolithography according to a pre-established pattern, expose implantation sites 80′ on the surface of the wells 21, 22 and 25.
  • A dopant of the N type is implanted at high density and to a shallow depth into these implantation sites 80′, simultaneously forming an emitter 82 of the future transistor NPN, the source 81 of the future JFET transistor, and the source and drain regions 85 of the future NMOS transistor.
  • FIG. 7 shows an integrated circuit obtained according to one embodiment, comprising a vertical junction field-effect transistor T1, a bipolar transistor of the NPN type T2, a bipolar transistor of the PNP type T4, a PMOS transistor T3 and an NMOS transistor T5. The insulated gates of the PMOS transistor T3 and NMOS transistor T5 have been formed in a conventional manner and comprise an insulating layer 93, for example of silicon oxide, and a layer of gate material 95, for example polycrystalline silicon.
  • The following steps for contact formation, including for example steps for silicidation and for deposition of contacts, are carried out in a conventional manner and are not shown.
  • FIG. 8 shows schematically a cellular structure architecture for JFET transistors of the type of the transistor T1 shown in FIG. 1, in the plane P2, seen as “a top view”.
  • The cellular structure SCEL comprises several unitary cells CELi, and each unitary cell CELi, comprises a JFET transistor notably comprising a drain region 31, two gate contact regions 71 and a source region 81.
  • The saturation drain current is known and controlled for each unitary cell. Thus, a saturation drain current may be adjusted to a desired value by connecting several unitary cells in parallel.
  • The saturation drain current of the cellular structure is then equal to the sum of the saturation drain currents of each unitary cell connected in parallel.
  • The cellular structure architecture of JFET transistors avoids having to fabricate the JFET transistors that are more extended in order to obtain a higher saturation drain current, extended JFET transistors exhibiting edge effects that are difficult to control and to model.
  • It is clear that the present invention is capable of several variants and modifications which will be apparent to those skilled in the art. In particular, the invention may be applied to the fabrication of a JFET transistor with a channel of the P type by reversing the corresponding types of conductivity.

Claims (18)

1. An integrated circuit, including at least one vertical junction field-effect transistor, comprising:
a semiconductor well of a first type of conductivity;
a drain region comprising a buried layer of the first type of conductivity having a doping level that is higher than a doping level of the semiconductor well;
a contact well of the first type of conductivity that extends from a surface of the semiconductor well down to the buried layer;
a gate region comprising two spaced apart first trenches in that are filled with a semiconductor material of a second type of conductivity, said two spaced apart first trenches bounding a channel region; and
a source region of the first type of conductivity on top of the semiconductor well at an active surface of the channel region.
2. The integrated circuit according to claim 1, further comprising a field implantation region comprising two spaced apart second trenches that are filled with a semiconductor material of a second type of conductivity, said two spaced apart second trenches being separated from the two spaced apart first trenches by a portion of the semiconductor well.
3. The integrated circuit according to claim 2, further comprising contact regions of the second type of conductivity on top of the semiconductor well, said contact regions making electrical contact to the semiconductor material of the second conductivity type present in the two spaced apart first trenches for the gate region and the two spaced apart second trenches of the field implantation region.
4. The integrated circuit according to claim 3, further comprising an isolation region at the top of the semiconductor well for isolating the contact regions of the second type of conductivity from the source region of the first type of conductivity.
5. The integrated circuit according to claim 4, wherein the isolation region is a LOCOS region.
6. The integrated circuit according to claim 4, wherein the isolation region is a trench isolation region.
7. The integrated circuit according to claim 1, further comprising contact regions of the second type of conductivity on top of the semiconductor well, said contact regions making electrical contact to the semiconductor material of the second conductivity type present in the two spaced apart first trenches for the gate region.
8. The integrated circuit according to claim 7, further comprising an isolation region at the top of the semiconductor well for isolating the contact regions of the second type of conductivity from the source region of the first type of conductivity.
9. The integrated circuit according to claim 8, wherein the isolation region is a LOCOS region.
10. The integrated circuit according to claim 8, wherein the isolation region is a trench isolation region.
11. The integrated circuit according to claim 1, wherein a distance between inner edges of the two spaced apart first trenches defines a critical dimension of the active surface of the channel region in contact with the source region of the first type of conductivity.
12. The integrated circuit according to claim 1, further comprising at least one bipolar transistor of the first type of conductivity, at least one bipolar transistor of the second type of conductivity, at least one insulated-gate field-effect transistor of the first type of conductivity and at least one insulated-gate field-effect transistor of the second type of conductivity.
13. The integrated circuit according to claim 12, wherein the buried layer and the contact well of the junction field-effect transistor are at a same level as buried layers and contact wells of collector regions of the bipolar transistor of the first type of conductivity and bipolar transistor of the second type of conductivity.
14. The integrated circuit according to claim 12, wherein the gate region of the vertical junction field-effect transistor is at a same level as field implantation regions of the bipolar transistor of the first type of conductivity and bipolar transistor of the second type of conductivity.
15. The integrated circuit according to claim 12, wherein the source region of the vertical junction field-effect transistor is at a same level as emitter regions of the bipolar transistor of the first type of conductivity and drain and source regions of insulated-gate field-effect transistor of the first type of conductivity.
16. The integrated circuit according to claim 12, wherein the vertical junction field-effect transistor comprises gate contact regions of the second type of conductivity in contact with the gate regions, said gate contact regions at a same level as emitter regions of the bipolar transistor of the second type of conductivity and drain and source regions of the insulated-gate field-effect transistor of the second type of conductivity.
17. The integrated circuit according to claim 1, wherein said at least one vertical junction field-effect transistor comprises a plurality of vertical junction field-effect transistors, wherein first ones of the plurality of vertical junction field-effect transistors have channel regions with critical dimensions of active surface different from second ones of the plurality of vertical junction field-effect transistors.
18. The integrated circuit according to claim 1, wherein said at least one vertical junction field-effect transistor comprises a plurality of vertical junction field-effect transistors, wherein the plurality of vertical junction field-effect transistors form a cellular structure.
US16/436,289 2015-12-21 2019-06-10 Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit Abandoned US20190296007A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/436,289 US20190296007A1 (en) 2015-12-21 2019-06-10 Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR1562956A FR3045937A1 (en) 2015-12-21 2015-12-21 METHOD FOR MANUFACTURING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT.
FR1562956 2015-12-21
US15/133,595 US10361188B2 (en) 2015-12-21 2016-04-20 Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit
US16/436,289 US20190296007A1 (en) 2015-12-21 2019-06-10 Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US15/133,595 Division US10361188B2 (en) 2015-12-21 2016-04-20 Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit

Publications (1)

Publication Number Publication Date
US20190296007A1 true US20190296007A1 (en) 2019-09-26

Family

ID=55300696

Family Applications (2)

Application Number Title Priority Date Filing Date
US15/133,595 Active 2037-01-02 US10361188B2 (en) 2015-12-21 2016-04-20 Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit
US16/436,289 Abandoned US20190296007A1 (en) 2015-12-21 2019-06-10 Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US15/133,595 Active 2037-01-02 US10361188B2 (en) 2015-12-21 2016-04-20 Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit

Country Status (4)

Country Link
US (2) US10361188B2 (en)
EP (1) EP3185288A1 (en)
CN (2) CN205845961U (en)
FR (1) FR3045937A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3045937A1 (en) * 2015-12-21 2017-06-23 St Microelectronics Crolles 2 Sas METHOD FOR MANUFACTURING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT.
US20190273169A1 (en) * 2018-03-01 2019-09-05 Semiconductor Components Industries, Llc Electronic device including a junction field-effect transistor having a gate within a well region and a process of forming the same
US10818662B2 (en) * 2018-09-19 2020-10-27 Alpha And Omega Semiconductor (Cayman) Ltd. Silicon carbide MOSFET with source ballasting
CN110534513B (en) * 2019-09-06 2022-02-08 电子科技大学 High-low voltage integrated device and manufacturing method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53135249A (en) * 1977-04-30 1978-11-25 Nippon Gakki Seizo Kk Logic circuit system for integration
JPS5425175A (en) * 1977-07-27 1979-02-24 Nippon Gakki Seizo Kk Integrated circuit device
US4546370A (en) * 1979-02-15 1985-10-08 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
US4403395A (en) * 1979-02-15 1983-09-13 Texas Instruments Incorporated Monolithic integration of logic, control and high voltage interface circuitry
US4325180A (en) * 1979-02-15 1982-04-20 Texas Instruments Incorporated Process for monolithic integration of logic, control, and high voltage interface circuitry
JPS62196360U (en) * 1986-06-05 1987-12-14
DE3916707A1 (en) * 1988-07-06 1990-01-11 Halbleiterwerk Frankfurt Oder Semiconductor arrangement for an integrated circuit and method of production thereof
US5302534A (en) * 1992-03-02 1994-04-12 Motorola, Inc. Forming a vertical PNP transistor
US6861303B2 (en) * 2003-05-09 2005-03-01 Texas Instruments Incorporated JFET structure for integrated circuit and fabrication method
US7164160B2 (en) * 2003-09-29 2007-01-16 Texas Instruments Incorporated Integrated circuit device with a vertical JFET
DE102005023891B4 (en) * 2004-05-24 2009-08-27 DENSO CORPORATION, Kariya-shi A method of manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device
US7642617B2 (en) * 2005-09-28 2010-01-05 Agere Systems Inc. Integrated circuit with depletion mode JFET
JP2013243272A (en) * 2012-05-22 2013-12-05 Sumitomo Electric Ind Ltd Silicon carbide semiconductor device and manufacturing method of the same
US10269658B2 (en) * 2012-06-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit devices with well regions and methods for forming the same
US9064887B2 (en) * 2012-09-04 2015-06-23 Infineon Technologies Austria Ag Field-effect semiconductor device and manufacturing method therefor
CN102931191B (en) * 2012-10-31 2016-03-02 成都芯源系统有限公司 Semiconductor device and method for manufacturing the same
CN103840012A (en) * 2012-11-22 2014-06-04 无锡华润上华半导体有限公司 Junction field-effect transistor (JFET) and preparation method thereof
US9666586B2 (en) * 2014-08-14 2017-05-30 Gil Asa CMOS compatible memory cells
FR3045937A1 (en) * 2015-12-21 2017-06-23 St Microelectronics Crolles 2 Sas METHOD FOR MANUFACTURING A JFET TRANSISTOR WITHIN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT.

Also Published As

Publication number Publication date
CN205845961U (en) 2016-12-28
FR3045937A1 (en) 2017-06-23
CN106898576B (en) 2021-06-29
CN106898576A (en) 2017-06-27
EP3185288A1 (en) 2017-06-28
US20170179113A1 (en) 2017-06-22
US10361188B2 (en) 2019-07-23

Similar Documents

Publication Publication Date Title
US20190296007A1 (en) Method for fabricating a jfet transistor within an integrated circuit and corresponding integrated circuit
US8836043B2 (en) Lateral bipolar junction transistor
KR100564890B1 (en) Manufacture of Bipolar / CMOS Integrated Circuits
US7095094B2 (en) Multiple doping level bipolar junctions transistors and method for forming
US8304308B2 (en) Configuration and fabrication of semiconductor structure having bipolar junction transistor in which non-monocrystalline semiconductor spacing portion controls base-link length
US7897995B2 (en) Lateral bipolar junction transistor with reduced base resistance
US8482081B2 (en) Semiconductor apparatus and manufacturing method thereof
US7932581B2 (en) Lateral bipolar junction transistor
JPH104198A (en) On-silicon semiconductor transistor with hollow injections
JPH05243584A (en) Manufacturing method of insulating vertical pnp transistor equipped with eeprom memory in complementary bicmos process
US7576406B2 (en) Semiconductor device
US6303420B1 (en) Integrated bipolar junction transistor for mixed signal circuits
US7968417B2 (en) Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure
KR100511024B1 (en) Semiconductor device applicable to variable capacitance condenser and amplifier
US6359317B1 (en) Vertical PNP bipolar transistor and its method of fabrication
JP3186043B2 (en) Method for manufacturing semiconductor device
JP2001237249A (en) Semiconductor device and its manufacturing method
US6881976B1 (en) Heterojunction BiCMOS semiconductor
US6150225A (en) Method for fabricating a semiconductor device having vertical and lateral type bipolar transistors
JP3902412B2 (en) Manufacturing method of semiconductor device
JP2011528187A (en) Transistor device and manufacturing method thereof
JP2003174100A (en) Semiconductor device and method of manufacturing the same
JP2009212362A (en) Manufacturing method of semiconductor device
JPH0479363A (en) Semiconductor substrate and semiconductor integrated circuit device

Legal Events

Date Code Title Description
STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION