CN103840012A - Junction field-effect transistor (JFET) and preparation method thereof - Google Patents
Junction field-effect transistor (JFET) and preparation method thereof Download PDFInfo
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- CN103840012A CN103840012A CN201210477888.9A CN201210477888A CN103840012A CN 103840012 A CN103840012 A CN 103840012A CN 201210477888 A CN201210477888 A CN 201210477888A CN 103840012 A CN103840012 A CN 103840012A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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Abstract
The invention provides a junction field-effect transistor (JFET) and a preparation method thereof, and belongs to the technical field of a JFET. The JFET comprises: a buried layer of a first conductive type, which is formed on a substrate; an epitaxial layer which grows and is formed on the buried layer in an epitaxial mode; a first trap of the first conductive type, which is formed in the epitaxial layer for forming a channel, the first trap being led out to form a source electrode; a second trap of a second conductive type, which is formed in the epitaxial layer, is disposed at the two sides of the width direction of the first trap and is adjacent to the first trap, the second trap being led out to form a grid electrode; and a third trap of the first conductive type, which is formed in the epitaxial layer, the third trap being led out to form a drain electrode. The channel direction of the JFET is basically vertical to the surface of the substrate; while the JFET is conducted, the first trap and the third trap are electrically connected for conduction through the buried layer; and the first conductive type is opposite to the second conductive layer. The pinch-off voltage of the JFET has the advantages of easy device adjustment and simple preparation process.
Description
Technical field
The invention belongs to junction field effect transistor (JFET) technical field, relate to the width size that can form the trap of vertical-channel by adjusting and regulate the junction field effect transistor of its pinch-off voltage (Pinch-off Voltage).
Background technology
Junction field effect transistor is widely used in the design of all kinds of analog circuits, for example: amplifier circuit, bias voltage or reduction voltage circuit, start-up circuit, variable resistor etc.For the high-voltage semi-conductor integrated circuit day by day rising, for meeting the demand such as different operating voltage devices in power management chip, the pinch-off voltage (also referred to as breakdown voltage) that improves junction field effect transistor meets the demand of more power management chip, becomes a new research topic.
In the jfet structure of prior art, the adjusting of its pinch-off voltage needs extra increase Mask(mask plate) and realize by extra injection, also greatly increased the complexity of its process costs and manufacture, and in same chip, be difficult to the preparation of the junction field effect transistor of simultaneously realizing various different pinch-off voltages.
Summary of the invention
One of object of the present invention is, proposes a kind of pinch-off voltage and is easy to regulate the junction field effect transistor arranging.
Another object of the present invention is, reduces the complicated process of preparation of junction field effect transistor.
For realizing above object or other objects, the invention provides following technical scheme.
According to an aspect of of the present present invention, a kind of junction field effect transistor is provided, it comprises:
On substrate, form the buried regions of the first conduction type;
The epitaxial loayer that epitaxial growth forms on described buried regions;
The first trap of the first conduction type that is used to form raceway groove forming in epitaxial loayer, described the first trap is drawn formation source electrode;
The second trap of the both sides of the Width forming in epitaxial loayer, be positioned at described the first trap the second conduction type being adjacent, described the second trap is drawn formation grid; And
The triple-well of the first conduction type forming in epitaxial loayer, described triple-well is drawn forms drain electrode;
Wherein, the channel direction of described junction field effect transistor is basically perpendicular to described substrate surface;
Described junction field effect transistor, in the time of conducting, is electrically connected conducting by described buried regions between described the first trap and described triple-well;
Described the first conduction type is contrary each other with described the second conduction type.
According to junction field effect transistor of the present invention, wherein, the width of described the first trap is set to regulate the pinch-off voltage of described junction field effect transistor.
According to the junction field effect transistor of one embodiment of the invention, wherein, the width of described the first trap arranges in the scope of 0.8 micron to 1.2 microns.
Preferably, the length of described raceway groove equals the thickness of described epitaxial loayer substantially.
In the junction field effect transistor of described any embodiment before, preferably, described the second trap is two, and it lays respectively at the both sides of the Width of described the first trap.
In the junction field effect transistor of described any embodiment before, at the described grid upper offset signal of telecommunication so that the PN junction reverse bias forming between described the first trap and described the second trap, by regulating the signal of telecommunication size of described grid upper offset to regulate the width of the depletion region of corresponding PN junction in described the first trap.
Further, when described grid upper offset pinch-off voltage, when described grid upper offset pinch-off voltage, the width of described the first trap equals the width of described depletion region substantially.
Further, the doping content scope of described buried regions can be 1E15/cm
3to 1E19/cm
3.Further, the doping content scope of described the first trap can be 1E15/cm
3to 1E19/cm
3.
Further, the doping content scope of described the second trap can be 1E15/cm
3to 1E19/cm
3.
Further, the doping content scope of described triple-well can be 1E15/cm
3to 1E19/cm
3.
Preferably, the doping content of described the first trap is lower than the doping content of described the second trap.
According to the also junction field effect transistor of an embodiment of the present invention, wherein, described triple-well be positioned at described the second trap Width both sides and be adjacent.
According to another aspect of the present invention, provide a kind of prepare the above and the method for junction field effect transistor, it comprises step:
On substrate, composition doping forms buried regions;
On the buried regions of described substrate, epitaxial growth forms epitaxial loayer;
On described epitaxial loayer, composition doping forms described the first trap, the second trap and triple-well; And
On described the first trap, the second trap and triple-well, draw respectively and form source electrode, grid and drain electrode.
According to the preparation method of the junction field effect transistor of one embodiment of the invention, wherein, form in source electrode, grid and drain electrode step drawing, on described the first trap, the second trap and triple-well, composition doping is formed with source electrode draw-out area, grid draw-out area and drain electrode draw-out area respectively.
According to the also preparation method of the junction field effect transistor of an embodiment of the present invention, wherein, described the first trap is identical with the doping content of described triple-well, and described the first trap and described triple-well form by synchronous composition doping.
Preferably, the doping content of described the first trap is lower than the doping content of described the second trap.
Technique effect of the present invention is, by form the raceway groove of direction perpendicular to substrate surface in the first trap, and the second trap is in the both sides of the Width of the first trap and be adjacent, conductivity type opposite, and it can regulate raceway groove easily.Therefore, the pinch-off voltage parameter of junction field effect transistor of the present invention can be subject to the width parameter control of the first trap, the width that the first trap is set by Butut can regulate easily pinch-off voltage size is set, and pinch-off voltage adjustable range is large, the compatible of the convenient junction field effect transistor of realizing different pinch-off voltages in same chip is standby, and preparation technology is simple.
Brief description of the drawings
From following detailed description by reference to the accompanying drawings, will make above and other object of the present invention and advantage more completely clear, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the cross section structure schematic diagram according to the junction field effect transistor of one embodiment of the invention.
Fig. 2 is the Id-Vg curve synoptic diagram of junction field effect transistor embodiment illustrated in fig. 1.
Fig. 3 is the Id-Vd curve synoptic diagram of junction field effect transistor embodiment illustrated in fig. 1.
Fig. 4 is the method flow schematic diagram of preparation junction field effect transistor embodiment illustrated in fig. 1.
Fig. 5 to Fig. 8 is the respective cross-section structural change schematic diagram based on the flow process of preparation method shown in Fig. 4.
Embodiment
What introduce below is some in multiple possibility embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.Easily understand, according to technical scheme of the present invention, do not changing under connotation of the present invention other implementations that one of ordinary skill in the art can propose mutually to replace.Therefore, below embodiment and accompanying drawing be only the exemplary illustration to technical scheme of the present invention, and should not be considered as of the present invention all or be considered as restriction or the restriction to technical solution of the present invention.
In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and region, and the mellow and full shape facility such as grade causing due to etching does not illustrate in the accompanying drawings.In description, use directional terminology (for example " on ", D score etc.) and the parts of the various execution modes described of similar terms represent the direction shown in accompanying drawing or the direction that can be understood by those skilled in the art.These directional terminology are used for relative description and clarification, instead of the orientation of any embodiment will be limited to concrete direction or orientation.
Figure 1 shows that the cross section structure schematic diagram according to the junction field effect transistor of one embodiment of the invention.In this embodiment, for convenience of not illustrating, to be defined as z direction perpendicular to the direction of substrate surface, to be parallel to substrate surface and the direction in channel width is defined as x direction.Junction field effect transistor 10 is in particular N-type junction field effect transistor in this example, it can be, but not limited to be formed in the Semiconductor substrate 11 of P-doping, the patterned doping of upper epidermis of Semiconductor substrate 11 forms buried regions (Buried Layer) 111, buried regions 111 is N-type doping, it is contrary doping type with Semiconductor substrate 11, and its doping content is relatively high, for example, the concentration range of buried regions 111 is 1E15/cm
3to 1E19/cm
3, for example, 4E18/cm
3.On buried regions 111, growth has formed the epitaxial loayer 12 that thickness is L1 in the z-direction, in epitaxial loayer 12, composition doping has formed N trap (being N conduction type) 121, P trap (being P conduction type) 122a and 122b and N trap (being N conduction type) 123a and 123b.Wherein, N trap 121 is drawn and is formed source electrode, P trap 122a and 122b and drawn and form grid, N trap 123a and 123b and drawn and form drain electrode; Particularly, on N trap 121, doping formation doping content is relatively higher than the source electrode draw-out area (N+) 1211 of N trap 121, form respectively doping content and be relatively higher than grid draw-out area (P+) 1221a and the 1221b of P trap in P trap 122a and 122b doping, form respectively doping content and be relatively higher than drain electrode draw-out area (N+) 1231a and the 1231b of N trap in N trap 123a and 123b doping.
Continue as shown in Figure 1, in this embodiment, N trap 121, P trap 122a and 122b, N trap 123a and 123b form by vertical dopant, and each trap runs through epitaxial loayer 12 in direction substantially, thereby its thickness equals the thickness L1 of epitaxial loayer 12 substantially.Adjacent both sides in the x of N trap 121 direction form respectively P trap 122a and 122b, the conductivity type opposite of the N trap 121 of the doping content of P trap 122a and 122b identical and its conduction type and adjacency, therefore, P trap 122a contacts and forms respectively PN junction with N trap 121 with 122b, for example, in the time that PN junction two ends add reversed bias voltage (gate bias negative voltage), the depletion region meeting broadening of PN junction, along with the increase of reversed bias voltage, in N trap 121, the depletion region of a corresponding PN junction can extremely contact with the depletion region of another PN junction by broadening, now raceway groove is substantially by pinch off, its effective width is the width that the effective width of 0(raceway groove equals its width and deduct depletion region), during by pinch off, corresponding reversed bias voltage is also defined as the pinch-off voltage of this junction field effect transistor.Therefore, the vertical-channel (as shown in dotted arrow in figure) forming in N trap 121 is in the time that grid is biased to pinch-off voltage, and it will disappear substantially.
In this embodiment, the pinch-off voltage Vp of junction field effect transistor 10 is at least decided by the width W of N trap 121, and width W is larger, the absolute value larger (being more not easy by pinch off) of pinch-off voltage Vp, on the contrary the absolute value of pinch-off voltage Vp is less; And its width W can be in the time that composition doping forms N trap 121, regulate and arrange by layout (Layout) Butut easily, therefore, the pinch-off voltage Vp of the junction field effect transistor 10 of this embodiment is very easy to regulate, and can be by different W be set in same chip, form the junction field effect transistor of multiple different pinch-off voltages.In this embodiment, the doping content scope of N trap 121 is 1E15/cm
3to 1E18/cm
3, for example, 4E16/cm
3, the doping content scope of P trap 122a and 122b is 1E15/cm
3to 1E18/cm
3, for example, 7E17/cm
3; Width W can arrange in the scope of 0.8 micron to 1.2 microns, and its pinch-off voltage Vp correspondingly changes to the scope of-2.6V at-0.6V.It will be appreciated that, the setting of above width W and corresponding pinch-off voltage Vp is only exemplary, and those skilled in the art can be according to above instruction and enlightenment, and corresponding width W parameter is specifically set.
In a preferred embodiment, the doping content of N trap 121 also can be set lower than the doping content of P trap 122a and 122b, thereby the two is forming PN junction and PN junction when reverse-biased, in N trap, depletion region is thicker, and its broadening effect is also more remarkable.Therefore, also can be by the concentration parameter of N trap 121 being set, regulating the pinch-off voltage that this JEFT is set, it regulates more aobvious convenience is set.
Continue as shown in Figure 1, N trap 123a and 123b lay respectively at the both sides of the x direction of P trap 122a and 122b, N trap 123a and P trap 122a adjacency, and N trap 123b and P trap 122b adjacency, the doping content of N trap 123a and 123b can be identical, and its doping content scope is 1E15/cm
3to 1E18/cm
3, for example, 4E16/cm
3.Between N trap 123a and 123b and N trap 121, buried regions 111 is electrically connected (between N trap 121 and buried regions 111, can be electrically connected), therefore, also can be understood as N trap 123a and draws from buried regions 111 is vertical with 123b.In the time of the biasing of drain electrode applied voltage, electronics can, via the vertical-channel of N trap 121, buried regions, N trap 123a or 123b, flow to drain electrode (as shown in dotted arrow Fig. 1) from source electrode.It should be noted that, in the time of drain bias high pressure, the breakdown voltage of junction field effect transistor 10 depends primarily on P trap 122a(or 122b) with N trap 123a(or 123b) voltage endurance capability of knot that forms, it generally can meet the withstand voltage demand higher than 40V.And buried regions 111 and N trap 123a and 123b can also form the shading ring of N trap 121, P trap 122a and 122b, conveniently meet the requirement of different circuit design.
The junction field effect transistor 10 of embodiment can be by arranging its pinch-off voltage of width adjusting Vp as shown in Figure 1.Figure 2 shows that the Id-Vg curve synoptic diagram of junction field effect transistor embodiment illustrated in fig. 1.In width W during respectively at 0.8um, 1.0um, 1.2um, its pinch-off voltage roughly respectively-0.6V ,-1.6V ,-2.6V.And when grid upper offset signal of telecommunication Vg, the effective width by P trap 122a and 122b modulation N trap 121 to be to regulate its conducting resistance, thereby makes electric current I d change (in the situation that Vd is certain) thereupon; In the time that Vg equals pinch-off voltage substantially, the effective width of N trap 121 is modulated to 0 by P trap 122a and 122b.Figure 3 shows that the Id-Vd curve synoptic diagram of junction field effect transistor embodiment illustrated in fig. 1.
Continue as shown in Figure 1, preferably, between each well region of epitaxial loayer 12, can be provided with the separator 125 for isolating, for example, separator 125 can be, but not limited to as shallow groove isolation layer (STI), and separator 125 also can form with LOCOS isolation method.
Figure 4 shows that the method flow schematic diagram of preparation junction field effect transistor embodiment illustrated in fig. 1.Fig. 5 is to the respective cross-section structural change schematic diagram Figure 8 shows that based on the flow process of preparation method shown in Fig. 4.Below in conjunction with Fig. 5 to Fig. 8, preparation method's process of junction field effect transistor embodiment illustrated in fig. 1 is described.
First, step S310, on substrate, composition doping forms buried regions.As shown in Figure 5, select the P type semiconductor substrate 11 of certain doping content, composition doping thereon forms buried regions 111, and buried regions 111 is N-type conduction type, its doping content relatively high (for example, its doping content is higher than the doping content of N trap 121).
Further, step S320, on the buried regions of substrate, epitaxial growth forms epitaxial loayer.As shown in Figure 6, buried regions 111 is formed on the upper epidermis of Semiconductor substrate 111, can form epitaxial loayer 12 by epitaxial growth technology thereon, the vertical-channel length scale of the junction field effect transistor 10 that the thickness L1 of epitaxial loayer 12 can form as required arranges, and its concrete thickness size, formation technique etc. is not restrictive.
Further, step S330, on described epitaxial loayer, composition doping forms the first trap, the second trap and triple-well.As shown in Figure 7, the first trap, the second trap and triple-well are respectively N trap 121, P trap 122a and 122b, N trap 123a and 123b, N trap 121 is used to form the raceway groove perpendicular to substrate surface, P trap 122a and 122b are adjacent to N trap 121 for modulating raceway groove, and N trap 123a and 123b form drain electrode for drawing to form the buried regions 111 of drain terminal and then draw thereon.N trap 121, P trap 122a and 122b, N trap 123a and 123b all can adulterate by vertical composition, its doping substantially connects epitaxial loayer 12 and stops on buried regions 111 surfaces in z direction, therefore the width of N trap 121, P trap 122a and 122b, N trap 123a and 123b all easily conveniently arranges by Butut (Layout), especially for N trap 121, its width W can be adjusted setting easily by Butut, regulates thereby pinch-off voltage is convenient.N trap 121, N trap 123a and 123b are identical conduction type, the doping content between them can be identical can be not identical yet, in the situation that doping content is identical, N trap 121, N trap 123a and 123b synchronously composition doping form.But the composition doping-sequence between N trap 121, N trap 123a and 123b, P trap 122a and 122b three is not restrictive, concrete doping method separately neither be restrictive, for example, can select ion injection method doping.
Further, step S340 draws respectively and forms source electrode, grid and drain electrode on the first trap, the second trap and triple-well.As shown in Figure 8, in this embodiment, on N trap 121, doping formation doping content is relatively higher than the source electrode draw-out area (N+) 1211 of N trap 121, form respectively doping content and be relatively higher than grid draw-out area (P+) 1221a and the 1221b of P trap in P trap 122a and 122b doping, form respectively doping content and be relatively higher than drain electrode draw-out area (N+) 1231a and the 1231b of N trap in N trap 123a and 123b doping, then on source electrode draw-out area 1211, form metal electrode and form source electrode (Source) to draw, on grid draw-out area 1221a and 1221b, form metal electrode simultaneously and form grid (Gate) to draw, on drain electrode draw-out area 1231a and 1231b, form metal electrode simultaneously and form drain electrode (Drain) to draw.In this embodiment, can also between each well region, form the separator 125 of the upper surface that is positioned at epitaxial loayer 12.So far, junction field effect transistor 10 embodiment illustrated in fig. 1 basically forms.
It should be noted that, in above illustrated embodiment, taking N-type (N-type raceway groove) junction field effect transistor as example, its architectural feature and preparation method are described, those skilled in the art are under above instruction and enlightenment, (for example it can be applied to analogically equally in the structure setting of P type (P type raceway groove) junction field effect transistor and preparation method, the first trap, the second trap, triple-well are corresponding respectively), and have equally pinch-off voltage be easy to regulate arrange, adjustable range is large, the simple advantage of preparation technology.
Above example has mainly illustrated junction field effect transistor of the present invention and preparation method thereof, although only some of them embodiments of the present invention are described, but those of ordinary skill in the art should understand, the present invention can implement not departing from its purport and scope with many other forms.Therefore, the example of showing and execution mode are regarded as illustrative and not restrictive, and in the situation that not departing from spirit of the present invention as defined in appended each claim and scope, the present invention may be contained various amendments and replacement.
Claims (17)
1. a junction field effect transistor, is characterized in that, comprising:
On substrate, form the buried regions of the first conduction type;
The epitaxial loayer that epitaxial growth forms on described buried regions;
The first trap of the first conduction type that is used to form raceway groove forming in epitaxial loayer, described the first trap is drawn formation source electrode;
The second trap of the both sides of the Width forming in epitaxial loayer, be positioned at described the first trap the second conduction type being adjacent, described the second trap is drawn formation grid; And
The triple-well of the first conduction type forming in epitaxial loayer, described triple-well is drawn forms drain electrode;
Wherein, the channel direction of described junction field effect transistor is basically perpendicular to described substrate surface;
Described junction field effect transistor, in the time of conducting, is electrically connected conducting by described buried regions between described the first trap and described triple-well;
Described the first conduction type is contrary each other with described the second conduction type.
2. junction field effect transistor as claimed in claim 1, is characterized in that, the width of described the first trap is set to regulate the pinch-off voltage of described junction field effect transistor.
3. junction field effect transistor as claimed in claim 1 or 2, is characterized in that, the width of described the first trap arranges in the scope of 0.8 micron to 1.2 microns.
4. junction field effect transistor as claimed in claim 1 or 2, is characterized in that, the length of described raceway groove equals the thickness of described epitaxial loayer substantially.
5. junction field effect transistor as claimed in claim 1 or 2, is characterized in that, described the second trap is two, and it lays respectively at the both sides of the Width of described the first trap.
6. junction field effect transistor as claimed in claim 1 or 2, it is characterized in that, at the described grid upper offset signal of telecommunication so that the PN junction reverse bias forming between described the first trap and described the second trap, by regulating the signal of telecommunication size of described grid upper offset to regulate the width of the depletion region of corresponding PN junction in described the first trap.
7. junction field effect transistor as claimed in claim 6, is characterized in that, when described grid upper offset pinch-off voltage, the width of described the first trap equals the width of described depletion region substantially.
8. junction field effect transistor as claimed in claim 1, is characterized in that, the doping content scope of described buried regions is 1E15/cm
3to 1E19/cm
3.
9. the junction field effect transistor as described in claim 1 or 8, is characterized in that, the doping content scope of described the first trap is 1E15/cm
3to 1E18/cm
3.
10. the junction field effect transistor as described in claim 1 or 8 or 9, is characterized in that, the doping content scope of described the second trap is 1E15/cm
3to 1E18/cm
3.
11. junction field effect transistors as described in claim 1 or 8 or 9 or 10, is characterized in that, the doping content scope of described triple-well is 1E15/cm
3to 1E18/cm
3.
12. junction field effect transistors as described in claim 1 or 8, is characterized in that, the doping content of described the first trap is lower than the doping content of described the second trap.
13. junction field effect transistors as claimed in claim 1 or 2, is characterized in that, described triple-well be positioned at described the second trap Width both sides and be adjacent.
Prepare the method for junction field effect transistor as claimed in claim 1 for 14. 1 kinds, it is characterized in that, comprise step:
On substrate, composition doping forms buried regions;
On the buried regions of described substrate, epitaxial growth forms epitaxial loayer;
On described epitaxial loayer, composition doping forms described the first trap, the second trap and triple-well; And
On described the first trap, the second trap and triple-well, draw respectively and form source electrode, grid and drain electrode.
15. methods as claimed in claim 14, is characterized in that, form in source electrode, grid and drain electrode step drawing, and on described the first trap, the second trap and triple-well, composition doping is formed with source electrode draw-out area, grid draw-out area and drain electrode draw-out area respectively.
16. methods as claimed in claim 14, is characterized in that, described the first trap is identical with the doping content of described triple-well, and described the first trap and described triple-well form by synchronous composition doping.
17. methods as described in claim 14 or 16, is characterized in that, the doping content of described the first trap is lower than the doping content of described the second trap.
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|---|---|---|---|
| CN201210477888.9A CN103840012A (en) | 2012-11-22 | 2012-11-22 | Junction field-effect transistor (JFET) and preparation method thereof |
| PCT/CN2013/087644 WO2014079381A1 (en) | 2012-11-22 | 2013-11-21 | Junction field-effect transistor and preparation method therefor |
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| CN201210477888.9A CN103840012A (en) | 2012-11-22 | 2012-11-22 | Junction field-effect transistor (JFET) and preparation method thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106898576A (en) * | 2015-12-21 | 2017-06-27 | 意法半导体(克洛尔2)公司 | Method and corresponding integrated circuit for manufacturing JFET transistor in integrated circuit |
| CN108886056A (en) * | 2016-03-31 | 2018-11-23 | 罗伯特·博世有限公司 | Vertical SiC-MOSFET |
| CN108878513A (en) * | 2017-05-09 | 2018-11-23 | 世界先进积体电路股份有限公司 | Semiconductor device and its manufacturing method |
| CN111200014A (en) * | 2018-11-19 | 2020-05-26 | 上海晶丰明源半导体股份有限公司 | Junction field effect transistor and manufacturing method thereof |
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