WO2021223357A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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WO2021223357A1
WO2021223357A1 PCT/CN2020/117286 CN2020117286W WO2021223357A1 WO 2021223357 A1 WO2021223357 A1 WO 2021223357A1 CN 2020117286 W CN2020117286 W CN 2020117286W WO 2021223357 A1 WO2021223357 A1 WO 2021223357A1
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type
gate
semiconductor device
region
epitaxial layer
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PCT/CN2020/117286
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French (fr)
Chinese (zh)
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刘磊
刘伟
袁愿林
龚轶
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苏州东微半导体有限公司
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Publication of WO2021223357A1 publication Critical patent/WO2021223357A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/83—FETs having PN junction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies

Definitions

  • This application belongs to the technical field of semiconductor devices, such as a semiconductor device related to junction field effect transistors.
  • JFET Junction Field effect transistor
  • n-type semiconductor substrate 10 an n-type semiconductor substrate 10
  • p-type doped regions 13 located in the n-type semiconductor substrate 10
  • Two p-type doped regions 13) are shown, a pn junction gate structure is formed between the p-type doped region 13 and the n-type semiconductor substrate 10, and the p-type doped region 13 passes through the gate metal (not shown in FIG. 1 (Shown) the gate voltage is drawn, both ends of the n-type semiconductor substrate 10 are respectively provided with an n-type drain region 12 and an n-type source region 11, and the n-type drain region 12 passes through the drain metal (not shown in FIG. 1) The drain voltage is drawn, and the n-type source region 11 is drawn with the source voltage through the source metal (not shown in FIG. 1).
  • the related art JFET device generally reduces its on-resistance by increasing the doping concentration of the n-type semiconductor substrate 10, but the increase of the doping concentration of the n-type semiconductor substrate 10 will reduce the breakdown voltage of the JFET device.
  • the present application provides a semiconductor device that can reduce the on-resistance without reducing its breakdown voltage.
  • This application provides a semiconductor device, including:
  • At least two gate regions located in the n-type epitaxial layer and far away from the n-type drain region;
  • An n-type source region located in the n-type epitaxial layer and between adjacent gate regions;
  • At least one p-type pillar located in the n-type epitaxial layer and between the gate region and the n-type drain region.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a JFET device in the related art
  • FIG. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor device provided by the present application
  • FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor device provided by the present application.
  • FIG. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor device provided by the present application.
  • the semiconductor device provided by the present application includes an n-type drain region 20, which is located above the n-type drain region 20.
  • n-type epitaxial layer 21 at least two gate regions 31 located in the n-type epitaxial layer 21 and far away from the n-type drain region 20, n-type located in the n-type epitaxial layer 21 and between adjacent gate regions 31
  • the source region 23 is at least one p-type pillar 22 located in the n-type epitaxial layer 21 and between the gate region 31 and the n-type drain region 20.
  • the number of p-type pillars 22 may be greater than, equal to, or less than the number of gate regions 31.
  • the n-type source region 23 located in the n-type epitaxial layer 21 and between adjacent p-type doped regions 24 is located in the n-type epitaxial layer 21 and between the p-type doped region 24 and the n-type drain region 20 Between multiple p-type pillars 22. Only three p-type doped regions 24 and three p-type pillars 22 are shown as an example in FIG. 3. In this embodiment, a p-type pillar is provided under each p-type doped region, and the p-type pillar is connected to the gate voltage through the corresponding p-type doped region, that is, the p-type pillars 22 are sequentially arranged in the p-type doped region. Below 24 and in contact with the p-type doped region 24, the p-type pillar 22 is connected to the gate voltage through the corresponding p-type doped region 24.
  • p-type pillars are arranged in the n-type epitaxial layer, and a charge balance is formed between the p-type pillars and the n-type epitaxial layer.
  • the charge balance structure ensures that the breakdown voltage of the semiconductor device is not reduced.

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  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present application belongs to the technical field of semiconductor devices. Disclosed is a semiconductor device, comprising: an n-type drain region; an n-type epitaxial layer located on the n-type drain region; at least two gate regions located within the n-type epitaxial layer and away from one side of the n-type drain region; an n-type source region located within the n-type epitaxial layer and located between adjacent gate regions; and a plurality of p-type columns located within the n-type epitaxial layer and between the gate regions and the n-type drain region.

Description

半导体器件Semiconductor device

本申请要求在2020年5月6日提交中国专利局、申请号为202010373740.5的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with an application number of 202010373740.5 on May 6, 2020. The entire content of this application is incorporated into this application by reference.

技术领域Technical field

本申请属于半导体器件技术领域，例如一种关于结型场效应晶体管的半导体器件。This application belongs to the technical field of semiconductor devices, such as a semiconductor device related to junction field effect transistors.

背景技术Background technique

在功率应用中，JFET(Junction Field-Effect Transistor，结型场效应晶体管)器件是由p-n结栅极、源极和漏极构成的一种具有放大功能的三端有源器件，其工作原理就是通过栅极电压改变沟道的导电性来实现对输出电流的控制。图1是相关技术的一种JFET器件的剖面结构示意图，包括：n型半导体衬底10，位于n型半导体衬底10内的至少两个p型掺杂区13(图1中仅示例性的示出了两个p型掺杂区13)，p型掺杂区13与n型半导体衬底10之间形成p-n结栅极结构，p型掺杂区13通过栅极金属(图1中未示出)引出接栅极电压，n型半导体衬底10的两端分别设有n型漏区12和n型源区11，n型漏区12通过漏极金属(图1中未示出)引出接漏极电压，n型源区11通过源极金属(图1中未示出)引出接源极电压。相关技术的JFET器件通常是通过增大n型半导体衬底10的掺杂浓度来降低其导通电阻，但是n型半导体衬底10的掺杂浓度的增加会使得JFET器件的击穿电压降低。In power applications, JFET (Junction Field-Effect Transistor, junction field effect transistor) device is a three-terminal active device with amplification function composed of pn junction gate, source and drain. Its working principle is The control of the output current is achieved by changing the conductivity of the channel through the gate voltage. 1 is a schematic cross-sectional structure diagram of a related art JFET device, including: an n-type semiconductor substrate 10, at least two p-type doped regions 13 located in the n-type semiconductor substrate 10 (only exemplary in FIG. 1 Two p-type doped regions 13) are shown, a pn junction gate structure is formed between the p-type doped region 13 and the n-type semiconductor substrate 10, and the p-type doped region 13 passes through the gate metal (not shown in FIG. 1 (Shown) the gate voltage is drawn, both ends of the n-type semiconductor substrate 10 are respectively provided with an n-type drain region 12 and an n-type source region 11, and the n-type drain region 12 passes through the drain metal (not shown in FIG. 1) The drain voltage is drawn, and the n-type source region 11 is drawn with the source voltage through the source metal (not shown in FIG. 1). The related art JFET device generally reduces its on-resistance by increasing the doping concentration of the n-type semiconductor substrate 10, but the increase of the doping concentration of the n-type semiconductor substrate 10 will reduce the breakdown voltage of the JFET device.

发明内容Summary of the invention

本申请提供一种半导体器件，在降低导通电阻的同时还可以不降低其击穿电压。The present application provides a semiconductor device that can reduce the on-resistance without reducing its breakdown voltage.

本申请提供了一种半导体器件，包括：This application provides a semiconductor device, including:

n型漏区；n-type drain region;

位于所述n型漏区之上的n型外延层；An n-type epitaxial layer located on the n-type drain region;

位于所述n型外延层内且远离所述n型漏区一侧的至少两个栅区；At least two gate regions located in the n-type epitaxial layer and far away from the n-type drain region;

位于所述n型外延层内且位于相邻的所述栅区之间的n型源区；An n-type source region located in the n-type epitaxial layer and between adjacent gate regions;

位于所述n型外延层内且介于所述栅区和所述n型漏区之间的至少一个p型柱。At least one p-type pillar located in the n-type epitaxial layer and between the gate region and the n-type drain region.

附图说明Description of the drawings

图1是相关技术的一种JFET器件的剖面结构示意图；FIG. 1 is a schematic diagram of a cross-sectional structure of a JFET device in the related art;

图2是本申请提供的一种半导体器件的第一个实施例的剖面结构示意图；2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor device provided by the present application;

图3是本申请提供的一种半导体器件的第二个实施例的剖面结构示意图；3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor device provided by the present application;

图4是本申请提供的一种半导体器件的第三个实施例的剖面结构示意图。FIG. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor device provided by the present application.

具体实施方式Detailed ways

以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出至少一个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。The technical solutions of the present application will be fully described below in specific ways in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. It should be understood that the terms such as "having", "including" and "including" used in this application do not include the presence or addition of at least one other element or a combination thereof. At the same time, in order to clearly illustrate the specific implementation of the present application, the schematic diagrams listed in the drawings of the specification have enlarged the thickness of the layers and regions described in the present application, and the listed graphic sizes do not represent actual sizes.

图2是本申请提供的一种半导体器件的第一个实施例的剖面结构示意图，如图2所示，本申请提供的半导体器件包括n型漏区20，位于n型漏区20之上的n型外延层21，位于n型外延层21内且远离n型漏区20一侧的至少两个栅区31，位于n型外延层21内且位于相邻的栅区31之间的n型源区23，位于n型外延层21内且介于栅区31和n型漏区20之间的至少一个p型柱22，在图 2中仅示例性的示出了三个栅区31和三个p型柱22，同时p型柱22均浮空设置，可选的，p型柱22的数量可以大于、等于或者小于栅区31的数量。2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor device provided by the present application. As shown in FIG. 2, the semiconductor device provided by the present application includes an n-type drain region 20, which is located above the n-type drain region 20. n-type epitaxial layer 21, at least two gate regions 31 located in the n-type epitaxial layer 21 and far away from the n-type drain region 20, n-type located in the n-type epitaxial layer 21 and between adjacent gate regions 31 The source region 23 is at least one p-type pillar 22 located in the n-type epitaxial layer 21 and between the gate region 31 and the n-type drain region 20. In FIG. 2, only three gate regions 31 and There are three p-type pillars 22, and the p-type pillars 22 are all floating. Optionally, the number of p-type pillars 22 may be greater than, equal to, or less than the number of gate regions 31.

图3是本申请提供的一种半导体器件的第二个实施例的剖面结构示意图，如图3所示，本申请提供的半导体器件包括n型漏区20，位于n型漏区20之上的n型外延层21，位于n型外延层21内且远离n型漏区20一侧的至少两个栅区，所述栅区为p型掺杂区24，p型掺杂区24通过栅极金属25外接栅极电压，示例性的，栅极金属25凹陷在p型掺杂区24内，以降低接触电阻。位于n型外延层21内且位于相邻的p型掺杂区24之间的n型源区23，位于n型外延层21内且介于p型掺杂区24和n型漏区20之间的多个p型柱22。图3中仅示例性的示出了三个p型掺杂区24和三个p型柱22。在该实施例中，每个p型掺杂区下方均设置一个p型柱，p型柱通过对应的p型掺杂区外接栅极电压，即p型柱22依次设置于p型掺杂区24下方并且与p型掺杂区24接触连接，p型柱22通过对应的p型掺杂区24外接栅极电压。FIG. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor device provided by the present application. As shown in FIG. 3, the semiconductor device provided by the present application includes an n-type drain region 20 located above the n-type drain region 20 The n-type epitaxial layer 21 is at least two gate regions located in the n-type epitaxial layer 21 and far away from the n-type drain region 20. The gate region is a p-type doped region 24, and the p-type doped region 24 passes through the gate The metal 25 is externally connected to the gate voltage. For example, the gate metal 25 is recessed in the p-type doped region 24 to reduce contact resistance. The n-type source region 23 located in the n-type epitaxial layer 21 and between adjacent p-type doped regions 24 is located in the n-type epitaxial layer 21 and between the p-type doped region 24 and the n-type drain region 20 Between multiple p-type pillars 22. Only three p-type doped regions 24 and three p-type pillars 22 are shown as an example in FIG. 3. In this embodiment, a p-type pillar is provided under each p-type doped region, and the p-type pillar is connected to the gate voltage through the corresponding p-type doped region, that is, the p-type pillars 22 are sequentially arranged in the p-type doped region. Below 24 and in contact with the p-type doped region 24, the p-type pillar 22 is connected to the gate voltage through the corresponding p-type doped region 24.

图4是本申请提供的一种半导体器件的第三个实施例的剖面结构示意图，如图4所示，本申请提供的半导体器件包括n型漏区20，位于n型漏区20之上的n型外延层21，位于n型外延层21内且远离n型漏区20一侧的至少两个栅区，所述栅区包括p型掺杂区24以及位于p型掺杂区24两侧的栅沟槽，每个栅沟槽内均设有栅介质层26和栅极27，栅极27和p型掺杂区24均通过栅极金属(栅极金属在图4中未示出)外接栅极电压。位于n型外延层21内且位于相邻的p型掺杂区24之间的n型源区23，位于n型外延层21内且介于p型掺杂区24和n型漏区20之间的多个p型柱22。图4中仅示例性的示出了三个p型掺杂区24和三个p型柱22，p型柱22依次设置与p型掺杂区24下方并且与p型掺杂区24接触连接，p型柱22通过对应的p型掺杂区24外接栅极电压。可选的，p型掺杂区的24横向宽度可以小于p型柱22的横向宽度，以减小半导体器件的芯片面积，如图4所示。4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor device provided by the present application. As shown in FIG. 4, the semiconductor device provided by the present application includes an n-type drain region 20, which is located above the n-type drain region 20 The n-type epitaxial layer 21 is at least two gate regions located in the n-type epitaxial layer 21 and far away from the n-type drain region 20. The gate region includes a p-type doped region 24 and located on both sides of the p-type doped region 24 Each gate trench is provided with a gate dielectric layer 26 and a gate 27, and the gate 27 and the p-type doped region 24 pass through the gate metal (the gate metal is not shown in FIG. 4) External grid voltage. The n-type source region 23 located in the n-type epitaxial layer 21 and between adjacent p-type doped regions 24 is located in the n-type epitaxial layer 21 and between the p-type doped region 24 and the n-type drain region 20 Between multiple p-type pillars 22. FIG. 4 only exemplarily shows three p-type doped regions 24 and three p-type pillars 22. The p-type pillars 22 are sequentially arranged below the p-type doped region 24 and are in contact with the p-type doped region 24. , The p-type pillar 22 is externally connected to the gate voltage through the corresponding p-type doped region 24. Optionally, the lateral width 24 of the p-type doped region may be smaller than the lateral width of the p-type pillar 22 to reduce the chip area of the semiconductor device, as shown in FIG. 4.

本申请的半导体器件，在n型外延层内设置p型柱，p型柱与n型外延层之间形成电荷平衡，这样通过提高n型外延层的掺杂浓度来降低导通电阻时，可以通过电荷平衡结构来保证半导体器件的击穿电压不被降低。In the semiconductor device of the present application, p-type pillars are arranged in the n-type epitaxial layer, and a charge balance is formed between the p-type pillars and the n-type epitaxial layer. In this way, when the on-resistance is reduced by increasing the doping concentration of the n-type epitaxial layer, The charge balance structure ensures that the breakdown voltage of the semiconductor device is not reduced.

Claims (8)

一种半导体器件，包括：A semiconductor device including: n型漏区；n-type drain region; 位于所述n型漏区之上的n型外延层；An n-type epitaxial layer located on the n-type drain region; 位于所述n型外延层内且远离所述n型漏区一侧的至少两个栅区；At least two gate regions located in the n-type epitaxial layer and far away from the n-type drain region; 位于所述n型外延层内且位于相邻的所述栅区之间的n型源区；An n-type source region located in the n-type epitaxial layer and between adjacent gate regions; 位于所述n型外延层内且介于所述栅区和所述n型漏区之间的至少一个p型柱。At least one p-type pillar located in the n-type epitaxial layer and between the gate region and the n-type drain region. 如权利要求1所述的半导体器件，其中，所述栅区包括p型掺杂区，所述p型掺杂区通过栅极金属外接栅极电压。The semiconductor device of claim 1, wherein the gate region comprises a p-type doped region, and the p-type doped region is externally connected to a gate voltage through a gate metal. 如权利要求2所述的半导体器件，其中，所述栅极金属凹陷在所述p型掺杂区内。3. The semiconductor device of claim 2, wherein the gate metal is recessed in the p-type doped region. 如权利要求2所述的半导体器件，其中，每个所述p型掺杂区下方均设置一个所述p型柱，所述p型柱通过对应的所述p型掺杂区外接栅极电压。The semiconductor device of claim 2, wherein one p-type pillar is provided under each of the p-type doped regions, and the p-type pillars are connected to a gate voltage through the corresponding p-type doped regions. . 如权利要求4所述的半导体器件，其中，所述栅区还包括位于所述p型掺杂区两侧的栅沟槽，所述栅沟槽内设有栅介质层和栅极，所述栅极外接栅极电压。The semiconductor device according to claim 4, wherein the gate region further comprises a gate trench located on both sides of the p-type doped region, a gate dielectric layer and a gate are provided in the gate trench, and The grid is connected to the grid voltage. 如权利要求5所述的半导体器件，其中，所述p型掺杂区的横向宽度小于所述p型柱的横向宽度。5. The semiconductor device of claim 5, wherein the lateral width of the p-type doped region is smaller than the lateral width of the p-type pillar. 如权利要求2所述的半导体器件，其中，所述p型柱浮空设置。The semiconductor device according to claim 2, wherein the p-type pillar is floating. 如权利要求1所述的半导体器件，其中，所述p型柱的数量大于、等于或者小于所述栅区的数量。The semiconductor device of claim 1, wherein the number of the p-type pillars is greater than, equal to, or less than the number of the gate regions.
PCT/CN2020/117286 2020-05-06 2020-09-24 Semiconductor device WO2021223357A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024131191A1 (en) * 2022-12-21 2024-06-27 苏州东微半导体股份有限公司 Semiconductor power device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600192B1 (en) * 1998-10-09 2003-07-29 The Kansai Electric Power Co., Inc. Vertical field-effect semiconductor device with buried gate region
US7211845B1 (en) * 2004-04-19 2007-05-01 Qspeed Semiconductor, Inc. Multiple doped channel in a multiple doped gate junction field effect transistor
CN102916049A (en) * 2012-10-30 2013-02-06 成都芯源系统有限公司 Semiconductor device including junction field effect transistor and method of manufacturing the same
CN103840012A (en) * 2012-11-22 2014-06-04 无锡华润上华半导体有限公司 Junction field-effect transistor (JFET) and preparation method thereof
EP2963678A1 (en) * 2014-03-26 2016-01-06 NGK Insulators, Ltd. Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4543706A (en) * 1984-02-24 1985-10-01 Gte Laboratories Incorporated Fabrication of junction field effect transistor with filled grooves
US6818939B1 (en) * 2003-07-18 2004-11-16 Semiconductor Components Industries, L.L.C. Vertical compound semiconductor field effect transistor structure
CN1812132A (en) * 2005-12-16 2006-08-02 北京工业大学 High-frequency low-consumption power junction type field effect transistor
DE102015121566B4 (en) * 2015-12-10 2021-12-09 Infineon Technologies Ag Semiconductor components and a circuit for controlling a field effect transistor of a semiconductor component

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6600192B1 (en) * 1998-10-09 2003-07-29 The Kansai Electric Power Co., Inc. Vertical field-effect semiconductor device with buried gate region
US7211845B1 (en) * 2004-04-19 2007-05-01 Qspeed Semiconductor, Inc. Multiple doped channel in a multiple doped gate junction field effect transistor
CN102916049A (en) * 2012-10-30 2013-02-06 成都芯源系统有限公司 Semiconductor device including junction field effect transistor and method of manufacturing the same
CN103840012A (en) * 2012-11-22 2014-06-04 无锡华润上华半导体有限公司 Junction field-effect transistor (JFET) and preparation method thereof
EP2963678A1 (en) * 2014-03-26 2016-01-06 NGK Insulators, Ltd. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024131191A1 (en) * 2022-12-21 2024-06-27 苏州东微半导体股份有限公司 Semiconductor power device

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