CN1812132A - High-frequency low-consumption power junction type field effect transistor - Google Patents
High-frequency low-consumption power junction type field effect transistor Download PDFInfo
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- CN1812132A CN1812132A CN 200510132111 CN200510132111A CN1812132A CN 1812132 A CN1812132 A CN 1812132A CN 200510132111 CN200510132111 CN 200510132111 CN 200510132111 A CN200510132111 A CN 200510132111A CN 1812132 A CN1812132 A CN 1812132A
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- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 238000009413 insulation Methods 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 40
- 239000010703 silicon Substances 0.000 claims description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 38
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 2
- 239000012774 insulation material Substances 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000006698 induction Effects 0.000 description 4
- 230000003068 static effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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Abstract
A kind of high-frequency low-power dissipation junction field effect transistor is consisted with channel region, source region, drain region, grid region and source electrode, grid electrode and drain electrode. In the semiconductor under each grid electrode bury the local insulation regions which have some distance each other. The insulation material of the insulation region is silicon oxide, silicon nitride or other insulation material. The junction field effect transistor can be ditch grid type or plane grid type. It can be frequent opening type or frequent closing type. As the local insulation region change electric field distribution, especially the local insulation region and grid region partly overlap and cut a part of area of grid ditch PN junction, the grid ditch PN junction electric capacity and switching wastage are reduced. This invention has lower high-frequency power consumption than ditch grid MOSFET and ditch grid without burying local insulation region JFET.
Description
Technical field:
The present invention relates to a kind of semiconductor device, more specifically saying so relates to a kind of power junction type field effect transistor (JFET).
Background technology:
Power transistor in power electronic technology generally with switch mode operation, for example in the Switching Power Supply.Major requirement to the power transistor performance is that high frequency power loss is little.This needs on-state power consumption Pon little little with switch power consumption Psw.The former requires on-state voltage drop Ron little; The latter requires switch-charge little, and it is little to discharge and recharge charge Q g when promptly changing between the open and close two condition.What used before the eighties last century is power bipolar transistor and thyristor, and their Ron is very little, but Qg is very big.And Psw is proportional to operating frequency, and the operating frequency that Qg crosses these devices of ambassador is limited in several kilo hertzs.The operating frequency that power electronic technology is used after the eighties improves rapidly.Adapt to this needs and power metal-oxide-field-effect transistor (power MOSFET) occurred, be suitable for the low pressure middle low power; Igbt (IGBT) has appearred in high-power field.Power MOSFET does not have the storage and the extraction of minority carrier when work, Ron is very big so its feature is just in time opposite with bipolar device, and Psw is very little.In order to reduce its Ron, structure to it has been carried out continuous improvement, vertical double diffusion power MOSFET (VDMOSFET), V-type groove power MOS FET, U type groove power MOS FET have been experienced, to the groove power MOSFET (TrenchMOSFET) of up-to-date vertical trench.Yet along with the meticulous and density of groove increases, gate capacitance increases, and Qg increases the restriction that begins to have shown to operating frequency.Up till now, the few of leeway of exploiting potentialities of TrenchMOSFET.And the development of compact device (as notebook computer) requires requirement that power tube further reduces power consumption also ever-increasingly.For this reason, the device developer examine closely again with last century the seventies trench gate junction field effect transistor (TrenchJFET) be used for this purposes.This device is called trench gate static induction transistor (SIT) or trench gate double pole mode static induction transistor (BSIT) (U.S.Patent, 4070690) again.The trench gate JFET of closed type the time has electricity to lead to be modulated to work in work makes Ron little, although there is electricity to lead modulation its switching loss there is adverse effect, but the change in voltage when changing between the open and close state between the drain-gate is less than MOSFET, is slightly less than TrenchMOSFET at the high frequency power consumption of the TrenchJFET of low-voltage and low-power dissipation optimization.Although the use of these new technologies is arranged, still can not finely satisfy the requirement of compact device development.
Summary of the invention:
Not enough little this weakness of Qg that The present invention be directed to existing TrenchJFET is carried out architecture advances, can obtain than the lower high frequency power loss of existing low pressure and low power semiconductor device.The present invention is a kind of high-frequency low-consumption power junction type field effect transistor, form by channel region, source region, drain region, grid region and source electrode, gate electrode, drain electrode, source region and drain region lay respectively at the 1st surface and the 2nd surface of silicon chip, channel region is between source region and drain region, channel region is the semiconductor with first kind of conductivity model, resistivity and perpendicular to the thickness of surface direction by puncture voltage decision between required drain-source, resistivity can be uniform or uneven; Source region and drain region also are the semiconductors with first kind of conductivity model, have doping content far above channel region to reduce series resistance and contact resistance; The source region is surrounded by the groove from the recessed certain depth in the 1st surface, gash depth can or not be 0 for 0, gash depth is to be known as surperficial grid junction type field effect transistor or surperficial grid electrostatic induction transistors at 0 o'clock, gash depth is not to be known as trench gate junction field effect transistor or trench gate static induction transistor at 0 o'clock; The grid region is to be arranged in channel bottom semiconductor semiconductor, that have second kind of conductivity model on every side, spacing between the adjacent grid region on the direction that is parallel to the semiconductor chip surface is changeable as required, form open type JFET when spacing is big, spacing hour formation closed type JFET; Grid region and channel region joint form PN junction; Source electrode, gate electrode and drain electrode lay respectively on the surface in corresponding each district; Filling dielectric on the gate electrode is generally silicon dioxide in the groove; The dielectric of source electrode metal filling in crossing groove is successively opened during the surface, it is characterized in that, buried in the semiconductor below each gate electrode have a local insulation layer.
Local insulation layer buried in the described semiconductor below each gate electrode has certain distance each other, and the adjacent distance of local insulation layer on the direction that is parallel to the semiconductor chip surface is 0.3 to 10 micron, for example can be 0.3,0.4,1,5,10 microns; The local insulation layer for example can be 0.2,0.4,1,3 being 0.2 to 3 micron perpendicular to the thickness on the direction on semiconductor chip surface, micron; The width of local insulation layer on the direction that is parallel to the semiconductor chip surface is 0.5 to 10 micron, for example 0.5,0.8,1,3, and 10 microns; The distance that the local insulation layer leaves gate electrode is 0 to 3 micron, for example can be 0,0.05,0.1,0.2,0.5,1,3 microns; The material that constitutes the local insulation layer is a silica, perhaps silicon nitride, and perhaps silicon oxynitride, perhaps silicon nitride layer and silicon oxide layer is compound.
Buried local insulation layer has substituted the semiconductor of relevant position below the gate electrode of power junction type field effect transistor of the present invention, because the change of Electric Field Distribution has reduced the barrier capacitance of PN junction between the grid ditch. when especially the local insulation layer distance of leaving gate electrode is less than the degree of depth of PN junction, insulation layer has cut off PN junction, significantly reduced the PN junction area, PN junction electric capacity is significantly reduced. therefore power field effect transistor of the present invention has less Qg and lower high frequency power loss Psw.
Description of drawings:
Fig. 1 junction field effect transistor schematic diagram that buried local insulation layer is arranged of the present invention
(A) trench gate type (gash depth is not 0)
(B) surperficial grid type (gash depth is 0)
The 1-channel region
The 2-source region
The 3-drain region
Fill megohmite insulant in the 4-groove, groove
The 5-grid region
6-source electrode
The 7-drain electrode
The 8-gate electrode
9-local insulation layer
10-silicon chip first surface
11-silicon chip second surface
The trench gate N raceway groove closed type silicon junction field effect transistor schematic diagram that buried local insulation layer is arranged of Fig. 2 embodiment of the invention
1.1-channel region
1.2-source region
1.3-drain region
1.4-fill silica in the groove, groove
1.5-grid region
1.6-source electrode
1.7-drain electrode
1.8-gate electrode
1.9-insulating material is the local insulation layer of silica
The adjacent P type of a-grid region is in the distance that is parallel on the semiconductor chip surface direction
The b-source region is at the width that is parallel on the surface direction
C-surrounds the width of the groove in source region
The width of d-local insulation layer
The thickness of e-local insulation layer
F-local insulation layer leaves the distance of gate electrode
The thickness of g-channel region
H-surrounds the degree of depth of the groove in source region
Distance between the adjacent local insulation layer of i-
The trench gate N raceway groove open type silicon junction field effect transistor schematic diagram that buried local insulation layer is arranged of Fig. 3 embodiment of the invention
2.1-channel region
2.2-source region
2.3-drain region
2.4-fill silica in the groove, groove
2.5-grid region
2.6-source electrode
2.7-drain electrode
2.8-gate electrode
2.9-insulating material is the local insulation layer of silica
The U-source region is at the width that is parallel on the surface direction
The adjacent P type of V-grid region is in the distance that is parallel on the surface direction
W-surrounds the width of the groove in source region
The thickness of X-local insulation layer
The width of Y-local insulation layer
Z-local insulation layer is apart from the distance of silicon chip surface
The thickness of K-channel region
H-source region thickness
Spacing between the adjacent local insulation layer of I-
The surperficial grid N raceway groove open type silicon junction field effect transistor schematic diagram that buried local insulation layer is arranged of Fig. 4 embodiment of the invention
3.1-channel region
3.2-source region
3.3-drain region
3.4-grid region
3.5-source electrode
3.6-drain electrode
3.7-gate electrode
3.8-the insulating material compound local insulation layer that is silicon oxide layer and silicon nitride layer
3.9-the silicon oxide layer in the local insulation layer
3.10-the silicon nitride layer in the local insulation layer
L-is parallel to the width of local insulation layer on the surface direction
Spacing between the adjacent local insulation layer of M-
N-is perpendicular to the thickness of local insulation layer on the surface direction
Spacing between the adjacent grid region of Q-
The thickness of R-channel region
Spacing between S-local insulation layer and the gate electrode
Embodiment:
Embodiment 1: embodiments of the invention 1 are a kind of closed type trench gate N channel silicon junction field effect transistors that buried local oxidation silicon area is arranged, and shown in the accompanying drawing 2 is its section part, and channel region 1.1 is a N type silicon, doping content 5 * 10
15Cm
-3Source region 1.2 is a heavy doping N type silicon, 0.2 micron of thickness, and doping content is higher than 1 * 10
19Cm
-3, heavily doped purpose is to reduce source region series resistance and electrode contact resistance, the gross thickness g of source region and channel region addition is 3 microns; The planar graph in source region is a long strip type; Have groove 1.4 to surround around the source region, gash depth h is 0.5 micron, and groove width c is 0.6 micron, and groove pitch b is for being 0.5 micron; Grid region 1.5 is the p type island region that is arranged in the semiconductor silicon of the poor bottom periphery of ditch, forms PN junction between grid region 1.5 and the channel region 1.1; Spacing a between the adjacent grid region is 0.2 micron, and this makes when adding zero-bias between the grid source PN junction barrier region just can be the abundant pinch off of the raceway groove between the grid region, thereby is closed type JFET, or claims normal cut-off type JFET; The drain region 1.3 doped N-type silicon of attaching most importance to, resistivity 0.003 ohmcm, 150 microns of thickness; Source electrode 1.6 and gate electrode 1.8 are metal silicide titanium silicons, on cover aluminium lamination; Drain electrode 1.7 is a titanium, nickel and silver multilayer metal; Filling megohmite insulant silica on the gate electrode in the groove 1.4; It below all is prior art, what embody feature of the present invention is in the gate electrode 1.8 following silicon buried local oxidation silicon area 1.9 to be arranged, and its width d is 0.5 micron, and thickness e is 0.2 micron, with gate electrode be 0.05 micron apart from f, between the adjacent local insulation layer is 0.3 micron apart from i.Puncture voltage is 35V between the drain-source of this device, FOM (=Rdson.Qg) low about 1/5 than the same size JFET of no buried local oxidation silicon, hang down about 1/3 than corresponding M OSFET.P type island region among the embodiment and N type district exchange, and then are formed with the closed type trench gate P channel silicon junction field effect transistor of buried local insulation layer.The insulating material of local insulation layer also can obtain same effect with silicon nitride or silicon oxynitride in the present embodiment.
Embodiment 2: embodiments of the invention 2 are a kind of open type trench gate N channel silicon junction field effect transistors that buried local oxidation silicon area is arranged, and shown in the accompanying drawing 3 is its section part, and channel region 2.1 is a N type silicon, doping content 1 * 10
16Cm
-3Source region 2.2 is a heavy doping N type silicon, and thickness H is 0.2 micron, and doping content is higher than 1 * 10
19Cm
-3, heavily doped purpose is to reduce source region series resistance and electrode contact resistance; The planar graph in source region is a long strip type; Have groove 2.4 to surround around the source region, gash depth Z is 0.5 micron, and groove width W is 0.6 micron, and groove pitch U is 1 micron; Grid region 2.5 is the p type island region that is arranged in the semiconductor silicon of the poor bottom periphery of ditch, forms PN junction between grid region 2.5 and the channel region 2.1; Spacing V between the adjacent grid region is 0.5 micron, and this makes when adding zero-bias between the grid source PN junction barrier region can not be the abundant pinch off of the raceway groove between the grid region, thereby sizable electric current is arranged between the drain-source, forms open type JFET, or claims normally-ON type JFET; The drain region 2.3 doped N-type silicon of attaching most importance to, resistivity 0.003 ohmcm, 150 microns of thickness; Source electrode 2.6, drain electrode 2.7 and gate electrode 2.8 are metal electrodes; It below all is prior art.What embody feature of the present invention is in the silicon buried local oxidation silicon area 2.9 to be arranged below the gate electrode 2.8, and its width Y is 0.8 micron, and thickness X is 0.35 micron, with the distance of gate electrode be zero, the spacing I between the adjacent local insulation layer is 0.8 micron.Puncture voltage is 30V between the drain-source of this device, and the power loss in 1 megahertz switch when work is low more about 1/3 than the same size JFET of no buried local oxidation silicon, hangs down about 1/2 than corresponding M OSFET.P type island region in the present embodiment and N type district exchange, and then are formed with the open type trench gate P channel silicon junction field effect transistor of buried local insulation layer.The insulating material of local insulation layer also can obtain same effect with silicon nitride or silicon oxynitride in the present embodiment.
Embodiment 3: embodiments of the invention 3 are a kind of open type surface grid N channel silicon junction field effect transistors that buried local insulation layer is arranged, and shown in the accompanying drawing 4 is its section part, and channel region 3.1 is a N type silicon, doping content 1 * 10
14Cm
-3Thickness R is 40 microns; Source region 3.2 is a heavy doping N type silicon, and thickness is 0.5 micron, and doping content is higher than 1 * 10
19Cm
-3, heavily doped purpose is to reduce source region series resistance and electrode contact resistance, the planar graph in source region is a long strip type; Grid region 3.4 is a P type silicon area, forms PN junction between grid region 3.4 and the channel region 3.1; Spacing Q between the adjacent grid region is 10 microns, and this makes when adding zero-bias between the grid source PN junction barrier region can not be the abundant pinch off of the raceway groove between the grid region, thereby sizable electric current is arranged between the drain-source, forms open type JFET, or claims normally-ON type JFET; The drain region 3.3 doped N-type silicon of attaching most importance to, resistivity 0.003 ohmcm, 150 microns of thickness; Source electrode 3.5, drain electrode 3.6 and gate electrode 3.7 are metal electrodes; It below all is prior art.What embody feature of the present invention is in the silicon buried local insulation layer 3.8 to be arranged below the gate electrode 3.7, and its width L is 10 microns, and thickness N is 3 microns, with gate electrode be 3 microns apart from S.Puncture voltage is 600V between the drain-source of this device, and power loss is than the same size JFET low about 1/4 of no buried local oxidation silicon.P type island region in the present embodiment and N type district exchange, and then form P-channel device; The insulating material of local insulation layer uses silica or silicon oxynitride can obtain same effect.
Claims (3)
1, a kind of high-frequency low-consumption power junction type field effect transistor, form by channel region, source region, drain region, grid region and source electrode, gate electrode, drain electrode, source region and drain region lay respectively at the 1st surface and the 2nd surface of silicon chip, channel region is between source region and drain region, the source region is surrounded by the groove from the recessed certain depth in the 1st surface, channel region and to have the source region and the drain region that are higher than the channel region doping content be the semiconductor with first kind of conductivity model; The grid region is to be arranged in channel bottom semiconductor semiconductor, that have second kind of conductivity model on every side; Grid region and channel region joint form PN junction; Source electrode, gate electrode and drain electrode lay respectively on the surface in corresponding each district, it is characterized in that, buried in the semiconductor below each gate electrode have a local insulation layer.
2, high-frequency low-consumption power junction type field effect transistor according to claim 1, it is characterized in that, local insulation layer buried in the semiconductor below each gate electrode has certain distance each other, and the adjacent distance of local insulation layer on the direction that is parallel to the semiconductor chip surface is 0.3 to 10 micron; The local insulation layer is being 0.2 to 3 micron perpendicular to the thickness on the direction on semiconductor chip surface, and the width of local insulation layer on the direction that is parallel to the semiconductor chip surface is 0.5 to 10 micron; The distance that the local insulation layer leaves gate electrode is 0 to 3 micron.
3, high-frequency low-consumption power junction type field effect transistor according to claim 1 and 2 is characterized in that, the insulating material of local insulation layer is a silica, or silicon nitride or silicon oxynitride or silicon oxide layer and silicon nitride layer is compound.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510132111 CN1812132A (en) | 2005-12-16 | 2005-12-16 | High-frequency low-consumption power junction type field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510132111 CN1812132A (en) | 2005-12-16 | 2005-12-16 | High-frequency low-consumption power junction type field effect transistor |
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| Publication Number | Publication Date |
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| CN1812132A true CN1812132A (en) | 2006-08-02 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200510132111 Pending CN1812132A (en) | 2005-12-16 | 2005-12-16 | High-frequency low-consumption power junction type field effect transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100459151C (en) * | 2007-01-26 | 2009-02-04 | 北京工业大学 | Insulation bar dual-pole transistor with the internal transparent collector |
| CN102201454A (en) * | 2010-03-25 | 2011-09-28 | 旺宏电子股份有限公司 | Junction field effect transistor element |
| CN113629128A (en) * | 2020-05-06 | 2021-11-09 | 苏州东微半导体股份有限公司 | Semiconductor device with a plurality of transistors |
-
2005
- 2005-12-16 CN CN 200510132111 patent/CN1812132A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100459151C (en) * | 2007-01-26 | 2009-02-04 | 北京工业大学 | Insulation bar dual-pole transistor with the internal transparent collector |
| CN102201454A (en) * | 2010-03-25 | 2011-09-28 | 旺宏电子股份有限公司 | Junction field effect transistor element |
| CN102201454B (en) * | 2010-03-25 | 2013-12-04 | 旺宏电子股份有限公司 | Junction field effect transistor element |
| CN113629128A (en) * | 2020-05-06 | 2021-11-09 | 苏州东微半导体股份有限公司 | Semiconductor device with a plurality of transistors |
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