CN1822396A - Vertical double diffusion metal oxide semiconductor power device - Google Patents
Vertical double diffusion metal oxide semiconductor power device Download PDFInfo
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- CN1822396A CN1822396A CN 200610020155 CN200610020155A CN1822396A CN 1822396 A CN1822396 A CN 1822396A CN 200610020155 CN200610020155 CN 200610020155 CN 200610020155 A CN200610020155 A CN 200610020155A CN 1822396 A CN1822396 A CN 1822396A
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Abstract
A vertical double diffusion MOS power device belongs to semiconductor power device technology field. Present invention leads in part oxygen burying zone located both sides of device main vertical electrically conductive paths, said oxygen burying zone capable of being done on epitaxial layer, or simultaneously occupying substrate and part area of epitaxial layer, or simultaneously occupying epitaxial layer and P/N zone part area, also occupying simultaneously substrate, epitaxial layer and P/N zone part area, its shape capable of being rectangular, trapezia and ellipse etc, made from silicon dioxide or silicon nitride etc insulating material. Present invention raises voltage withstand and anti irradiation ability through part oxygen burying structure provided high voltage withstand, high electronic-hole pair recombination compound channel. Compared with traditional vertical DMOS, under same conduction resistance, said invention raises voltage withstand by more than 20 per cent, transient state irradiation ability by more than two times, and single particle fault threshold by almost one times. Present invention can make different kinds of high-speed vertical DMOS device with fine anti irradiation and high voltage performance.
Description
Technical field
A kind of vertical double diffusion metal oxide semiconductor power device belongs to the semiconductor power device technology field.
Background technology
Vertical DMOS (V-DMOS) is for the lateral DMOS that early occurs, it transfers to drain region, drift region and channel region in the bottom and body of silicon chip respectively from the surface, the silicon area that tube core takies is dwindled greatly, improved the utilance of silicon chip surface, and the frequency characteristic of device also obtained very big improvement, and power MOS (Metal Oxide Semiconductor) device is a a progressive step to the process that high-power field strides forward from small-power.Vertical DMOS is suitable for making high power device, is the important foundation of power electronic, and characteristics such as power switch, the vertical DMOS device is withstand voltage with its height, low on-resistance are usually used in power integrated circuit and the power integrated system.Fig. 1 is the traditional vertical DMOS device architecture schematic diagram that is produced on the body silicon.Wherein, the 1st, the drain electrode of vertical DMOS device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Double-diffused metal oxide semiconductor (DMOS) device is in the extensive application of environment such as nuclear radiation and space irradiation, to the demands for higher performance of its anti-irradiation.For traditional DMOS device, under transient state irradiation and single particle radiation situation, it is right to produce more electronics-hole in the device.Under the transient state irradiation, electronics-hole is to being swept drain-source, and under the single particle radiation, collect depleted district in electronics-hole, and transient state irradiation effect and single particle radiation effect take place respectively.All will produce bigger transient current in the DMOS device under above-mentioned two kinds of situations, thereby cause component failure, so the anti-irradiation ability of traditional DMOS device is not strong, this has produced very adverse influence to its reliability and environmental suitability.
In order to improve the anti-radiation performance of device, researchers have proposed various measures.Document J.R.Schwank, M.R.Shaneyfelt, etc, " Radiation Effects in SOI Technologies " (irradiation effect on the insulator in the growing single-crystal silicon technology), IEEE TRANSACTION ON NUCLEAR SCIENCE, VOL.50, NO.3, JUNE 2003, adopted a kind of special layout design, as Fig. 2, it is on the basis that keeps traditional lateral MOS structure, claiming to have introduced oxygen buried layer structure-insulator region 4 at the end 1, making source, leakage, grid and the channel region of device then in the monocrystalline silicon on oxygen buried layer.This structure is by introducing electronics-hole part oxygen buried layer higher to compound ability, improve the anti-irradiation ability of device, but this device is subjected to the influence of floater effect, and its anti-single particle radiation ability weakens, so its anti-irradiation ability still can not be improved fully.In addition, because it is at a kind of lateral MOS device, be not suitable for making high power device, and the chip area that tube core takies is too big, the silicon chip surface utilance is not high yet.
Summary of the invention
The object of the present invention is to provide a kind of vertical double diffusion metal oxide semiconductor power device, it has partial SOI (Silicon On Insulator, growth thin single crystal silicon fiml on the insulator) structure, it is a kind of vertical DMOS device with partial SOI structure, compare with traditional vertical DMOS device, have under identical conducting resistance situation, make withstand voltage raising more than 20%, anti-transient state irradiation ability improves more than 2 times, and the single-particle failure threshold improves nearly 1 times characteristics.
Technical solution of the present invention is as follows:
A kind of vertical double diffusion metal oxide semiconductor power device, as shown in Figure 3, comprise substrate 2, epitaxial loayer 3 and p (or n) district 5, epitaxial loayer 3 is positioned at the centre in substrate 2 and p (or n) district 5, it is characterized in that also comprising and partly bury oxide structure, described part is buried the both sides that oxide structure is positioned at the main vertical conduction path of device, is made of insulator region 4.
Need to prove:
(1) the described part that is made of insulator region 4 is buried oxide structure and can be made on the epitaxial loayer 3, also can occupy the subregion of substrate 2 and epitaxial loayer 3 simultaneously, or occupy the subregion in epitaxial loayer 3 and p (or n) district 5 simultaneously, can also occupy the subregion (shown in Fig. 4,5,6) in substrate 2, epitaxial loayer 3 and p (or n) district 5 simultaneously.
(2) the described part that is made of insulator region 4 is buried oxide structure, and its shape can be a rectangle, also can be trapezoidal, non-regular shape such as ellipse (shown in Fig. 7,8).
(3) the described part that is made of insulator region 4 is buried oxide structure and can be made by insulating material such as silicon dioxide or silicon nitrides.
(4) a kind of vertical double diffusion metal oxide semiconductor power device of the present invention can adopt semi-conducting material manufacturings such as body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
Operation principle of the present invention:
A kind of vertical double diffusion metal oxide semiconductor power device provided by the invention, it is good inadequately to overcome the anti-irradiation ability of traditional vertical DMOS device, and withstand voltage not high enough shortcoming obtains anti-preferably irradiation ability and higher withstand voltage.Here be that the vertical DMOS of silicon dioxide is example (as Fig. 3) with the part buried oxide region, operation principle of the present invention is described.
Be subjected under the irradiation situation at device, part bury oxide structure be electronics-hole of producing of irradiation to bigger recombination probability is provided, effectively reduce the irradiation electric current, reach the purpose of the anti-irradiation ability of enhance device.Under the transient state irradiation situation, in the device because electronics-hole that irradiation produces is swept Lou/source quilt, thereby produces transient current.Because the design feature of silicon dioxide itself has the huge complex centre of quantity in its body, so the right recombination probability in the electronics-hole of transient state irradiation generation is bigger in the silicon dioxide, thereby the transient current that silicon dioxide shows under transient state irradiation is very little; Under the single particle radiation situation, the high energy particle of incident will be right along the highdensity electronics-hole of its trajectory generation, and electronics-hole that irradiation produces is to its depletion layer on every side that can neutralize again.If depletion layer further disappears, then owing to lose shielding action, the electric field that positive bias produces will be advanced to substrate interior, make the drain terminal electric current reach maximum in a flash.Owing to the recombination probability that electronics-hole in the silicon dioxide is right is higher, make a large amount of electronics-holes that produce in the irradiation to just compound before depleted layer is collected, the effective track length that is device collection electronics has reduced, so the transient current that vertical DMOS provided by the invention produces under the single particle radiation situation significantly reduces.Incide device inside in very short time at single-particle, because the existence that part is buried oxide structure, partial SOI vertical DMOS internal temperature only is slightly to increase, and slowly recovers then, therefore is not easy to take place thermal breakdown, so its inefficacy thresholding increases.
Can get by MEDICI emulation, under the transient state irradiation situation, irradiation dose is 1 * 10
3Rad (Si)-1 * 10
7In rad (Si) scope, vertical DMOS device with partial SOI structure of the present invention (hereinafter to be referred as: the partial SOI vertical DMOS) and traditional vertical DMOS device (hereinafter to be referred as: the drain terminal that transient state irradiation traditional vertical DMOS) produces induces the relation of peak current and transient state irradiation shown in Fig. 9,10, as seen from the figure, the more traditional vertical DMOS of the anti-transient state irradiation ability of partial SOI vertical DMOS improves more than 2 times.Under the single particle radiation situation, for gold particle, linear transfer can (Linear Energy Transfer LET) induces current impulse peak value relation as shown in figure 10 with the irradiation that produces.As seen from the figure, single particle radiation is far smaller than influence to traditional vertical DMOS device to the influence of partial SOI vertical DMOS, tests with yttrium, bromine, indium, four kinds of particle incidents of copper, also leads to the same conclusion.Irradiation induced current impulse shown in Figure 12,13 before and after single-particle burnt, and as seen from the figure, the more traditional vertical DMOS of partial SOI vertical DMOS failure threshold improves more than 1 times.As seen, structure provided by the invention can reduce the irradiation electric current significantly after oxide structure is buried to the part of compound ability in the high electronics-hole of introducing, and the anti-irradiation ability of device is improved.According to structure provided by the invention, the anti-transient state irradiation ability of device is improved more than 2 times, the single-particle failure threshold improves more than 1 times.
The present invention is except significantly improving the anti-irradiation ability of device, and the advantage that also has is that conducting resistance changes not quite, and device withstand voltage improves.After the introducing part was buried oxide structure, break-over of device resistance increased to some extent than traditional structure, but changed not quite, and the doping content of suitably regulating the outer can make partial SOI vertical DMOS device with traditional vertical DMOS device identical conducting resistance be arranged, even littler.Because the introducing that part is buried oxide structure is equivalent to be equivalent to increase a TRENCH structure in this structure, makes the drift region elongated, so device withstand voltage improves.
Analyze the wide height can get the part oxygen buried layer and conducting resistance, withstand voltage relation such as Figure 14,15 by ISE, as seen from the figure, get H=7 μ m, during L=5 μ m, the conducting resistance of partial SOI vertical DMOS is identical with IRF120, has withstand voltagely improved 30V than IRF120.As seen, according to structure provided by the invention, can reach and make device withstand voltage than the raising of traditional vertical DMOS more than 20% under the equal conducting resistance.
In sum, a kind of vertical double diffusion metal oxide semiconductor power device provided by the invention, by burying oxide structure, the passage of compound ability is improved device withstand voltage and anti-irradiation ability thereof so that high withstand voltage, a high electronics-hole to be provided in the inner part of introducing of power device.Compare with traditional vertical DMOS, can reach under the equal conducting resistance, withstand voltage raising is more than 20%, and anti-transient state irradiation ability improves more than 2 times, and the single-particle failure threshold improves nearly 1 times.Therefore, adopt the present invention can make anti-irradiation, high pressure, the high speed vertical DMOS device of various function admirables.
Description of drawings
Fig. 1 is traditional vertical DMOS structural representation
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 2 is the lateral MOS structural representation with soi structure
Wherein, the 1st, drain electrode, the 2nd, p (or n) substrate zone, the 4th, insulator region, the 6th, n
+(or p
+) district, the 8th, source electrode, the 9th, grid, the 10th, n
+(or p
+) district.
Fig. 3 is the vertical DMOS device architecture schematic diagram that part is buried oxide structure of introducing provided by the invention
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 9th, source electrode, the 9th, grid.
Fig. 4 is that part is buried oxide structure and is made in situation on the subregion of substrate 2 and epitaxial loayer 3 simultaneously
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 5 is that part is buried oxide structure and is made in situation on the subregion in epitaxial loayer 3 and p (or n) district 6 simultaneously
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 6 is that part is buried oxide structure and is made in situation on the subregion in substrate 2, epitaxial loayer 3 and p (or n) district 6 simultaneously
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 7 is that part buried oxide region of the present invention is trapezoidal situation
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 8 is that part buried oxide region of the present invention is trapezoidal situation
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, insulator region, the 5th, p (or n) district, the 6th, n
+(or p
+) district, the 7th, p
+(or n
+) district, the 8th, source electrode, the 9th, grid.
Fig. 9 is a device when being in OFF state, under the transient state irradiation situation, current peak and irradiation dose concern schematic diagram
Wherein, curve 11,12 be respectively traditional vertical DMOS and partial SOI vertical DMOS under transient state irradiation, the relation curve of current peak and irradiation dose.As seen from the figure, irradiation dose is respectively 5 * 10
3Rad (Si), 5 * 10
4During rad (Si), the drain terminal peak current of traditional vertical DMOS is respectively 1.55 * 10
-4A/ μ m and 0.34A/ μ m, the drain terminal peak current of partial SOI vertical DMOS is respectively 8.73 * 10
-5A/ μ m and 9.7 * 10
-4A/ μ m.Device is under the OFF state situation as can be known, and the ability of the anti-transient state irradiation of partial SOI vertical DMOS is greater than traditional vertical DMOS device.
Figure 10 is a device when being in ON state, under the transient state irradiation situation, current peak and irradiation dose concern schematic diagram
Wherein, curve 13,14 be respectively traditional vertical DMOS and partial SOI vertical DMOS under transient state irradiation, the relation curve of current peak and irradiation dose.As seen from the figure, irradiation dose is respectively 2 * 10
4Rad (Si), 5 * 10
5During rad (Si), the drain terminal peak current of traditional vertical DMOS is respectively 8.3 * 10
-4A/ μ m and 0.08A/ μ m, the drain terminal peak current of partial SOI vertical DMOS is respectively 5.3 * 10
-4A/ μ m and 0.042A/ μ m.Device is under the ON state situation as can be known, and the ability of the anti-transient state irradiation of partial SOI vertical DMOS is also greater than traditional vertical DMOS device.As we know from the figure, produce 5 * 10
-4The drain terminal current peak that A/ μ m, 0.08A/ μ m are onesize, the partial SOI vertical DMOS needs 2 * 10 respectively
4Rad (Si) and, 5 * 10
5The irradiation dose of rad (Si), traditional vertical DMOS needs 1 * 10 respectively
4Rad (Si) and 2 * 10
6The irradiation dose of rad (Si), the more conventional traditional DMOS device of the anti-transient state irradiation ability of partial SOI vertical DMOS improves more than 2 times as can be known.
Figure 11 is under single-particle (gold particle) condition of incidence, and the irradiation of linear transmission of power of particle and generation induces the current impulse peak value and concerns schematic diagram
Wherein, curve the 15, the 16th, when traditional vertical DMOS device was in OFF state and ON state respectively, irradiation induced peak current and gold particle linear threshold energy relation curve; Curve the 17, the 18th, when partial SOI vertical DMOS device was in OFF state and ON state respectively, irradiation induces peak current and the gold particle linear threshold can relation curve.As seen from the figure, in the tradition vertical DMOS, in linear threshold can be for experiment during minimum value 0.145pc/ μ m, the peak current of ON state situation is 0.0036A/ μ m, the peak current of OFF state situation is 0.0133A/ μ m, and during maximum 0.677pc/ μ m, the peak current of ON state situation is 0.27A/ μ m in linear threshold can be for experiment, the peak current of OFF state situation is 0.84A/ μ m, and its peak current obviously increases.And in the partial SOI vertical DMOS, it is very faint that peak current changes, and can ignore with respect to the absolute peak electric current of traditional vertical DMOS.Therefore, single particle radiation is far smaller than traditional DMOS device to the influence of partial SOI vertical DMOS as can be known.
Single-particle takes place to burn pre irradiation and induce the current impulse schematic diagram in Figure 12
Wherein, curve 19,20 is respectively single-particle to take place in traditional vertical DMOS and the partial SOI vertical DMOS burn pre irradiation and induce the current impulse profile.Before experimental record obtained taking place single-particle and burns, the linear threshold of incoming particle can be respectively 1.27pc/ μ m and 2.8pc/ μ m in traditional vertical DMOS and the partial SOI vertical DMOS.
Figure 13 is that irradiation induced the current impulse schematic diagram after the generation single-particle burnt
Wherein, curve 21,22 is respectively that irradiation induced the current impulse profile after the generation single-particle burnt in traditional vertical DMOS and the partial SOI vertical DMOS.After experimental record obtained taking place single-particle and burns, the linear threshold of incoming particle can be respectively 1.29pc/ μ m and 3pc/ μ m in traditional vertical DMOS and the partial SOI vertical DMOS.Comprehensive Figure 12,13 partial SOI vertical DMOS failure threshold as can be known is about more traditional vertical DMOS raising more than 1 times.
Figure 14 is that the wide height and the conducting resistance of oxygen buried layer concerns schematic diagram
The width and the conducting resistance relation curve of oxygen buried layer when wherein, curve the 23,24,25,26, the 27th, oxygen buried layer height are respectively 4 μ m, 5 μ m, 6 μ m, 7 μ m, 8 μ m.As seen from the figure, get H=7 μ m, during L=5 μ m, the conducting resistance of partial SOI vertical DMOS is identical with IRF120.(index of the vertical DMOS commercial product IRF120 series of IR company is: puncture voltage 120V; Conducting resistance 0.05 Ω * μ m.)
Figure 15 is that the wide height and the device withstand voltage of oxygen buried layer concerns schematic diagram
When wherein, curve the 28,29,30,31, the 32nd, oxygen buried layer height are respectively 4 μ m, 5 μ m, 6 μ m, 7 μ m, 8 μ m the width of oxygen buried layer with the device withstand voltage relation curve.As seen from the figure, get H=7 μ m, during L=5 μ m, the withstand voltage of partial SOI vertical DMOS improved 30V than IRF120, promptly improved more than 20%.
Embodiment
Adopt part of the present invention to bury oxide structure, can obtain anti-irradiation, high pressure, the high-speed power device of function admirable.Can be applied to common power devices such as bilateral diffusion field-effect tranisistor, insulated gate bipolar power transistor, electrostatic induction transistor, PN diode.Adopt the device that partly buries oxide structure can be used for Aero-Space, nuclear environment and other fields that the device anti-radiation performance is had relatively high expectations.Along with development of semiconductor, adopt the present invention can also make more anti-irradiation, high pressure, high-speed power device.
Introduce part and bury the new vertical DMOS power device of oxide structure, as shown in Figure 2, comprise drain electrode 1, n
+(or p
+) substrate zone 2, n
-(or p
-) epitaxial loayer 3, p (or n) district 5, n
+(or p
+) district 6, p
+(or n
+) district 7, source electrode 8, grid 9.It is characterized in that it comprises that also part buries oxide structure, it is to be made of insulator region 4 that part is buried oxide structure.
Can adopt the bonding technology first during concrete enforcement, more together with it and another wafer bonding behind the silicon chip partial oxidation.Also can adopt the pre-oxygen technology of injecting, oxygen be carried out in the subregion of silicon chip inject, to form the part buried oxide region.
In implementation process, can be as the case may be, under the constant situation of basic structure, carry out certain accommodation design.For example:
Shown in Figure 4 is that the part buried oxide region is made on the subregion of substrate 2 and epitaxial loayer 3 simultaneously.
Shown in Figure 5 is that the part buried oxide region is made on the subregion in epitaxial loayer 3 and p (or n) district 6 simultaneously.
Shown in Figure 6 is that the part buried oxide region is made on the subregion in substrate 2, epitaxial loayer 3 and p (or n) district 6 simultaneously.
Part buried oxide region shown in Figure 7, the insulator region 4 that it comprises be shaped as trapezium structure.
Part buried oxide region shown in Figure 8, the insulator region 4 that it comprises be shaped as ellipsoidal structure.
Can also replace silicon dioxide with insulating material such as silicon nitrides, form the part oxygen buried layer;
Semi-conducting materials such as also available carborundum, GaAs, indium phosphide or germanium silicon replace body silicon when making device.
Claims (5)
1, a kind of vertical double diffusion metal oxide semiconductor power device, comprise substrate (2), epitaxial loayer (3) and p/n district (5), epitaxial loayer (3) is positioned at the centre of substrate (2) and p/n district (5), it is characterized in that also comprising and partly bury oxide structure, described part is buried the both sides that oxide structure is positioned at the main vertical conduction path of device, is made of insulator region (4).
2, a kind of vertical double diffusion metal oxide semiconductor power device according to claim 1, it is characterized in that, the described part that is made of insulator region (4) is buried oxide structure and can be made on the epitaxial loayer (3), also can occupy the subregion of substrate (2) and epitaxial loayer (3) simultaneously, or occupy the subregion of epitaxial loayer (3) and p/n district (5) simultaneously, can also occupy the subregion of substrate (2), epitaxial loayer (3) and p/n district (5) simultaneously.
3, a kind of vertical double diffusion metal oxide semiconductor power device according to claim 2 is characterized in that, the described part that is made of insulator region (4) is buried oxide structure, and its shape can be a rectangle, also can be trapezoidal, non-regular shape such as ellipse.
4, a kind of vertical double diffusion metal oxide semiconductor power device according to claim 2 is characterized in that, the described part that is made of insulator region (4) is buried oxide structure and can be made by insulating material such as silicon dioxide or silicon nitrides.
5, a kind of vertical double diffusion metal oxide semiconductor power device according to claim 1, it is characterized in that described a kind of vertical double diffusion metal oxide semiconductor power device can adopt semi-conducting material manufacturings such as body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901829A (en) * | 2010-05-07 | 2010-12-01 | 深圳深爱半导体有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN102760770A (en) * | 2012-06-11 | 2012-10-31 | 电子科技大学 | Single particle irradiation-resistant super junction VDMOS device |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Anti-single-particle-radiation MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) apparatus and preparation method |
| CN107425070A (en) * | 2017-07-27 | 2017-12-01 | 电子科技大学 | A kind of half super node MOSFET with assisted oxidation buried regions |
| CN108063160A (en) * | 2017-12-18 | 2018-05-22 | 深圳市晶特智造科技有限公司 | Vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
-
2006
- 2006-01-16 CN CN 200610020155 patent/CN1822396A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901829A (en) * | 2010-05-07 | 2010-12-01 | 深圳深爱半导体有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN102760770A (en) * | 2012-06-11 | 2012-10-31 | 电子科技大学 | Single particle irradiation-resistant super junction VDMOS device |
| CN102969316A (en) * | 2012-11-20 | 2013-03-13 | 电子科技大学 | Anti-single-particle-radiation MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) apparatus and preparation method |
| CN107425070A (en) * | 2017-07-27 | 2017-12-01 | 电子科技大学 | A kind of half super node MOSFET with assisted oxidation buried regions |
| CN107425070B (en) * | 2017-07-27 | 2020-05-01 | 电子科技大学 | Half surpasses knot MOSFET with supplementary buried oxide layer |
| CN108063160A (en) * | 2017-12-18 | 2018-05-22 | 深圳市晶特智造科技有限公司 | Vertical bilateral diffusion field-effect tranisistor and preparation method thereof |
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