CN101901829A - Electrostatic discharge protection structure and manufacturing method thereof - Google Patents
Electrostatic discharge protection structure and manufacturing method thereof Download PDFInfo
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- CN101901829A CN101901829A CN 201010172923 CN201010172923A CN101901829A CN 101901829 A CN101901829 A CN 101901829A CN 201010172923 CN201010172923 CN 201010172923 CN 201010172923 A CN201010172923 A CN 201010172923A CN 101901829 A CN101901829 A CN 101901829A
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Abstract
The invention relates to an electrostatic discharge protection structure. The electrostatic discharge protection structure is connected in series between a grid and a source of a metal oxide semiconductor field effect transistor, and has an NPN triode structure or a PNP triode structure. The invention also relates to a method for manufacturing a vertical double-diffusion metal oxide semiconductor field effect transistor which has the electrostatic discharge protection structure. By serially connecting the electrostatic discharge protection structure which has the NPN triode structure or the PNP triode structure between the grid and the source of MOSFET, the electrostatic discharge structure makes the potential difference between the grid and the source have insulation characteristics before exceeding the breakdown voltage of the triode structure. When the electrostatic voltage exceeds the breakdown voltage, the triode structure is conducted to discharge the static so as to prevent the static from breaking down a grid oxide layer and damaging the device. Meanwhile, the electrostatic discharge protection structure has bidirectional insulation characteristics, namely in spite of the grid potential, the grid potential is in an insulation state relative to the source so as to avoid the influence on the normal working state of the device.
Description
[technical field]
The present invention relates to semiconductor device, (Electro-Static Discharge, ESD) the protection structure also relates to a kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOSFET) with esd protection structure to relate in particular to a kind of static release.
[background technology]
(Electro-Static Discharge ESD) can cause semiconductor components and devices, for example the damage of metal oxide semiconductor field effect tube (MOSFET) in static release.Especially the gate oxide of vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOSFET) is thinner, be generally less than 1000 dusts, the breakdown potential that can bear is forced down, has only 80～120V, and general human body discharge mode (Human Body Model, HBM) electrostatic potential that is produced can reach 2000V, causes the gate oxide damage of VDMOSFET easily or punctures, and causes the reliability of device to go wrong even directly burns device.Raising along with the device reliability requirement, particularly in the devices field of some low threshold voltages, require the thickness of gate oxide to have only the hundreds of dust, VDMOSFET is improved the requirement that static discharges resistivity, the electric capacity ability that only relies on device itself can't guarantee reliability.
[summary of the invention]
Based on this, be necessary to provide a kind of metal oxide semiconductor field effect tube that can prevent to damage because of static discharges, improve the electrostatic discharge protection structure of device reliability.
A kind of electrostatic discharge protection structure, described electrostatic discharge protection structure are connected between the grid and source electrode of metal oxide semiconductor field effect tube, and described electrostatic discharge protection structure is NPN three-stage structure or PNP three-stage structure.
Preferably, described metal oxide semiconductor field effect tube is a vertical double-diffusion metal-oxide-semiconductor field effect transistor, and described NPN three-stage structure and PNP three-stage structure are to realize by the doping that the polysilicon gate to described vertical double-diffusion metal-oxide-semiconductor field effect transistor itself carries out N type and p type impurity.
Preferably, described vertical double-diffusion metal-oxide-semiconductor field effect transistor comprises substrate, epitaxial loayer on the substrate, well region in the epitaxial loayer, injection region in the well region, the gate oxide of epi-layer surface, the polysilicon layer on the gate oxide, the protective layer on polysilicon layer surface, and the electrode on the protective layer; Described polysilicon layer comprises polysilicon gate and polysilicon gate; Described protective layer comprises the gate protection layer on polysilicon gate surface and the grid protective layer of polycrystalline silicon gate surface; Described electrode comprises source electrode and gate electrode, described source electrode is positioned at the protective layer that contacts and coat described polysilicon gate and polycrystalline silicon gate surface on the well region, with the injection region, and described gate electrode is positioned on the polysilicon gate and runs through the protective layer on polysilicon gate surface and contact with polysilicon gate; Described polysilicon gate comprises by N type district and the p type island region that mix to form, and specifically is that two N type districts are clipped in the middle a p type island region and form the NPN three-stage structure, or two p type island regions are clipped in the middle a N type district and form the PNP three-stage structure; The two ends of described NPN three-stage structure and PNP three-stage structure contact with the source electrode with gate electrode respectively.
Preferably, the puncture voltage of described NPN three-stage structure and PNP three-stage structure is less than the puncture voltage of described gate oxide.
Preferably, described electrode surface is provided with silicon nitride layer.
Preferably, the composition of described protective layer is phosphorosilicate glass or boron-phosphorosilicate glass.
Preferably, described vertical double-diffusion metal-oxide-semiconductor field effect transistor is a N type field effect transistor: described substrate is N
+Substrate, described epitaxial loayer are N
-Epitaxial loayer, described well region are P type well region, and described injection region is N
+Injection region, the composition of described gate oxide are silicon dioxide.
A kind of manufacture method with vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure also is provided.
A kind of manufacture method with vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure comprises the following steps: the electrostatic discharge protection structure of connecting between the grid of described metal oxide semiconductor field effect tube and source electrode; Described electrostatic discharge protection structure is NPN three-stage structure or PNP three-stage structure, and described NPN three-stage structure and PNP three-stage structure are to realize by the doping that the polysilicon gate to described vertical double-diffusion metal-oxide-semiconductor field effect transistor itself carries out N type and p type impurity; Described manufacture method specifically may further comprise the steps: at the substrate growing epitaxial layers; The oxide layer of on described epitaxial loayer, growing; In described epitaxial loayer, inject p type impurity and form well region; Deposit polysilicon layer on described oxide layer; Doped N-type and p type impurity form the injection region, and form described NPN three-stage structure or PNP three-stage structure; Specifically be in described well region, to inject N type impurity, form the injection region, and in polysilicon layer, inject N type and p type impurity, form described NPN three-stage structure or PNP three-stage structure; Form protective layer at described polysilicon layer surface deposition; The described protective layer of etching forms electrode by sputter after forming fairlead, and described electrode comprises source electrode and the gate electrode that is separated from each other; Specifically to be two N type districts with a p type island region be clipped in the middle forms the NPN three-stage structure for described NPN three-stage structure and PNP three-stage structure, or two p type island regions are clipped in the middle a N type district and form the PNP three-stage structure; The two ends of described NPN three-stage structure and PNP three-stage structure contact with the source electrode with gate electrode respectively.
Preferably, further comprising the steps of: at electrode surface deposit silicon nitride layer, and the described silicon nitride layer of etching, form the pressure welding mouth at described electrode surface.
Preferably, described vertical double-diffusion metal-oxide-semiconductor field effect transistor is a N type field effect transistor: described substrate is N
+Substrate, described epitaxial loayer are N
-Epitaxial loayer, described well region are P type well region, and described injection region is N
+Injection region, the composition of described protective layer are phosphorosilicate glass or boron-phosphorosilicate glass, and the composition of described oxide layer is a silicon dioxide.
Above-mentioned static releasing structure by the electrostatic discharge protection structure of series connection NPN or PNP three-stage structure between the grid of MOSFET and source electrode, makes electrical potential difference between grid and the source electrode before surpassing the puncture voltage of three-stage structure, presents insulation characterisitic; When electrostatic potential surpassed puncture voltage, the three-stage structure conducting made static obtain discharging, and avoids the electrostatic breakdown gate oxide that device is caused damage.And what this electrostatic discharge protection structure presented is two-way insulation characterisitic; promptly no matter grid potential no matter positive and negative (and the absolute value of grid and source potential difference is less than puncture voltage) is state of insulation with respect to source electrode, avoid the normal operating conditions of device is impacted.And just on the basis of traditional handicraft, polysilicon doping technology is made change, simple to operate and cost is low.
[description of drawings]
Fig. 1 is the structural representation of vertical double-diffusion metal-oxide-semiconductor field effect transistor among the embodiment;
Fig. 2 is the generalized section of vertical double-diffusion metal-oxide-semiconductor field effect transistor among the embodiment;
Fig. 3 is the flow chart of manufacture method that has the vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure among the embodiment.
[embodiment]
Electrostatic discharge (ESD) of the present invention protection structure is to form by between the grid of MOSFET and source electrode NPN (or PNP) three-stage structure being set, and promptly NPN (or PNP) three-stage structure is connected between the grid and source electrode of MOSFET.
Below an embodiment of (VDMOSFET) comes the present invention is made clearly explanation in the vertical double-diffusion metal-oxide-semiconductor field effect transistor by esd protection structure is applied in.Fig. 1 is the structure chart of vertical double-diffusion metal-oxide-semiconductor field effect transistor among this embodiment.Vertical double-diffusion metal-oxide-semiconductor field effect transistor comprises grid 10, and source electrode 20 and drain electrode 30 are provided with esd protection structure 40 between grid 10 and the source electrode 20, and this esd protection structure 40 is three-stage structures of a NPN (or PNP).
In a preferred embodiment, the three-stage structure of electrostatic discharge protection structure 40 is to carry out N type and P type doping realization by the polysilicon gate to VDMOSFET itself.
Fig. 2 is the generalized section of vertical double-diffusion metal-oxide-semiconductor field effect transistor among the embodiment.Comprise substrate 110, the epitaxial loayer 120 on the substrate 110, the well region 122 in the epitaxial loayer 120; injection region 124 in the well region 122, the gate oxide 130 on epitaxial loayer 120 surfaces, the polysilicon layer on the gate oxide 130; the protective layer on polysilicon layer surface, and the electrode on the protective layer.
Polysilicon layer comprises polysilicon gate 150 and polysilicon gate 140.Protective layer comprises the gate protection layer 170 on polysilicon gate 150 surfaces and the grid protective layer 160 on polysilicon gate 140 surfaces.Electrode comprises source electrode 180 and the gate electrode 190 that is separated from each other; described source electrode 180 is positioned on the well region 122, contact and coat the grid protective layer 160 on described polysilicon gate 140 and polysilicon gate 140 surfaces with injection region 124, and described gate electrode 190 is positioned on the polysilicon gate 150 and runs through the gate protection layer 170 on polysilicon gate 150 surfaces and contact with polysilicon gate 150.
Polysilicon gate 150 comprises N type district and the p type island region that forms by mixing, and specifically can be as shown in Figure 2, and N type district 152 and N type district 156 are clipped in the middle p type island region 154, forms the NPN three-stage structure.Also can be that two p type island regions are clipped in the middle a N type district in other embodiments, form the PNP three-stage structure.The two ends of NPN (or PNP) three-stage structure contact with source electrode 180 with gate electrode 190 respectively, have so just formed the structure that is connected between MOSFET grid and the source electrode.
In a preferred embodiment, the material of protective layer adopts boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
In a preferred embodiment, can lay silicon nitride layer, device is isolated from the outside, play a protective role at electrode surface.
The composition of gate oxide 130 is a silicon dioxide.When above-mentioned vertical double-diffusion metal-oxide-semiconductor field effect transistor was N type field effect transistor, substrate 110 was N
+Substrate, epitaxial loayer 120 is N
-Epitaxial loayer, well region 122 are P type well region, and injection region 124 is N
+The injection region.
Can realize puncture voltage BV by regulating doping content or other parameters of polysilicon gate to NPN (or PNP) three-stage structure
GS(this puncture is recoverable) adjusted, to adapt to the needs of device, BV
GSShould be less than the puncture voltage V of gate oxide
B
The manufacturing of VDMOSFET with above-mentioned esd protection structure is similar to traditional manufacturing process, when just carrying out polysilicon doping behind the deposit polysilicon layer, should carry out the doping that the P type carries out the N type again.Fig. 3 is the flow chart of manufacture method that has the VDMOSFET of esd protection structure among the embodiment.Comprise the following steps:
S10: at the substrate growing epitaxial layers.
S20: the oxide layer of on epitaxial loayer, growing.
S30: in epitaxial loayer, inject p type impurity and form well region.
S40: deposit polysilicon layer on oxide layer.
S50: inject N type and p type impurity and form injection region and three-stage structure.Specifically be in well region, to inject N type impurity, form the injection region, and in polysilicon layer, inject N type and p type impurity, form NPN three-stage structure or PNP three-stage structure.
S60: form protective layer at the polysilicon layer surface deposition.
S70: the described protective layer of etching forms electrode by sputter after forming fairlead, comprises the source electrode and the gate electrode that are separated from each other.
In a preferred embodiment, also be included in electrode surface deposit silicon nitride layer, and etches both silicon nitride layer, in the step of electrode surface formation pressure welding mouth.
The composition of above-mentioned oxide layer is a silicon dioxide, and the composition of protective layer is boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG).
When above-mentioned vertical double-diffusion metal-oxide-semiconductor field effect transistor was N type field effect transistor, substrate was N
+Substrate, epitaxial loayer are N
-Epitaxial loayer, well region are P type well region, and the injection region is N
+The injection region.
Specifically to be two N type districts with a p type island region be clipped in the middle NPN (or PNP) three-stage structure forms NPN three-stage structure (or two p type island regions a N type district is clipped in the middle form the PNP three-stage structure).The two ends of described NPN (or PNP) three-stage structure contact with the source electrode with gate electrode respectively.
Above-mentioned static releasing structure by the electrostatic discharge protection structure of series connection NPN or PNP three-stage structure between the grid of MOSFET and source electrode, makes electrical potential difference between grid and the source electrode before surpassing the puncture voltage of three-stage structure, presents insulation characterisitic; When electrostatic potential surpassed puncture voltage, the three-stage structure conducting made static obtain discharging, and avoids the electrostatic breakdown gate oxide that device is caused damage.And what this electrostatic discharge protection structure presented is two-way insulation characterisitic; promptly no matter grid potential no matter positive and negative (and the absolute value of grid and source potential difference is less than puncture voltage) is state of insulation with respect to source electrode, avoid the normal operating conditions of device is impacted.And just on the basis of traditional handicraft, polysilicon doping technology is made change, simple to operate and cost is low.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an electrostatic discharge protection structure is characterized in that, described electrostatic discharge protection structure is connected between the grid and source electrode of metal oxide semiconductor field effect tube, and described electrostatic discharge protection structure is NPN three-stage structure or PNP three-stage structure.
2. electrostatic discharge protection structure according to claim 1; it is characterized in that; described metal oxide semiconductor field effect tube is a vertical double-diffusion metal-oxide-semiconductor field effect transistor, and described NPN three-stage structure and PNP three-stage structure are to realize by the doping that the polysilicon gate to described vertical double-diffusion metal-oxide-semiconductor field effect transistor itself carries out N type and p type impurity.
3. electrostatic discharge protection structure according to claim 2, it is characterized in that, described vertical double-diffusion metal-oxide-semiconductor field effect transistor comprises substrate, injection region in the well region in the epitaxial loayer on the substrate, epitaxial loayer, well region, the gate oxide of epi-layer surface, polysilicon layer on the gate oxide, the protective layer on polysilicon layer surface, and the electrode on the protective layer;
Described polysilicon layer comprises polysilicon gate and polysilicon gate; Described protective layer comprises the gate protection layer on polysilicon gate surface and the grid protective layer of polycrystalline silicon gate surface; Described electrode comprises source electrode and gate electrode, described source electrode is positioned at the protective layer that contacts and coat described polysilicon gate and polycrystalline silicon gate surface on the well region, with the injection region, and described gate electrode is positioned on the polysilicon gate and runs through the protective layer on polysilicon gate surface and contact with polysilicon gate;
Described polysilicon gate comprises by N type district and the p type island region that mix to form, and specifically is that two N type districts are clipped in the middle a p type island region and form the NPN three-stage structure, or two p type island regions are clipped in the middle a N type district and form the PNP three-stage structure; The two ends of described NPN three-stage structure and PNP three-stage structure contact with the source electrode with gate electrode respectively.
4. electrostatic discharge protection structure according to claim 3 is characterized in that, the puncture voltage of described NPN three-stage structure and PNP three-stage structure is less than the puncture voltage of described gate oxide.
5. electrostatic discharge protection structure according to claim 3 is characterized in that described electrode surface is provided with silicon nitride layer.
6. electrostatic discharge protection structure according to claim 3 is characterized in that, the composition of described protective layer is phosphorosilicate glass or boron-phosphorosilicate glass.
7. according to any described electrostatic discharge protection structure among the claim 1-6, it is characterized in that described vertical double-diffusion metal-oxide-semiconductor field effect transistor is a N type field effect transistor: described substrate is N
+Substrate, described epitaxial loayer are N
-Epitaxial loayer, described well region are P type well region, and described injection region is N
+The injection region; The composition of described gate oxide is a silicon dioxide.
8. manufacture method with vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure comprises the following steps: the electrostatic discharge protection structure of connecting between the grid of described metal oxide semiconductor field effect tube and source electrode; Described electrostatic discharge protection structure is NPN three-stage structure or PNP three-stage structure, and described NPN three-stage structure and PNP three-stage structure are to realize by the doping that the polysilicon gate to described vertical double-diffusion metal-oxide-semiconductor field effect transistor itself carries out N type and p type impurity; Described manufacture method specifically may further comprise the steps:
At the substrate growing epitaxial layers;
The oxide layer of on described epitaxial loayer, growing;
In described epitaxial loayer, inject p type impurity and form well region;
Deposit polysilicon layer on described oxide layer;
Doped N-type and p type impurity form the injection region, and form described NPN three-stage structure or PNP three-stage structure; Specifically be in described well region, to inject N type impurity, form the injection region, and in polysilicon layer, inject N type and p type impurity, form described NPN three-stage structure or PNP three-stage structure;
Form protective layer at described polysilicon layer surface deposition;
The described protective layer of etching forms electrode by sputter after forming fairlead, and described electrode comprises source electrode and the gate electrode that is separated from each other;
Specifically to be two N type districts with a p type island region be clipped in the middle forms the NPN three-stage structure for described NPN three-stage structure and PNP three-stage structure, or two p type island regions are clipped in the middle a N type district and form the PNP three-stage structure; The two ends of described NPN three-stage structure and PNP three-stage structure contact with the source electrode with gate electrode respectively.
9. the manufacture method with vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure according to claim 8 is characterized in that, and is further comprising the steps of:
At electrode surface deposit silicon nitride layer, and the described silicon nitride layer of etching, the pressure welding mouth formed at described electrode surface.
10. according to Claim 8 or 9 described manufacture methods with vertical double-diffusion metal-oxide-semiconductor field effect transistor of electrostatic discharge protection structure; it is characterized in that described vertical double-diffusion metal-oxide-semiconductor field effect transistor is a N type field effect transistor: described substrate is N
+Substrate, described epitaxial loayer are N
-Epitaxial loayer, described well region are P type well region, and described injection region is N
+The injection region; The composition of described protective layer is phosphorosilicate glass or boron-phosphorosilicate glass, and the composition of described oxide layer is a silicon dioxide.
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| CN 201010172923 CN101901829A (en) | 2010-05-07 | 2010-05-07 | Electrostatic discharge protection structure and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867832A (en) * | 2014-02-21 | 2015-08-26 | 北大方正集团有限公司 | Manufacturing method of vertical double-diffusion metal oxide semiconductor field effect transistor |
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| CN1630079A (en) * | 2003-12-15 | 2005-06-22 | 三星电子株式会社 | Electrostatic discharge protection device and manufacturing method thereof |
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| CN1964070A (en) * | 2006-11-15 | 2007-05-16 | 四川绵阳信益科技有限公司 | A vertical dual diffused MOS power device protected by polysilicon ESD structure |
| CN100399583C (en) * | 2001-05-22 | 2008-07-02 | 通用半导体公司 | DMOS with zener diode for ESD protection |
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| CN100399583C (en) * | 2001-05-22 | 2008-07-02 | 通用半导体公司 | DMOS with zener diode for ESD protection |
| TWI231593B (en) * | 2003-10-31 | 2005-04-21 | Advanced Power Electronics Cor | Line skeleton of power MOS product having gate-source protection diode |
| CN1630079A (en) * | 2003-12-15 | 2005-06-22 | 三星电子株式会社 | Electrostatic discharge protection device and manufacturing method thereof |
| CN1822396A (en) * | 2006-01-16 | 2006-08-23 | 电子科技大学 | Vertical double diffusion metal oxide semiconductor power device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104867832A (en) * | 2014-02-21 | 2015-08-26 | 北大方正集团有限公司 | Manufacturing method of vertical double-diffusion metal oxide semiconductor field effect transistor |
| CN104867832B (en) * | 2014-02-21 | 2017-10-20 | 北大方正集团有限公司 | The manufacture method of vertical double-diffusion metal-oxide-semiconductor field effect transistor |
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Application publication date: 20101201 |