CN1964070A - A vertical dual diffused MOS power device protected by polysilicon ESD structure - Google Patents
A vertical dual diffused MOS power device protected by polysilicon ESD structure Download PDFInfo
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- CN1964070A CN1964070A CN 200610022264 CN200610022264A CN1964070A CN 1964070 A CN1964070 A CN 1964070A CN 200610022264 CN200610022264 CN 200610022264 CN 200610022264 A CN200610022264 A CN 200610022264A CN 1964070 A CN1964070 A CN 1964070A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims description 43
- 229920005591 polysilicon Polymers 0.000 title claims description 42
- 230000009977 dual effect Effects 0.000 title 1
- 238000009792 diffusion process Methods 0.000 claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 11
- 150000004706 metal oxides Chemical class 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 230000006698 induction Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 238000007599 discharging Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000011982 device technology Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005686 electrostatic field Effects 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003902 lesion Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The related vertical double-diffusion MOS power device protected by multicrystal silicon ESD structure introduces PN diode for voltage endurance and discharging ESD current based on general VDMOS. Wherein, the PN junction is formed by different doping multicrystal silicon. This invention can improve device capacity for anti ESD greatly.
Description
Technical field
The vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure belongs to the semiconductor power device technology field.
Background technology
Vertical DMOS (VDMOS) power device is the important foundation of power electronic, and characteristics such as power switch, VDMOS is high pressure resistant with it, low on-resistance are usually used in power integrated circuit and the power integrated system.VDMOS is the indispensable part of weaponry system, and it provides driving for electronic equipment provides the power supply of desired form and motor device, and almost all electronic equipments and motor device all need be used POWER VD MOS device.Along with the enhancing of the anti-irradiation ability of VDMOS device, it also is applied even more extensively in Aero-Space and nuclear environment.Fig. 1 is conventional VDMOS device architecture schematic diagram.Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, p (or n) district, the 5th, n
+(or p
+) district, the 6th, p
+(or n
+) district, the 7th, silicon dioxide layer, the 8th, polysilicon layer, the 9th, source electrode, the 10th, grid.
Electrostatic Discharge is the transmission of electrostatic charge between the object of two different electrostatic potentials causing of directly contact or electrostatic field induction.ESD can comprise hundreds of millimicro Joule energy, and produces about 3000V voltage, and it can damage almost most semiconductor device and semiconductor integrated circuit.
The VDMOS device is in manufacturing and applied environment, because extensive employing, machine discharge, electrification device and electromagnetic interference of the ion injection of high energy, static electricity on human body, macromolecular material or the like all can be brought the problem of ESD.ESD can cause following damage to the VDMOS device: the voltage that is added on the oxide layer owing to ESD causes the interface charge of grid oxygen or an oxygen medium puncture, oxide layer electric charge and silicon/silicon dioxide to increase; Because the electric current that ESD causes causes the fusing of device incoming flow, second breakdown etc.The damage that has directly causes the inefficacy of device, and the meeting that has produces hiding defective in the VDMOS device, and they did not lose efficacy immediately but can cause the interrupted fault and the problems such as latent lesion of long-term reliability.These have all produced very adverse influence to the reliability and the environmental suitability of VDMOS device.
Preventive means to the ESD damage is divided into two aspects both at home and abroad: be external factor on the one hand, promptly improve production, work, storage environment and the standard of device and circuit; Be internal factor on the other hand, promptly improve the performance of esd protection circuit in the sheet, this respect also is the main means that improve the anti-ESD performance of integrated circuit at present.
The esd protection structure that is used for the VDMOS device so far both at home and abroad all adopts the part-structure form of conventional MOS device or CMOS integrated circuit; aspect the anti-ESD ability that improves conventional MOS device and CMOS integrated circuit, researchers have proposed various measures.Document sieve magnificence, grace Yun Fei etc., the anti-ESD designing technique of many fingers nMOSFET, the Circuits and Systems journal, 2004,12, studied to utilize many fingers nMOSFET to carry out anti-ESD design be an important means that improves the anti-ESD ability of current C MOS integrated circuit.Fig. 2 is a typical n type MOSFET and parasitic horizontal npn transistor schematic thereof.Fig. 3 is the exemplary currents-voltage response of grounded-grid nMOSFET under the ESD effect, wherein the voltage and current at 14 places is respectively cut-in voltage and firing current, the voltage at 15 places is for keeping voltage, and the voltage and current at 16 places is respectively secondary breakdown voltage and second breakdown electric current.After ESD voltage surpasses the cut-in voltage of parasitic npn pipe, nMOSFET enters negative differential resistance region, and voltage remains on keeps voltage, provides bleed-off circuit for the ESD electric current simultaneously, if the ESD electric current has surpassed transistorized second breakdown electric current, transistor will breakdownly burn.Therefore in order to obtain good anti-ESD ability; will reduce cut-in voltage and increase the second breakdown electric current; increasing the most frequently used method of second breakdown electric current is that the area that increases protection tube promptly adopts many fingers transistor, and its structure is connected in parallel with regard to the nMOSFET that is equivalent to a plurality of single fingers.When ESD stress during in many fingers nMOSFET, at first any finger triggering and conducting among many fingers nMOSFET enters negative differential resistance region, the big electric current of ESD that begins to release, and voltage slowly gos up.Design single finger secondary breakdown voltage greater than its cut-in voltage, then before the finger that has triggered enters second breakdown, the voltage that ESD stress causes will surpass the cut-in voltage of nMOSFET once more, second finger is triggered, with first finger big electric current of ESD of releasing, go on like this, until entire n MOSFET conducting.
There is the many fingers ESD electric current of releasing together many fingers nMOSFET inside, thereby its anti-ESD ability strengthens greatly.But many fingers nMOSFET can not directly apply to VDMOS at the lateral MOS designs, and the area that the device that adopts this method to design takies is bigger, and technology operability and controllability are not strong, and cost is also higher.
Summary of the invention
The object of the present invention is to provide the vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure; it has introduced the next withstand voltage and ESD electric current of releasing of diode that the pn knot forms in conventional VDMOS; thereby formation esd protection structure; compare with conventional VDMOS device; have the advantages that anti-ESD ability improves greatly; and device technology operability and controllability are stronger, and cost of manufacture is not high yet.
Technical solution of the present invention is as follows:
The vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure; as shown in Figure 4; it is characterized in that on the basis of conventional VDMOS, utilized the polysilicon pn of the polysilicon formation of different doping types itself to tie the diode of formation as esd protection structure.
Need to prove:
(1) vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure; as shown in Figure 4; two parts that the device polysilicon layer is mixed by difference are formed, and utilize the polysilicon pn of the polysilicon formation of different doping types itself to tie the esd protection structure of the diode of formation as device.
(2) vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure, its esd protection structure is in the inner realization of grid.
Operation principle of the present invention:
The vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure provided by the invention; can overcome the imperfect shortcoming of the anti-ESD ability of conventional VDMOS device; obtain anti-preferably ESD ability, and device technology operability and controllability are stronger, cost of manufacture is not high yet.Specify operation principle of the present invention below.
When ESD occurred among the conventional VDMOS, may cause that conventional VDMOS crosses to have a meeting, an audience, etc. well under one's control to cause lost efficacy and the inefficacy of overcurrent thermic.When ESD occurs in the conventional VDMOS device, may apply certain voltage on oxide layer, under institute's making alive, electronics is injected into oxide layer, and the ionization that bumps in oxide layer produces trapped hole.Trapped hole is a space charge, this will certainly influence the electric field in the oxide layer, the surface charge density of trapped hole is proportional to the poor of two Electrode Field in the oxide layer, when the surface charge density of trapped hole increases to certain depth, make the difference of the electric field on the electrode surpass dielectric breakdown voltage, then oxide layer generation dielectric breakdown; When ESD occurs in the conventional VDMOS device, may cause in device that electric current flows through knot, the power dissipation in knot elevates the temperature to silicon area and melts, when silicon melts, its resistance reduces by 30 times, and this causes that more electric current flows through the fusion zone, further the heat fused district, cause heat to fly ease, produce second breakdown, foreign atom distributes along the fusing route again simultaneously, and lattice damage causes electric field and leakage current, in serious situation, the knot short circuit takes place.
And for the VDMOS device of protected by polysilicon ESD structure provided by the invention, when ESD takes place when, be added in the diode that polysilicon pn knot that the voltage on the oxide layer can form by the polysilicon of different doping types itself forms and bear, therefore, dielectric breakdown can not take place in the device oxide layer; When producing big electric current in the device, the diode that electric current can form by the pn knot of introducing discharges, and can not cause fusing of device overcurrent or second breakdown.Thereby the VDMOS device of protected by polysilicon ESD structure can prevent the damage that ESD brings effectively, makes device avoid losing efficacy.
In sum; the vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure provided by the invention; tie the diode of formation as esd protection structure by in traditional VDMOS, introducing pn; be added in voltage on the oxide layer to bear ESD, the electric current that the ESD that releases causes improves the anti-ESD ability of device.Adopt the present invention to make more to have the high reliability and the anti-ESD power device of ease for operation more.
Description of drawings
Fig. 1 is conventional VDMOS device architecture schematic diagram
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, p (or n) district, the 5th, n
+(or p
+) district, the 6th, p
+(or n
+) district, the 7th, silicon dioxide layer, the 8th, polysilicon layer, the 9th, source electrode, the 10th, grid.
Fig. 2 is a typical n type MOSFET and parasitic horizontal npn transistor schematic thereof
Wherein, the 1st, the drain electrode of device, the 9th, source electrode, the 10th, grid, the 11st, p type substrate zone, the 12nd, resistance substrate, the 13rd, n
+The district.
Fig. 3 is the exemplary currents-voltage response of grounded-grid nMOSFET under the ESD effect
Wherein the voltage and current at 14 places is respectively cut-in voltage and firing current, and the voltage at 15 places is for keeping voltage, and the voltage and current at 16 places is respectively secondary breakdown voltage and second breakdown electric current.
Fig. 4 is the VDMOS power unit structure schematic diagram of protected by polysilicon ESD structure provided by the invention
Wherein, the 1st, the drain electrode of device, the 2nd, n
+(or p
+) substrate zone, the 3rd, n
-(or p
-) epitaxial loayer, the 4th, p (or n) district, the 5th, n
+(or p
+) district, the 6th, p
+(or n
+) district, the 7th, silicon dioxide layer, the 8th, mix the polysilicon layer of n (or p), the 9th, source electrode, the 10th, grid, the 17th, mix the polysilicon layer of p (or n).
Embodiment
Adopt polysilicon ESD protection structure of the present invention, can obtain the anti-ESD VDMOS power device of function admirable.Can be applied to common power devices such as bilateral diffusion field-effect tranisistor, insulated gate bipolar power transistor, electrostatic induction transistor.Adopt the irradiation of protected by polysilicon ESD structure to reinforce the VDMOS device and can be used for Aero-Space, nuclear environment and other fields that device performance is had relatively high expectations.Along with development of semiconductor, adopt the present invention to make more to have the high reliability and the anti-ESD power device of ease for operation more.
Introduce the VDMOS power device of protected by polysilicon ESD structure, as shown in Figure 4, comprise drain electrode 1, n
+(or p
+) substrate zone 2, n
-(or p
-) epitaxial loayer 3, p (or n) district 4, n
+(or p
+) district 5, p
+(or n
+) district 6, silicon dioxide layer 7 is mixed the polysilicon layer 8 of n (or p), source electrode 9, and grid 10 is mixed the polysilicon layer 17 of p (or n).It is characterized in that two parts that its polysilicon layer is mixed by difference form, the polysilicon pn that utilizes the polysilicon of different doping types itself to form ties the esd protection structure of the diode of formation as device.
The VDMOS power device of protected by polysilicon ESD structure in the specific implementation, only needs the step in doped polycrystalline silicon, and polysilicon is carried out dissimilar doping, and all the other making steps and conventional VDMOS's is identical.
Claims (3)
1, the vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure as shown in Figure 4, comprises drain electrode 1, n
+(or p
+) substrate zone 2, n-(or p-) epitaxial loayer 3, p (or n) district 4, n
+(or p
+) district 5, p
+(or n
+) district 6, silicon dioxide layer 7 is mixed the polysilicon layer 8 of n (or p), source electrode 9, and grid 10 is mixed the polysilicon layer 17 of p (or n).It is characterized in that two parts that its polysilicon layer is mixed by difference form, the polysilicon pn that utilizes the polysilicon of different doping types itself to form ties the esd protection structure of the diode of formation as device.
2, the vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure according to claim 1 is characterized in that, esd protection structure is in the inner realization of grid.
3, the vertical double diffusion metal oxide semiconductor power device of protected by polysilicon ESD structure according to claim 1, polysilicon ESD protection structure wherein can also be used for semiconductor device such as lateral MOS device, insulated gate bipolar power transistor, electrostatic induction transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610022264 CN1964070A (en) | 2006-11-15 | 2006-11-15 | A vertical dual diffused MOS power device protected by polysilicon ESD structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610022264 CN1964070A (en) | 2006-11-15 | 2006-11-15 | A vertical dual diffused MOS power device protected by polysilicon ESD structure |
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| Publication Number | Publication Date |
|---|---|
| CN1964070A true CN1964070A (en) | 2007-05-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610022264 Pending CN1964070A (en) | 2006-11-15 | 2006-11-15 | A vertical dual diffused MOS power device protected by polysilicon ESD structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901829A (en) * | 2010-05-07 | 2010-12-01 | 深圳深爱半导体有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN102544104A (en) * | 2012-01-12 | 2012-07-04 | 清华大学 | High-voltage resistant tunneling transistor and preparation method thereof |
-
2006
- 2006-11-15 CN CN 200610022264 patent/CN1964070A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901829A (en) * | 2010-05-07 | 2010-12-01 | 深圳深爱半导体有限公司 | Electrostatic discharge protection structure and manufacturing method thereof |
| CN102544104A (en) * | 2012-01-12 | 2012-07-04 | 清华大学 | High-voltage resistant tunneling transistor and preparation method thereof |
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