CN113629128A - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN113629128A CN113629128A CN202010373740.5A CN202010373740A CN113629128A CN 113629128 A CN113629128 A CN 113629128A CN 202010373740 A CN202010373740 A CN 202010373740A CN 113629128 A CN113629128 A CN 113629128A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 claims description 11
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Abstract
The invention belongs to the technical field of semiconductor devices, and particularly discloses a semiconductor device, which comprises: an n-type drain region; an n-type epitaxial layer located above the n-type drain region; at least two gate regions positioned in the n-type epitaxial layer and far away from one side of the n-type drain region; the n-type source region is positioned in the n-type epitaxial layer and positioned between the adjacent gate regions; a plurality of p-type pillars within the n-type epitaxial layer and between the gate region and the n-type drain region. The semiconductor device of the invention can improve the breakdown voltage and reduce the on-resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor device of a junction field effect transistor.
Background
In power application, a JFET (Junction Field-Effect Transistor) device is a three-terminal active device with an amplifying function, which is composed of a p-n Junction gate, a source and a drain, and the working principle is to change the conductivity of a channel through gate voltage to realize the control of output current. Fig. 1 is a schematic cross-sectional structure of a JFET device of the prior art, comprising: the semiconductor device comprises an n-type semiconductor substrate 10, at least two p-type doped regions 13 (only two p-type doped regions 13 are exemplarily shown in fig. 1) located in the n-type semiconductor substrate 10, a p-n junction gate structure is formed between the p-type doped regions 13 and the n-type semiconductor substrate 10, the p-type doped regions 13 are led out through gate metal (not shown in fig. 1) to be connected with gate voltage, an n-type drain region 12 and an n-type source region 11 are respectively arranged at two ends of the n-type semiconductor substrate 10, the n-type drain region 12 is led out through drain metal (not shown in fig. 1) to be connected with drain voltage, and the n-type source region 11 is led out through source metal (not shown in fig. 1) to be connected with source voltage. The prior art JFET device typically has its on-resistance reduced by increasing the doping concentration of the n-type semiconductor substrate 10, but an increase in the doping concentration of the n-type semiconductor substrate 10 causes the breakdown voltage of the JFET device to decrease.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide a semiconductor device that can reduce the on-resistance without reducing the breakdown voltage.
To achieve the above object of the present invention, the present invention provides a semiconductor device comprising:
an n-type drain region;
an n-type epitaxial layer located above the n-type drain region;
at least two gate regions positioned in the n-type epitaxial layer and far away from one side of the n-type drain region;
the n-type source region is positioned in the n-type epitaxial layer and positioned between the adjacent gate regions;
at least one p-type pillar located within the n-type epitaxial layer and between the gate region and the n-type drain region.
Optionally, the gate region includes a p-type doped region, and the p-type doped region is externally connected to a gate voltage through a gate metal.
Optionally, the gate metal is recessed within the p-type doped region.
Optionally, a p-type column is disposed below each p-type doped region, and the p-type column is externally connected to a gate voltage through the corresponding p-type doped region.
Optionally, the gate region further includes gate trenches located at two sides of the p-type doped region, a gate dielectric layer and a gate electrode are arranged in the gate trenches, and the gate electrode is externally connected with a gate voltage.
Optionally, a lateral width of the p-type doped region is smaller than a lateral width of the p-type pillar.
Optionally, the p-type columns are arranged in a floating manner.
Optionally, the number of the p-type pillars is greater than, equal to, or less than the number of the gate regions.
According to the semiconductor device provided by the invention, the p-type column is arranged in the n-type epitaxial layer, and charge balance is formed between the p-type column and the n-type epitaxial layer, so that when the on-resistance is reduced by improving the doping concentration of the n-type epitaxial layer, the breakdown voltage of the semiconductor device can be ensured not to be reduced through the charge balance structure.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments.
Figure 1 is a schematic cross-sectional view of a JFET device of the prior art;
fig. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor device according to the present invention;
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure diagram of a semiconductor device according to a third embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be fully described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. It is to be understood that the terms "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof. Meanwhile, in order to clearly illustrate the embodiments of the present invention, the schematic drawings listed in the accompanying drawings enlarge the thickness of the layers and regions of the present invention, and the listed sizes of the figures do not represent actual sizes.
Fig. 2 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor device provided by the present invention, and as shown in fig. 2, the semiconductor device provided by the present invention includes an n-type drain region 20, an n-type epitaxial layer 21 located above the n-type drain region 20, at least two gate regions 31 located in the n-type epitaxial layer 21 and on a side away from the n-type drain region 20, an n-type source region 23 located in the n-type epitaxial layer 21 and between adjacent gate regions 31, and at least one p-type pillar 22 located in the n-type epitaxial layer 21 and between the gate region 31 and the n-type drain region 20, in fig. 2, only three gate regions 31 and three p-type pillars 22 are exemplarily shown, and the p-type pillars 22 are all arranged in a floating manner, and optionally, the number of the p-type pillars 22 may be greater than, equal to, or less than the number of the gate regions 31.
Fig. 3 is a schematic cross-sectional structure diagram of a second embodiment of a semiconductor device provided by the present invention, and as shown in fig. 3, the semiconductor device provided by the present invention includes an n-type drain region 20, an n-type epitaxial layer 21 located above the n-type drain region 20, and at least two gate regions located in the n-type epitaxial layer 21 and on a side away from the n-type drain region 20, where the gate regions are p-type doped regions 24, and the p-type doped regions 24 are externally connected with a gate voltage through a gate metal 25, and preferably, the gate metal 25 is recessed in the p-type doped regions 24 to reduce contact resistance. An n-type source region 23 located within the n-type epitaxial layer 21 and between adjacent p-type doped regions 24, and a plurality of p-type pillars 22 located within the n-type epitaxial layer 21 and between the p-type doped regions 24 and the n-type drain region 20. Three p-type doped regions 24 and three p-type pillars 22 are shown in fig. 3 for illustrative purposes only. In this embodiment, the p-type pillars 22 are sequentially disposed under the p-type doped regions 24 and connected in contact with the p-type doped regions 24, and the p-type pillars 22 are externally connected to a gate voltage through the corresponding p-type doped regions 24.
Fig. 4 is a schematic cross-sectional structure diagram of a third embodiment of a semiconductor device provided by the present invention, and as shown in fig. 4, the semiconductor device provided by the present invention includes an n-type drain region 20, an n-type epitaxial layer 21 located above the n-type drain region 20, at least two gate regions located in the n-type epitaxial layer 21 and on a side away from the n-type drain region 20, the gate regions include a p-type doped region 24 and gate trenches located on both sides of the p-type doped region 24, a gate dielectric layer 26 and a gate 27 are located in each gate trench, and the gate 27 and the p-type doped region 24 are both externally connected with a gate voltage through a gate metal (the gate metal is not shown in fig. 4). An n-type source region 23 located within the n-type epitaxial layer 21 and between adjacent p-type doped regions 24, and a plurality of p-type pillars 22 located within the n-type epitaxial layer 21 and between the p-type doped regions 24 and the n-type drain region 20. Three p-doped regions 24 and three p-pillars 22 are shown only by way of example in fig. 4, the p-pillars 22 being arranged in succession beneath the p-doped regions 24 and in contact with the p-doped regions 24, the p-pillars 22 being connected to the gate voltage via the respective p-doped regions 24. Alternatively, the lateral width of the p-type doped region 24 may be smaller than the lateral width of the p-type pillar 22 to reduce the chip area of the semiconductor device, as shown in fig. 4.
According to the semiconductor device, the p-type column is arranged in the n-type epitaxial layer, and charge balance is formed between the p-type column and the n-type epitaxial layer, so that when the on-resistance is reduced by improving the doping concentration of the n-type epitaxial layer, the breakdown voltage of the semiconductor device is not reduced through the charge balance structure.
The above embodiments and examples are specific supports for the technical ideas of the present invention, and the protection scope of the present invention should not be limited thereby, and any equivalent changes or equivalent modifications made on the basis of the technical solutions according to the technical ideas proposed by the present invention still belong to the protection scope of the technical solutions of the present invention.
Claims (8)
1. A semiconductor device, comprising:
an n-type drain region;
an n-type epitaxial layer located above the n-type drain region;
at least two gate regions positioned in the n-type epitaxial layer and far away from one side of the n-type drain region;
the n-type source region is positioned in the n-type epitaxial layer and positioned between the adjacent gate regions;
at least one p-type pillar located within the n-type epitaxial layer and between the gate region and the n-type drain region.
2. The semiconductor device of claim 1, wherein the gate region comprises a p-type doped region circumscribing a gate voltage through a gate metal.
3. The semiconductor device of claim 2, in which the gate metal is recessed within the p-type doped region.
4. The semiconductor device of claim 2, wherein one of said p-type pillars is disposed below each of said p-type doped regions, said p-type pillar circumscribing a gate voltage through the corresponding said p-type doped region.
5. The semiconductor device of claim 4, wherein the gate region further comprises gate trenches located on both sides of the p-type doped region, a gate dielectric layer and a gate electrode are disposed in the gate trenches, and the gate electrode is externally connected to a gate voltage.
6. The semiconductor device of claim 5, in which a lateral width of the p-type doped region is less than a lateral width of the p-type pillar.
7. The semiconductor device of claim 2, wherein the p-type pillars are arranged floating.
8. The semiconductor device of claim 1, wherein a number of the p-type pillars is greater than, equal to, or less than a number of the gate regions.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010373740.5A CN113629128B (en) | 2020-05-06 | 2020-05-06 | Semiconductor device with a plurality of transistors |
| PCT/CN2020/117286 WO2021223357A1 (en) | 2020-05-06 | 2020-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010373740.5A CN113629128B (en) | 2020-05-06 | 2020-05-06 | Semiconductor device with a plurality of transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113629128A true CN113629128A (en) | 2021-11-09 |
| CN113629128B CN113629128B (en) | 2022-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202010373740.5A Active CN113629128B (en) | 2020-05-06 | 2020-05-06 | Semiconductor device with a plurality of transistors |
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| Country | Link |
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| CN (1) | CN113629128B (en) |
| WO (1) | WO2021223357A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4543706A (en) * | 1984-02-24 | 1985-10-01 | Gte Laboratories Incorporated | Fabrication of junction field effect transistor with filled grooves |
| CN1577885A (en) * | 2003-07-18 | 2005-02-09 | 半导体元件工业有限责任公司 | Vertical compound semiconductor field effect transistor structure |
| CN1812132A (en) * | 2005-12-16 | 2006-08-02 | 北京工业大学 | High-frequency low-consumption power junction type field effect transistor |
| EP2963678A1 (en) * | 2014-03-26 | 2016-01-06 | NGK Insulators, Ltd. | Semiconductor device |
| US20170170264A1 (en) * | 2015-12-10 | 2017-06-15 | Infineon Technologies Ag | Semiconductor Devices and a Circuit for Controlling a Field Effect Transistor of a Semiconductor Device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1128443B1 (en) * | 1998-10-09 | 2009-12-30 | The Kansai Electric Power Co., Inc. | Field-effect semiconductor device and fabrication method thereof |
| US7211845B1 (en) * | 2004-04-19 | 2007-05-01 | Qspeed Semiconductor, Inc. | Multiple doped channel in a multiple doped gate junction field effect transistor |
| CN102916049B (en) * | 2012-10-30 | 2015-04-22 | 成都芯源系统有限公司 | Semiconductor device comprising junction type filed effect transistor and manufacturing method thereof |
| CN103840012A (en) * | 2012-11-22 | 2014-06-04 | 无锡华润上华半导体有限公司 | Junction field-effect transistor (JFET) and preparation method thereof |
-
2020
- 2020-05-06 CN CN202010373740.5A patent/CN113629128B/en active Active
- 2020-09-24 WO PCT/CN2020/117286 patent/WO2021223357A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4543706A (en) * | 1984-02-24 | 1985-10-01 | Gte Laboratories Incorporated | Fabrication of junction field effect transistor with filled grooves |
| CN1577885A (en) * | 2003-07-18 | 2005-02-09 | 半导体元件工业有限责任公司 | Vertical compound semiconductor field effect transistor structure |
| CN1812132A (en) * | 2005-12-16 | 2006-08-02 | 北京工业大学 | High-frequency low-consumption power junction type field effect transistor |
| EP2963678A1 (en) * | 2014-03-26 | 2016-01-06 | NGK Insulators, Ltd. | Semiconductor device |
| US20170170264A1 (en) * | 2015-12-10 | 2017-06-15 | Infineon Technologies Ag | Semiconductor Devices and a Circuit for Controlling a Field Effect Transistor of a Semiconductor Device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021223357A1 (en) | 2021-11-11 |
| CN113629128B (en) | 2022-08-19 |
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