JP2011216847A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2011216847A
JP2011216847A JP2010280431A JP2010280431A JP2011216847A JP 2011216847 A JP2011216847 A JP 2011216847A JP 2010280431 A JP2010280431 A JP 2010280431A JP 2010280431 A JP2010280431 A JP 2010280431A JP 2011216847 A JP2011216847 A JP 2011216847A
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semiconductor device
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JP5718627B2 (en
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Hisao Inomata
久雄 猪股
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of an SJ structure having improved breakdown voltage and breakdown resistance.SOLUTION: The semiconductor device 1 includes a transistor element 200 formed on a semiconductor substrate 101, the transistor element having a parallel structure composed of a first conductive drift region 202 and a second conductive column region 205 and a second conductive base region 203. The parallel structure composed of the first conductive drift region 202 and the second conductive column regions 205 and a second conductive annular diffusion region 303 located on a side of the base region 203 to be separated therefrom are formed in an outer peripheral region 300X outside an element forming region. The annular diffusion region 303 has an innermost end 303A and a portion close thereto that are located on the column region 205, and an outermost end 303B that is located outside the outermost column region 205. A field insulating film 306 covering the annular diffusion region 303 is overlaid on a semiconductor layer 201 of the outer peripheral region 300X.

Description

本発明は、所謂スーパージャンクション構造の半導体装置に関するものである。   The present invention relates to a semiconductor device having a so-called super junction structure.

高耐圧と大電流容量とを実現する代表的な半導体装置として、パワーＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）がある。基板の両面に形成された一対の電極間に電流を流すタイプは縦型パワーＭＯＳＦＥＴと呼ばれ、低いオン抵抗を有するスイッチングデバイス等として広く普及している。   There is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) as a typical semiconductor device that realizes a high breakdown voltage and a large current capacity. A type in which a current flows between a pair of electrodes formed on both sides of a substrate is called a vertical power MOSFET, and is widely used as a switching device having a low on-resistance.

縦型パワーＭＯＳＦＥＴは、用途に応じて所定の耐圧を持つように設計される。ここで、「所定の耐圧」とは、デバイスのどこかで局所電界が臨界値を超え、ブレークダウンが発生するときのドレイン−ソース間電圧のことである。一般に耐圧とオン抵抗との間にはトレードオフ関係があるため、ある程度の耐圧を得ようとすると、オン抵抗を低減しようにも限界がある。
従来の縦型パワーＭＯＳＦＥＴでは、ベース領域とドリフト領域（不純物濃度の低いドレイン領域）間のｐ／ｎ接合で耐圧が決まるため、理論的に求められる最小オン抵抗の耐圧依存性（Ｓｉリミットと称される。）が知られていた。 The vertical power MOSFET is designed to have a predetermined breakdown voltage according to the application. Here, the “predetermined breakdown voltage” is a drain-source voltage when a local electric field exceeds a critical value somewhere in the device and breakdown occurs. In general, since there is a trade-off relationship between breakdown voltage and on-resistance, there is a limit to reducing the on-resistance in order to obtain a certain level of breakdown voltage.
In the conventional vertical power MOSFET, the breakdown voltage is determined by the p / n junction between the base region and the drift region (drain region having a low impurity concentration), and therefore the theoretically required breakdown voltage dependency (referred to as Si limit). Was known).

近年、縦型パワーＭＯＳＦＥＴにおけるオン抵抗をＳｉリミットを越えて低減する技術として、所謂スーパージャンクション構造（ＳＪ構造）が提案されている。図７を参照して、ＳＪ構造を有する縦型パワーＭＯＳＦＥＴの基本構成を説明する。図７は要部断面図である。   In recent years, a so-called super junction structure (SJ structure) has been proposed as a technique for reducing the on-resistance in a vertical power MOSFET beyond the Si limit. With reference to FIG. 7, a basic configuration of a vertical power MOSFET having an SJ structure will be described. FIG. 7 is a cross-sectional view of the main part.

図７に示すＭＯＳＦＥＴ５００は、
第１導電型半導体基板５０１と、
半導体基板５０１の一方の面（図示上面）に形成された半導体層６０１と、
半導体層６０１上に形成された層間絶縁膜６１０と、
層間絶縁膜６１０に開孔されたコンタクトホールを介して、半導体層６０１と電気的に接続されたソース電極６１１と、
半導体層６０１の上面から開溝された溝部（トレンチ）内に形成されたゲート絶縁膜６０６及びゲート電極６０７と、
半導体基板６０１の他方の面（図示下面）に形成されたドレイン電極６１２とを備えている。 The MOSFET 500 shown in FIG.
A first conductivity type semiconductor substrate 501;
A semiconductor layer 601 formed on one surface (illustrated upper surface) of the semiconductor substrate 501;
An interlayer insulating film 610 formed over the semiconductor layer 601;
A source electrode 611 electrically connected to the semiconductor layer 601 through a contact hole opened in the interlayer insulating film 610;
A gate insulating film 606 and a gate electrode 607 formed in a groove (trench) opened from the upper surface of the semiconductor layer 601;
And a drain electrode 612 formed on the other surface (illustrated lower surface) of the semiconductor substrate 601.

半導体層６０１内には、
第１導電型のドリフト領域６０２と、
ドリフト領域６０２の上方に形成された第２導電型のベース領域６０３と、
ベース領域６０３の上層部に形成された第１導電型のソース領域６０４と、
ドリフト領域６０２内に柱状に形成された第２導電型のコラム領域６０５とが形成されている。 In the semiconductor layer 601,
A first conductivity type drift region 602;
A base region 603 of the second conductivity type formed above the drift region 602;
A first conductivity type source region 604 formed in an upper layer portion of the base region 603;
A column region 605 of the second conductivity type formed in a columnar shape is formed in the drift region 602.

この例では、半導体基板５０１はｎ＋型、ドリフト領域６０２はｎ型、ベース領域６０３はｐ型、ソース領域６０４はｎ＋型、コラム領域６０５はｐ型である。
半導体層６０１内には、第１導電型のドリフト領域６０２と第２導電型のコラム領域６０５とが基板面方向に並列された並列構造（ｐ／ｎ接合構造）が形成されている。 In this example, the semiconductor substrate 501 is n + type, the drift region 602 is n type, the base region 603 is p type, the source region 604 is n + type, and the column region 605 is p type.
In the semiconductor layer 601, a parallel structure (p / n junction structure) in which a first conductivity type drift region 602 and a second conductivity type column region 605 are arranged in parallel in the substrate surface direction is formed.

ＳＪ構造では、ドリフト領域のドナー不純物量とコラム領域のアクセプタ不純物量とを略同一に設定することにより、ドリフト領域のチャージとコラム領域のチャージとがバランスした状態（チャージバランス条件）となり、耐圧を最大化することができる。かかるチャージバランス条件下では、デバイスのＯＦＦ時にドレイン−ソース電極間に逆バイアス電圧がかかると、ドリフト領域とコラム領域間のｐ／ｎ接合から空乏層が横方向に均等に広がるため、隣接する空乏層同士が互いに接続し易くなる。ＳＪ構造全体が空乏化して単一の空乏層になると、等ポテンシャル面がほぼ等間隔かつほぼ平行となるため、耐圧を最大化することができる。ＳＪ構造の設計では、チャージバランス条件下で（耐圧を最大化した状態で）ドリフト領域の不純物濃度を高濃度化できるため、ドリフト抵抗を低減でき、オン抵抗を低減できる。   In the SJ structure, by setting the donor impurity amount in the drift region and the acceptor impurity amount in the column region to be substantially the same, the charge in the drift region and the charge in the column region are balanced (charge balance condition), and the breakdown voltage is reduced. Can be maximized. Under such a charge balance condition, when a reverse bias voltage is applied between the drain and source electrodes when the device is OFF, the depletion layer spreads laterally evenly from the p / n junction between the drift region and the column region. Layers can be easily connected to each other. When the entire SJ structure is depleted to form a single depletion layer, the equipotential surfaces are substantially equidistant and substantially parallel, so that the withstand voltage can be maximized. In the design of the SJ structure, the impurity concentration in the drift region can be increased under charge balance conditions (with the breakdown voltage maximized), so that the drift resistance can be reduced and the on-resistance can be reduced.

また、パワーＭＯＳＦＥＴの半導体チップの設計においては、デバイスに過大な誘導負荷などがかかった場合でも、チップの外周領域にアバランシェ電流が集中してデバイス破壊が起こらないような高い破壊耐量を実現することが重要である。そのためには、少なくとも１つのＭＯＳＦＥＴが形成された素子形成領域（セル領域）の耐圧より外側の外周領域の耐圧を高くしておく必要がある。   Also, in the design of power MOSFET semiconductor chips, even when an excessive inductive load is applied to the device, a high breakdown resistance must be realized so that the avalanche current does not concentrate on the outer peripheral region of the chip and the device is destroyed. is important. For this purpose, it is necessary to increase the breakdown voltage of the outer peripheral region outside the breakdown voltage of the element formation region (cell region) where at least one MOSFET is formed.

外周領域の耐圧を高くする手段として、ＳＪ構造の特徴である柱状のｐ／ｎ接合の繰り返し構造を外周領域にまで延長する構造が提案されている。   As means for increasing the breakdown voltage of the outer peripheral region, a structure in which a columnar p / n junction repeating structure, which is a feature of the SJ structure, is extended to the outer peripheral region has been proposed.

特許文献１及びそれを基礎とする米国出願である特許文献２には、外周領域に素子形成領域と同様の柱状のｐ／ｎ接合の繰り返し構造を形成して、外周領域の不純物濃度を素子形成領域と同等以下に設定することで、外周領域を素子形成領域と同じかそれ以上に空乏化し易くして耐圧を向上させた構造が記載されている。
特許文献１の図１９／特許文献２の図１７、図１８には、素子形成領域（１２２）と外周領域（２０）に、同じ柱状のｐ／ｎ接合の繰り返し構造（ｎ型ドリフト領域（２０ａ）／コラム領域（２０ｂ）の繰り返し構造）が形成された構造が記載されている。外周領域（２０）の素子形成領域（１２２）側には、素子形成領域（１２２）を囲むように、コラム領域（２０ｂ）よりも不純物濃度の高い環状の浅いｐ型領域（２０ｃ）が形成されている。外周領域（２０）の半導体層上には、表面保護及び安定化のためにフィールド絶縁膜（２３）が積層されている（段落００４１）。コラム領域（２０ｂ）は、環状の浅いｐ型領域（２０ｃ）よりも外側の領域（図１９の図示左側）にも形成されており、この領域では、コラム領域（２０ｂ）の上端がフィールド絶縁膜（２３）に接触している。フィールド絶縁膜（２３）上に、フィールド電極は設けられていない。 In Patent Document 1 and US Patent Application 2, which is a US application based on the same, a columnar p / n junction repetitive structure similar to the element forming region is formed in the outer peripheral region, and the impurity concentration in the outer peripheral region is defined as the element forming. A structure is described in which the breakdown voltage is improved by setting the outer peripheral region to be equal to or higher than the element formation region by setting it equal to or less than the region.
In FIG. 19 of Patent Document 1 / FIG. 17 and FIG. 18 of Patent Document 2, the same columnar p / n junction repeating structure (n-type drift region (20a) is formed in the element formation region (122) and the outer peripheral region (20). ) / Repeated structure of column region (20b)) is described. An annular shallow p-type region (20c) having an impurity concentration higher than that of the column region (20b) is formed on the element forming region (122) side of the outer peripheral region (20) so as to surround the element forming region (122). ing. On the semiconductor layer in the outer peripheral region (20), a field insulating film (23) is laminated for surface protection and stabilization (paragraph 0041). The column region (20b) is also formed in a region outside the annular shallow p-type region (20c) (the left side in FIG. 19). In this region, the upper end of the column region (20b) is the field insulating film. (23) is in contact. No field electrode is provided on the field insulating film (23).

特許文献３及びそれを基礎とする米国出願である特許文献４には、外周領域のｐ／ｎ接合とフィールド絶縁膜の内端との位置関係を規定して外周領域の電界集中を緩和した構造が記載されている。
特許文献３の図１／特許文献４の図１Ａ、図１Ｂには、外周領域（５６）に環状の浅いｐ型領域はなく、素子形成領域（５４）のコラム領域（３４，３６）より浅い位置にコラム領域（３８）が形成された構造が形成されている。外周領域（５６）には、コラム領域（３８）の直上に、フィールド絶縁膜（４６）とフィールド電極（４８）とが積層されている。特許文献２では、外周領域（５６）において、フィールド絶縁膜（４６）の下方にコラム領域（３８）が形成されているが、フィールド絶縁膜（４６）の内端（６４）の直下及びその近傍領域にはコラム領域（３８）が形成されないようにして、フィールド絶縁膜（４６）の内端（６４）付近の電界集中を緩和している。 Patent document 3 and US patent document 4 which is a US application based on the above structure have a structure in which the electric field concentration in the outer peripheral region is reduced by defining the positional relationship between the p / n junction in the outer peripheral region and the inner end of the field insulating film. Is described.
In FIG. 1A and FIG. 1B of Patent Document 3 in FIG. 1 / Patent Document 4, there is no annular shallow p-type region in the outer peripheral region (56), which is shallower than the column regions (34, 36) of the element formation region (54). A structure in which a column region (38) is formed at a position is formed. In the outer peripheral region (56), a field insulating film (46) and a field electrode (48) are laminated immediately above the column region (38). In Patent Document 2, the column region (38) is formed below the field insulating film (46) in the outer peripheral region (56), but just below and near the inner end (64) of the field insulating film (46). The column region (38) is not formed in the region, and the electric field concentration near the inner end (64) of the field insulating film (46) is relaxed.

特許文献５及びそれを基礎とする米国出願である特許文献６の図１には、外周領域に環状の浅いｐ型領域（１０５）とコラム領域（１０６）とが形成され、外周領域において最外周のコラム領域（１０６ａ）より外側の領域（環状の浅いｐ型領域（１０５）とコラム領域（１０６）とがない領域）にフィールド絶縁膜（１１８）が形成され、外周領域においてコラム領域（１０６）の直上を除く領域にフィールド電極（１２０）が形成された構造が記載されている。
また、それに関連する説明には、外周領域にコラム領域（１０６）を形成することにより、外周領域の耐圧を高く保つことができると記載されている。特許文献５、６では、フィールド電極（１２０）をコラム領域（１０６）直上に形成しないことで、フィールド電極を形成した後にコラム領域（１０６）を形成することを可能としている。 In FIG. 1 of Patent Document 5 and Patent Document 6 which is a US application based thereon, an annular shallow p-type region (105) and a column region (106) are formed in the outer peripheral region, and the outermost periphery is formed in the outer peripheral region. A field insulating film (118) is formed in a region outside the column region (106a) (region where there is no annular shallow p-type region (105) and column region (106)), and the column region (106) is formed in the outer peripheral region. A structure in which a field electrode (120) is formed in a region except directly above is described.
In addition, the description related thereto describes that the breakdown voltage of the outer peripheral region can be kept high by forming the column region (106) in the outer peripheral region. In Patent Documents 5 and 6, the field electrode (120) is not formed immediately above the column region (106), so that the column region (106) can be formed after the field electrode is formed.

外周領域に柱状のコラム領域がないタイプであるが、参考までに特許文献７及びそれを基礎とする米国出願である特許文献８を挙げておく。特許文献７、８の図１には、外周領域にコラム領域（４）の代わりにｐ型の埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）が設けられ、これら埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）の上方に環状の浅いｐ型領域（ＧＲ１〜ＧＲ４）が設けられ、これら環状の浅いｐ型領域（ＧＲ１〜ＧＲ４）の直上にフィールド電極（１４）が形成された構造が記載されている。特許文献４の段落００３２〜００４１には、環状の浅いｐ型領域ＧＲ１〜ＧＲ４及び埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）によって、局所的な電界集中が抑えられることが記載されている。   Although it is a type which does not have a columnar column region in the outer peripheral region, Patent Document 7 and Patent Document 8 which is a US application based on the same are cited for reference. In FIG. 1 of Patent Documents 7 and 8, p-type buried semiconductor regions (BGR1 to BGR4) are provided in the outer peripheral region instead of the column region (4), and a ring is formed above these buried semiconductor regions (BGR1 to BGR4). In this structure, a shallow p-type region (GR1 to GR4) is provided, and a field electrode (14) is formed immediately above these annular shallow p-type regions (GR1 to GR4). Paragraphs 0032 to 0041 of Patent Document 4 describe that local electric field concentration can be suppressed by the annular shallow p-type regions GR1 to GR4 and the embedded semiconductor regions (BGR1 to BGR4).

特開2001-298190号公報JP 2001-298190 A 米国特許出願公開第2001/0028083号明細書US Patent Application Publication No. 2001/0028083 特開2007-103902号公報JP 2007-103902 A 米国特許出願公開第2007/0052015号明細書US Patent Application Publication No. 2007/0052015 特開2006-196518号公報JP 2006-196518 A 米国特許出願公開第2006/0151831号明細書US Patent Application Publication No. 2006/0151831 特開2009-088345号公報JP 2009-088345 米国特許出願公開第2009/0090968号明細書US Patent Application Publication No. 2009/0090968

本発明者が詳細な分析を実施したところ、後述するように、上記従来構造では外周領域における耐圧や破壊耐量が必ずしも充分ではないことが分かった。   As a result of detailed analysis by the inventor, it was found that the above-described conventional structure does not necessarily have sufficient withstand pressure and breakdown resistance in the outer peripheral region, as will be described later.

本発明の半導体装置は、
半導体基板の一方の面に半導体層が形成された基板に、
前記半導体層内に、第１導電型のドリフト領域と第２導電型のコラム領域とが基板面方向に並列された並列構造と、当該並列構造の上方に形成された第２導電型のベース領域とを有する少なくとも１つのトランジスタ素子が形成された半導体装置であって、
前記少なくとも１つのトランジスタ素子が形成された素子形成領域より外側の外周領域には、前記半導体層内に、前記トランジスタ素子の前記並列構造と同一構造である、第１導電型のドリフト領域と第２導電型のコラム領域との並列構造と、前記トランジスタ素子の前記ベース領域の側方に当該ベース領域から離間して平面視環状に形成された第２導電型の環状拡散領域とが形成されており、
前記外周領域の前記第２導電型の環状拡散領域は、最内端及びその近傍部分が前記コラム領域上に位置され、最外端が最外周の前記コラム領域よりも外側に位置されており、
前記外周領域の前記半導体層上に、前記第２導電型の環状拡散領域を覆うフィールド絶縁膜が積層されたものである。 The semiconductor device of the present invention is
On a substrate having a semiconductor layer formed on one side of the semiconductor substrate,
A parallel structure in which a first conductivity type drift region and a second conductivity type column region are arranged in parallel in the substrate surface direction in the semiconductor layer, and a second conductivity type base region formed above the parallel structure. A semiconductor device in which at least one transistor element is formed,
In the outer peripheral region outside the element formation region where the at least one transistor element is formed, a drift region of the first conductivity type and the second structure are the same as the parallel structure of the transistor elements in the semiconductor layer. A parallel structure with a conductive type column region and a second conductive type annular diffusion region formed in an annular shape in plan view and spaced apart from the base region are formed on the side of the base region of the transistor element. ,
The annular diffusion region of the second conductivity type in the outer peripheral region, the innermost end and the vicinity thereof are positioned on the column region, the outermost end is positioned outside the outermost column region,
A field insulating film covering the annular diffusion region of the second conductivity type is laminated on the semiconductor layer in the outer peripheral region.

本発明によれば、図３Ａに等ポテンシャル面のシミュレーション例を示すように、電界集中が緩和され、耐圧及び破壊耐量が向上された所謂スーパージャンクション構造の半導体装置を提供することができる。   According to the present invention, as shown in FIG. 3A showing an example of an equipotential surface simulation, it is possible to provide a semiconductor device having a so-called super junction structure in which electric field concentration is reduced and breakdown voltage and breakdown resistance are improved.

本発明によれば、電界集中が緩和され、耐圧及び破壊耐量が向上された所謂スーパージャンクション構造の半導体装置を提供することができる。   According to the present invention, it is possible to provide a semiconductor device having a so-called super junction structure in which electric field concentration is reduced and breakdown voltage and breakdown resistance are improved.

本発明に係る第１実施形態の半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device of 1st Embodiment which concerns on this invention. 図１の半導体装置の要部平面図である。FIG. 2 is a main part plan view of the semiconductor device of FIG. 1. 図１の半導体装置の全体平面図である。FIG. 2 is an overall plan view of the semiconductor device of FIG. 1. 本発明に係る実施例の外周領域の等ポテンシャル面のシミュレーション例である。It is an example of a simulation of the equipotential surface of the outer periphery area | region of the Example which concerns on this invention. 比較例の外周領域の等ポテンシャル面のシミュレーション例である。It is a simulation example of the equipotential surface of the outer peripheral area | region of a comparative example. 設計変更例を示す要部平面図である。It is a principal part top view which shows the example of a design change. 設計変更例を示す全体平面図である。It is a whole top view which shows the example of a design change. 他の設計変更例を示す全体平面図である。It is a whole top view which shows the example of another design change. 本発明に係る第２実施形態の半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device of 2nd Embodiment which concerns on this invention. 本発明に係る第３実施形態の半導体装置の要部断面図である。It is principal part sectional drawing of the semiconductor device of 3rd Embodiment concerning this invention. ＳＪ構造を有する縦型パワーＭＯＳＦＥＴの基本構成を示す要部断面図である。It is principal part sectional drawing which shows the basic composition of the vertical power MOSFET which has SJ structure.

「第１実施形態」
図面を参照して、本発明に係る第１実施形態の半導体装置の構成について説明する。図１は本実施形態の半導体装置の要部断面図、図２Ａは要部平面図、図２Ｂは全体平面図である。図面上は視認しやすくするため、各部材の縮尺や位置は適宜、実際のものとは異ならせてある。 “First Embodiment”
The configuration of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. 1 is a cross-sectional view of a main part of the semiconductor device of the present embodiment, FIG. 2A is a plan view of the main part, and FIG. 2B is a plan view of the whole. In order to facilitate visual recognition on the drawings, the scale and position of each member are appropriately different from the actual ones.

本実施形態の半導体装置１は、第１導電型の半導体基板１０１に、少なくとも１つのスーパージャンクション（ＳＪ）構造を有する縦型のパワーＭＯＳＦＥＴ（トランジスタ素子）２００が形成されたものである。本実施形態では、１つの半導体基板１０１に複数のＭＯＳＦＥＴ２００が形成されており、複数のＭＯＳＦＥＴ２００が形成された領域を素子形成領域（セル領域）２００Ｘ、それより外側を外周領域３００Ｘと呼ぶ。素子形成領域２００Ｘと外周領域３００Ｘとの間には明確な境界がある訳ではない。図１では、ｐ型ベース領域２０３の形成領域を素子形成領域２００Ｘとし、それより外側を外周領域３００Ｘとして、図示してある。   In the semiconductor device 1 of the present embodiment, a vertical power MOSFET (transistor element) 200 having at least one super junction (SJ) structure is formed on a first conductive type semiconductor substrate 101. In the present embodiment, a plurality of MOSFETs 200 are formed on one semiconductor substrate 101, and a region where the plurality of MOSFETs 200 are formed is referred to as an element formation region (cell region) 200X, and the outer side is referred to as an outer peripheral region 300X. There is no clear boundary between the element formation region 200X and the outer peripheral region 300X. In FIG. 1, the formation region of the p-type base region 203 is illustrated as an element formation region 200X, and the outer side is illustrated as an outer peripheral region 300X.

半導体装置１には、第１導電型の半導体基板１０１の一方の面（図示上面）全体に半導体層２０１が形成され、他方の面（図示下面）全体にドレイン電極２１２が形成されている。
ＭＯＳＦＥＴ２００（半導体装置１の素子形成領域２００Ｘ）は、
半導体基板１０１の一方の面（図示上面）に形成された半導体層２０１と、
半導体層２０１上に形成された層間絶縁膜２１０と、
層間絶縁膜２１０に開孔されたコンタクトホールを介して、半導体層２０１と電気的に接続されたソース電極２１１と、
半導体層２０１の上面から開溝された溝部（トレンチ）内に形成されたゲート絶縁膜２０６及びゲート電極２０７と、
半導体基板１０１の他方の面（図示下面）に形成されたドレイン電極２１２とを備えている。 In the semiconductor device 1, a semiconductor layer 201 is formed on one entire surface (illustrated upper surface) of the first conductivity type semiconductor substrate 101, and a drain electrode 212 is formed on the entire other surface (illustrated lower surface).
MOSFET 200 (element formation region 200X of semiconductor device 1)
A semiconductor layer 201 formed on one surface (illustrated upper surface) of the semiconductor substrate 101;
An interlayer insulating film 210 formed on the semiconductor layer 201;
A source electrode 211 electrically connected to the semiconductor layer 201 through a contact hole opened in the interlayer insulating film 210;
A gate insulating film 206 and a gate electrode 207 formed in a groove (trench) opened from the upper surface of the semiconductor layer 201;
And a drain electrode 212 formed on the other surface (the lower surface in the drawing) of the semiconductor substrate 101.

ＭＯＳＦＥＴ２００は、
半導体層２０１内に、
第１導電型のドリフト領域（不純物濃度の低いドレイン領域）２０２と、
ドリフト領域２０２の上方に形成された第２導電型のベース領域２０３と、
ベース領域２０３の上層部に形成された第１導電型のソース領域２０４と、
ドリフト領域２０２内においてベース領域２０３の下方に柱状に形成された第２導電型のコラム領域２０５とを備えている。 MOSFET 200 is
In the semiconductor layer 201,
A first conductivity type drift region (drain region having a low impurity concentration) 202;
A second conductivity type base region 203 formed above the drift region 202;
A first conductivity type source region 204 formed in an upper layer portion of the base region 203;
The drift region 202 includes a column region 205 of a second conductivity type formed in a column shape below the base region 203.

ＭＯＳＦＥＴ２００において、断面視、内部にゲート絶縁膜２０６及びゲート電極２０７が形成された溝部は、半導体層２０１の上面から少なくともソース領域２０４とベース領域２０３とに跨って開溝されている。内部にゲート絶縁膜２０６及びゲート電極２０７が形成された溝部の平面パターンについては、図２Ａ及び図２Ｂを参照されたい。   In the MOSFET 200, a groove portion in which the gate insulating film 206 and the gate electrode 207 are formed is opened from the upper surface of the semiconductor layer 201 across at least the source region 204 and the base region 203. Refer to FIGS. 2A and 2B for the planar pattern of the groove in which the gate insulating film 206 and the gate electrode 207 are formed.

本実施形態では、第１導電型はｎ型、第２導電型はｐ型である。より詳しくは、半導体基板１０１はｎ＋型、ドリフト領域２０２はｎ型、ベース領域２０３はｐ型、ソース領域２０４はｎ＋型、コラム領域２０５はｐ型である。 In the present embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. More specifically, the semiconductor substrate 101 is n + type, the drift region 202 is n type, the base region 203 is p type, the source region 204 is n + type, and the column region 205 is p type.

半導体層２０１内には、第１導電型のドリフト領域２０２と第２導電型のコラム領域２０５とが基板面方向に並列された並列構造（ｐ／ｎ接合構造）が形成されている。
本実施形態において、第１導電型のドリフト領域２０２のドナー不純物量と第２導電型のコラム領域２０５のアクセプタ不純物量とが略同一に設定されることが好ましい。「略同一」は、誤差範囲のずれは許容されることを意味する。
第１導電型のドリフト領域２０２のドナー不純物量と第２導電型のコラム領域２０５のアクセプタ不純物量とが略同一の条件では、第１導電型のドリフト領域２０２と第２導電型のコラム領域２０５のチャージとがバランスした状態（チャージバランス条件）となり、耐圧を最大化することができ、好ましい。かかるチャージバランス条件下では、デバイスのＯＦＦ時にドレイン−ソース電極間に逆バイアス電圧がかかると、ドリフト領域とコラム領域間のｐ／ｎ接合から空乏層が横方向に均等に広がるため、隣接する空乏層同士が互いに接続し易くなる。ＳＪ構造全体が空乏化して単一の空乏層になると、等ポテンシャル面がほぼ等間隔かつほぼ平行となるため、耐圧を最大化することができる。ＳＪ構造の設計では、チャージバランス条件下で（耐圧を最大化した状態で）ドリフト領域の不純物濃度を高濃度化できるため、ドリフト抵抗を低減でき、オン抵抗を低減できる。 In the semiconductor layer 201, a parallel structure (p / n junction structure) in which a first conductivity type drift region 202 and a second conductivity type column region 205 are arranged in parallel in the substrate surface direction is formed.
In the present embodiment, it is preferable that the donor impurity amount of the first conductivity type drift region 202 and the acceptor impurity amount of the second conductivity type column region 205 are set to be substantially the same. “Substantially the same” means that a deviation in the error range is allowed.
Under the condition that the donor impurity amount of the first conductivity type drift region 202 and the acceptor impurity amount of the second conductivity type column region 205 are substantially the same, the first conductivity type drift region 202 and the second conductivity type column region 205 are the same. It is preferable that the charge is balanced (charge balance condition) and the withstand voltage can be maximized. Under such a charge balance condition, when a reverse bias voltage is applied between the drain and source electrodes when the device is OFF, the depletion layer spreads laterally evenly from the p / n junction between the drift region and the column region. Layers can be easily connected to each other. When the entire SJ structure is depleted to form a single depletion layer, the equipotential surfaces are substantially equidistant and substantially parallel, so that the withstand voltage can be maximized. In the design of the SJ structure, the impurity concentration in the drift region can be increased under charge balance conditions (with the breakdown voltage maximized), so that the drift resistance can be reduced and the on-resistance can be reduced.

なお、半導体基板１０１、ドリフト領域２０２、ベース領域２０３、ソース領域２０４、コラム領域２０５の導電型及び不純物濃度については、本発明の趣旨を逸脱しない範囲内において適宜設計変更できる。第１導電型と第２導電型とは、上記の逆でも構わない。   Note that the conductivity types and impurity concentrations of the semiconductor substrate 101, the drift region 202, the base region 203, the source region 204, and the column region 205 can be appropriately changed within the scope of the present invention. The first conductivity type and the second conductivity type may be reversed.

図２Ａ及び図２Ｂに示すように、本実施形態において、平面視、ライン状の複数の第２導電型のコラム領域２０５が、図示左右方向に周期的に配列されている。   As shown in FIGS. 2A and 2B, in the present embodiment, a plurality of second conductivity type column regions 205 in a line shape in a plan view are periodically arranged in the horizontal direction in the drawing.

本実施形態において、外周領域３００Ｘには、半導体層２０１内に、素子形成領域２００Ｘに形成された第１導電型のドリフト領域２０２と第２導電型のコラム領域２０５の並列構造と同一の並列構造と、素子形成領域２００Ｘの第２導電型のベース領域２０３の側方に、当該ベース領域から離間して平面視環状に形成された第２導電型の環状拡散領域３０３とが形成されている。本実施形態において、第２導電型の環状拡散領域３０３は素子形成領域２００Ｘのベース領域２０３と同様、ｐ型である。   In the present embodiment, the outer peripheral region 300X has the same parallel structure as the parallel structure of the first conductivity type drift region 202 and the second conductivity type column region 205 formed in the element formation region 200X in the semiconductor layer 201. In addition, a second conductivity type annular diffusion region 303 is formed on the side of the element formation region 200X on the side of the second conductivity type base region 203 so as to be spaced apart from the base region and formed in an annular shape in plan view. In the present embodiment, the annular diffusion region 303 of the second conductivity type is p-type like the base region 203 of the element formation region 200X.

素子形成領域２００Ｘの第２導電型のベース領域２０３と外周領域３００Ｘの第２導電型の環状拡散領域３０３の深さと不純物濃度は、略同一でも異なっていても構わないが、略同一であることが好ましい。
素子形成領域２００Ｘの第２導電型のベース領域２０３と外周領域３００Ｘの第２導電型の環状拡散領域３０３とは同一プロセスで形成されることが好ましい。この場合、第２導電型の環状拡散領域３０３を設けても、工程数の増加がなく、好ましい。 The depth and impurity concentration of the second conductivity type base region 203 of the element formation region 200X and the second conductivity type annular diffusion region 303 of the outer peripheral region 300X may be substantially the same or different, but are substantially the same. Is preferred.
The second conductivity type base region 203 of the element formation region 200X and the second conductivity type annular diffusion region 303 of the outer peripheral region 300X are preferably formed by the same process. In this case, even if the second conductivity type annular diffusion region 303 is provided, there is no increase in the number of steps, which is preferable.

本実施形態において、素子形成領域２００Ｘにおいて、断面視、第２導電型のベース領域２０３と第２導電型のコラム領域２０５とが接し、外周領域３００Ｘにおいて、断面視、第２導電型の環状拡散領域３０３と第２導電型のコラム領域２０５とが接している。   In the present embodiment, the second conductivity type base region 203 and the second conductivity type column region 205 are in contact with each other in the element formation region 200X, and the second conductivity type annular diffusion in the outer peripheral region 300X. The region 303 and the second conductivity type column region 205 are in contact with each other.

図１に示すように、本実施形態において、外周領域３００Ｘの第２導電型の環状拡散領域３０３は、最内端３０３Ａ及びその近傍部分がコラム領域２０５上に位置され、最外端３０３Ｂが最外周のコラム領域（図示最右端のコラム領域）２０５よりも外側に位置されている。
すなわち、外周領域３００Ｘの第２導電型の環状拡散領域３０３は、最内端３０３Ａを含む図示左端部がコラム領域２０５に重なって形成されており、最外端３０３Ｂを含む図示右端部が最外周のコラム領域２０５より外側に張り出している。
素子形成領域２００Ｘの第２導電型のベース領域２０３と、外周領域３００Ｘの第２導電型の環状拡散領域３０３、及び第２導電型のコラム領域２０５の平面関係については、図２Ａ及び図２Ｂを参照されたい。 As shown in FIG. 1, in the present embodiment, in the second conductivity type annular diffusion region 303 of the outer peripheral region 300X, the innermost end 303A and the vicinity thereof are located on the column region 205, and the outermost end 303B is the outermost end. It is located outside the outer peripheral column region (the rightmost column region in the figure) 205.
That is, the second conductivity type annular diffusion region 303 of the outer peripheral region 300X is formed so that the illustrated left end including the innermost end 303A overlaps the column region 205, and the illustrated right end including the outermost end 303B is the outermost peripheral. It protrudes outside the column region 205.
2A and 2B for the planar relationship between the second conductivity type base region 203 of the element formation region 200X, the second conductivity type annular diffusion region 303 of the outer peripheral region 300X, and the second conductivity type column region 205. Please refer.

外周領域３００Ｘの半導体層２０１上に、第２導電型の環状拡散領域３０３を覆うように、フィールド絶縁膜３０６が積層されている。フィールド絶縁膜３０６上にはさらに、フィールド電極３０７と層間絶縁膜２１０とが順次積層されている。フィールド電極３０７は、素子形成領域２００Ｘのゲート電極２０７の材料（例えばポリシリコン）が図示しない領域でフィールド絶縁膜３０６上に引き出されたものである。フィールド電極３０７は、ゲートパッド（図示せず）に接続されている。   A field insulating film 306 is stacked on the semiconductor layer 201 in the outer peripheral region 300 </ b> X so as to cover the annular diffusion region 303 of the second conductivity type. On the field insulating film 306, a field electrode 307 and an interlayer insulating film 210 are sequentially stacked. In the field electrode 307, the material (for example, polysilicon) of the gate electrode 207 in the element formation region 200X is drawn on the field insulating film 306 in a region not shown. The field electrode 307 is connected to a gate pad (not shown).

本実施形態は所謂スーパージャンクション構造（ＳＪ構造）を有する縦型パワーＭＯＳＦＥＴ２００を備えたものであるので、高耐圧特性と大電流容量とを有しつつ、オン抵抗をＳＪ構造を有しない縦型パワーＭＯＳＦＥＴよりも低減することが可能である。
本実施形態は所謂スーパージャンクション構造（ＳＪ構造）を有する縦型パワーＭＯＳＦＥＴ２００を備えたものであるので、高耐圧特性と大電流容量とを有しつつ、オン抵抗をＳｉリミットを越えて低減することが可能である。
本実施形態では、ＳＪ構造の特徴である柱状のｐ／ｎ接合（コラム領域２０５／ドリフト領域２０２とのｐ／ｎ接合）の繰り返し構造を外周領域３００Ｘまで延長しているので、外周領域３００Ｘの耐圧及び破壊耐量の向上が図られている。
本実施形態においてはさらに、外周領域３００Ｘに、最内端３０３Ａ及びその近傍部分はコラム領域２０５上に位置し、最外端３０３Ｂは最外周のコラム領域２０５よりも外側に位置する第２導電型の環状拡散領域３０３を設けることで、外周領域３００Ｘにおける耐圧及び破壊耐量のより一層の向上が図られている。 Since the present embodiment includes the vertical power MOSFET 200 having a so-called super junction structure (SJ structure), the vertical power without the SJ structure has a high withstand voltage characteristic and a large current capacity. It can be reduced as compared with the MOSFET.
Since this embodiment includes a vertical power MOSFET 200 having a so-called super junction structure (SJ structure), the on-resistance is reduced beyond the Si limit while having high breakdown voltage characteristics and large current capacity. Is possible.
In this embodiment, the columnar p / n junction (p / n junction with the column region 205 / drift region 202), which is a feature of the SJ structure, is extended to the outer peripheral region 300X. Improvements in pressure resistance and breakdown resistance are achieved.
In the present embodiment, in the outer peripheral region 300X, the innermost end 303A and its vicinity are located on the column region 205, and the outermost end 303B is located outside the outermost column region 205. By providing the annular diffusion region 303, the breakdown voltage and the breakdown resistance in the outer peripheral region 300X are further improved.

図３Ａは、本実施形態において、ＭＯＳＦＥＴ２００のＯＦＦ時にドレイン−ソース電極間に充分に大きな逆バイアス電圧が印加された場合の外周領域３００Ｘにおける等ポテンシャル面のシミュレーション例である（実施例）。
図３Ｂは、外周領域３００Ｘに第２導電型の環状拡散領域３０３がないことを除けば本実施形態と同様の構成についての同シミュレーション例である（比較例）。この比較例の構成では、外周領域３００Ｘにおいて、第２導電型の環状拡散領域３０３がなく、コラム領域２０５がフィールド絶縁膜３０６に直接接している。 FIG. 3A is a simulation example of an equipotential surface in the outer peripheral region 300X when a sufficiently large reverse bias voltage is applied between the drain and source electrodes when the MOSFET 200 is OFF in the present embodiment (Example).
FIG. 3B is a simulation example of the same configuration as that of the present embodiment except that the outer peripheral region 300X does not have the second conductivity type annular diffusion region 303 (comparative example). In the configuration of this comparative example, there is no second conductivity type annular diffusion region 303 in the outer peripheral region 300 </ b> X, and the column region 205 is in direct contact with the field insulating film 306.

図３Ａと図３Ｂとを比較すると分かるように、図３Ｂでは、フィールド絶縁膜と最外周のコラム領域との接触部分付近で等ポテンシャル面の曲率が急激に小さくなり、その部分に電界が集中している。
これに対して、図３Ａでは、外周領域３００Ｘに、最内端３０３Ａ及びその近傍部分はコラム領域２０５上に位置し、最外端３０３Ｂは最外周のコラム領域２０５よりも外側に位置する第２導電型の環状拡散領域３０３が設けられたことで、等ポテンシャル面の間隔が広がり、且つ等ポテンシャル面の曲率が緩やかになっており、電界集中が緩和されている。 As can be seen from a comparison between FIG. 3A and FIG. 3B, in FIG. 3B, the curvature of the equipotential surface suddenly decreases near the contact portion between the field insulating film and the outermost column region, and the electric field concentrates on that portion. ing.
On the other hand, in FIG. 3A, in the outer peripheral region 300X, the innermost end 303A and the vicinity thereof are located on the column region 205, and the outermost end 303B is the second outermost region located outside the outermost peripheral column region 205. By providing the conductive type annular diffusion region 303, the interval between the equipotential surfaces is widened, the curvature of the equipotential surfaces is gentle, and the electric field concentration is alleviated.

フィールド電極３０７にはゲート電圧がかかるため、デバイスのＯＦＦ時には接地電位が印加される。デバイスのＯＦＦ時にはフィールド電極３０７が一定電位（接地電位）になるため、第２導電型のコラム領域２０５も第２導電型の環状拡散領域３０３も形成されていない更に外側の領域では、図３Ａの場合も図３Ｂの場合も、等ポテンシャル面がフィールド電極３０７及びドレイン電極２１２に対して平行になる。このため、最外周のコラム領域２０５からフィールド絶縁膜３０６に向かう等ポテンシャル面は、フィールド電極３０７があることにより、これに並行になるように曲げられており、等ポテンシャル面の曲率はフィールド電極３０７が無い場合に比べて緩やかになる。   Since a gate voltage is applied to the field electrode 307, a ground potential is applied when the device is OFF. Since the field electrode 307 is at a constant potential (ground potential) when the device is OFF, in the further outer region where the second conductivity type column region 205 and the second conductivity type annular diffusion region 303 are not formed, In both cases and FIG. 3B, the equipotential surface is parallel to the field electrode 307 and the drain electrode 212. For this reason, the equipotential surface from the outermost column region 205 toward the field insulating film 306 is bent in parallel with the presence of the field electrode 307, and the curvature of the equipotential surface is the field electrode 307. It becomes gentle compared to the case where there is no.

本実施形態では、素子成領域２００Ｘの第２導電型のベース領域２０３と外周領域３００Ｘの第２導電型の環状拡散領域３０３とを、平面視で離間させている。かかる構成では、素子成領域２００Ｘの第２導電型のベース領域２０３の外端２０３Ｂと第１導電型のドリフト領域２０２間のｐ／ｎ接合と、第２導電型の環状拡散領域３０３の内端３０３Ａと第１導電型のドリフト領域２０２間のｐ／ｎ接合のそれぞれから横方向に空乏層が広がるため、第２導電型のベース領域２０３と第２導電型の環状拡散領域３０３とが離間していない場合よりも、横方向の電界に強い半導体装置１が得られる。   In the present embodiment, the second conductivity type base region 203 of the element forming region 200X and the second conductivity type annular diffusion region 303 of the outer peripheral region 300X are separated in plan view. In such a configuration, the p / n junction between the outer end 203B of the second conductivity type base region 203 and the first conductivity type drift region 202 of the element forming region 200X, and the inner end of the second conductivity type annular diffusion region 303 are formed. Since a depletion layer spreads laterally from each of the p / n junctions between 303A and the first conductivity type drift region 202, the second conductivity type base region 203 and the second conductivity type annular diffusion region 303 are separated from each other. Thus, the semiconductor device 1 that is more resistant to the electric field in the lateral direction can be obtained than when it is not.

第１導電型のドリフト領域２０２の比抵抗（不純物濃度）、第２導電型のコラム領域２０５の不純物濃度、第２導電型の環状拡散領域３０３の不純物濃度、及び第２導電型の環状拡散領域３０３の最外周のコラム領域２０５からの張出し部分の長さは、所望の耐圧（ＶＤＳＳ）に応じて設計できる。
本発明者は、例えば、素子形成領域２００Ｘの耐圧（ＶＤＳＳ）が５５Ｖのトレンチゲート型パワーＭＯＳＦＥＴ２００を得ようとする場合、第１導電型のドリフト領域２０２を比抵抗０．５０Ω・ｃｍ程度のエピタキシャル層で形成し、第２導電型のコラム領域２０５の不純物濃度を６．０×１０１６ｃｍ−３程度とし、第２導電型の環状拡散領域３０３の不純物濃度を４．０×１０１６ｃｍ−３程度とし、第２導電型の環状拡散領域３０３を最外周のコラム領域２０５よりも約５．０μｍ外側に張り出すように設計すればよいことを求めている。なお、ここに挙げた数値は設計例であり、適宜設計できることは言うまでもない。 The specific resistance (impurity concentration) of the drift region 202 of the first conductivity type, the impurity concentration of the column region 205 of the second conductivity type, the impurity concentration of the annular diffusion region 303 of the second conductivity type, and the annular diffusion region of the second conductivity type The length of the protruding portion from the outermost column region 205 of 303 can be designed according to the desired breakdown voltage (VDSS).
For example, when the present inventor intends to obtain a trench gate type power MOSFET 200 in which the breakdown voltage (VDSS) of the element formation region 200X is 55V, the first conductivity type drift region 202 is epitaxially formed with a specific resistance of about 0.50 Ω · cm. The second conductivity type column region 205 has an impurity concentration of about 6.0 × 10 16 cm −3 , and the second conductivity type annular diffusion region 303 has an impurity concentration of 4.0 × 10 16 cm −. 3 about and to require that we may be designed so as to project approximately 5.0μm outward from the second conductive type annular diffusion region 303 outermost peripheral column region 205. Needless to say, the numerical values given here are design examples and can be designed as appropriate.

「背景技術」の項で挙げた特許文献１の図１９（特許文献２の図１８）には、素子形成領域（１２２）を囲うように浅いｐ型領域（２０ｃ）が形成されているものの、この浅いｐ型領域（２０ｃ）よりも外側のコラム領域（２０ｂ）がフィールド絶縁膜（２３）に接触している。また、外周領域にはフィールド電極も存在しない。従って、特許文献１の外周構造における等ポテンシャル面は、特許文献１の図１９（特許文献２の図１８）内に破線で示されているように、フィールド絶縁膜（２３）に対してほぼ垂直に入り込んでいる。つまり、比較例の図３Ｂよりもさらに電界集中が大きく、耐圧や破壊耐量が低くなっている。   In FIG. 19 of Patent Document 1 (FIG. 18 of Patent Document 2) cited in the “Background Art” section, a shallow p-type region (20c) is formed so as to surround the element formation region (122). The column region (20b) outside the shallow p-type region (20c) is in contact with the field insulating film (23). Further, there is no field electrode in the outer peripheral region. Therefore, the equipotential surface in the outer peripheral structure of Patent Document 1 is substantially perpendicular to the field insulating film (23) as shown by a broken line in FIG. 19 of Patent Document 1 (FIG. 18 of Patent Document 2). I'm stuck in. That is, the electric field concentration is larger than that in FIG.

「背景技術」の項で挙げた特許文献３の図１（特許文献４の図１Ａ、図１Ｂ）には、特許文献１（特許文献２）に比べて、外周領域（５６）に浅いｐ型領域がなく、素子形成領域のコラム領域（３４，３６）よりも浅い位置にコラム領域（３８）が形成されており、外周領域（５６）にフィールド電極（４８）が形成されているため、最外周のコラム領域（３８）とフィールド絶縁膜（４６）との接触部分における電界集中は、特許文献１（特許文献２）よりも緩和されると考えられる。
しかしながら、特許文献３（特許文献４）の外周構造では、コラム領域（３８）は素子形成領域（５４）のベース領域（５１）よりも深い位置に形成されている。すなわち、特許文献３（特許文献４）の外周構造では、最外周のコラム領域（３８）の深さは、本実施形態の浅いｐ型環状拡散領域３０３に比べるとかなり深いため、最外周のコラム領域（３８）からフィールド絶縁膜（４６）に向かう等ポテンシャル面は図３Ａよりも急峻であり、等ポテンシャル面の曲率は図３Ａよりも小さくなる。従って、本実施形態の外周構造の方が、特許文献３（特許文献４）よりも電界集中が小さくなり、耐圧や破壊耐量が優れている。 FIG. 1 of Patent Document 3 (FIGS. 1A and 1B of Patent Document 4) cited in the section “Background Art” shows a shallow p-type in the outer peripheral region (56) compared to Patent Document 1 (Patent Document 2). Since there is no region, the column region (38) is formed at a position shallower than the column regions (34, 36) of the element formation region, and the field electrode (48) is formed in the outer peripheral region (56). It is considered that the electric field concentration at the contact portion between the outer peripheral column region (38) and the field insulating film (46) is more relaxed than in Patent Document 1 (Patent Document 2).
However, in the outer peripheral structure of Patent Document 3 (Patent Document 4), the column region (38) is formed at a position deeper than the base region (51) of the element formation region (54). That is, in the outer peripheral structure of Patent Document 3 (Patent Document 4), the depth of the outermost column region (38) is considerably deeper than that of the shallow p-type annular diffusion region 303 of the present embodiment. The equipotential surface from the region (38) toward the field insulating film (46) is steeper than in FIG. 3A, and the curvature of the equipotential surface is smaller than that in FIG. 3A. Therefore, the electric field concentration is smaller in the outer peripheral structure of the present embodiment than in Patent Document 3 (Patent Document 4), and the breakdown voltage and the breakdown resistance are excellent.

「背景技術」の項で挙げた特許文献５（特許文献６）の図１には、外周領域に浅いｐ型領域（１０５）とコラム領域１０６とが形成されているが、外周領域の浅いｐ型領域（１０５）の最内端及びその近傍部分はコラム領域（１０６）上には位置していない。外周領域にフィールド絶縁膜（１１８）とフィールド電極（１２０）とが形成されているが、これらは浅いｐ型領域（１０５）とコラム領域１０６との上方には形成されていない。
特許文献５（特許文献６）では、フィールド絶縁膜の下にはコラム領域もベース領域も形成されていないので、等電位面を緩やかにする効果は特許文献３（特許文献４）よりも劣っている。 In FIG. 1 of Patent Document 5 (Patent Document 6) cited in the “Background Art” section, a shallow p-type region (105) and a column region 106 are formed in the outer peripheral region. The innermost end of the mold region (105) and the vicinity thereof are not located on the column region (106). A field insulating film (118) and a field electrode (120) are formed in the outer peripheral region, but they are not formed above the shallow p-type region (105) and the column region.
In Patent Document 5 (Patent Document 6), neither the column region nor the base region is formed under the field insulating film, so that the effect of relaxing the equipotential surface is inferior to that of Patent Document 3 (Patent Document 4). Yes.

「背景技術」の項で挙げた特許文献７（特許文献８）の図１には、外周領域にコラム領域（４）の代わりにｐ型の埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）が設けられ、これら埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）の上方に環状の浅いｐ型領域（ＧＲ１〜ＧＲ４）が設けられ、これら環状の浅いｐ型領域（ＧＲ１〜ＧＲ４）の直上にフィールド電極（１４）が形成された構造が記載されている。
この半導体装置は、外周領域にコラム領域がなく、代わりに厚み方向の異なる位置に複数の埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）が設けられているので、外周領域の設計が複雑である。また、埋め込み半導体領域（ＢＧＲ１〜ＢＧＲ４）を素子領域のコラム領域とは異なる工程で形成しているため、工程数も多くなる。 In FIG. 1 of Patent Document 7 (Patent Document 8) cited in “Background Art”, p-type buried semiconductor regions (BGR1 to BGR4) are provided in the outer peripheral region instead of the column region (4). An annular shallow p-type region (GR1 to GR4) is provided above the buried semiconductor region (BGR1 to BGR4), and a field electrode (14) is formed immediately above the annular shallow p-type region (GR1 to GR4). The structure is described.
In this semiconductor device, there is no column region in the outer peripheral region, and instead a plurality of embedded semiconductor regions (BGR1 to BGR4) are provided at different positions in the thickness direction, so the design of the outer peripheral region is complicated. Further, since the buried semiconductor regions (BGR1 to BGR4) are formed in a process different from the column region of the element region, the number of processes is increased.

以上説明したように、本実施形態によれば、電界集中が緩和され、耐圧及び破壊耐量が向上された半導体装置１を提供することができる。   As described above, according to the present embodiment, it is possible to provide the semiconductor device 1 in which the electric field concentration is reduced and the breakdown voltage and the breakdown resistance are improved.

「第１実施形態の設計変更例」
第１導電型のコラム領域２０５のパターンは、図２Ａ及び図２Ｂに示したラインパターンに制限されず、適宜設計変更できる。
第１導電型のコラム領域２０５のパターンは、図４Ａ及び図４Ｂに示すようなアレイパターンあるいは図４Ｃに示すような千鳥パターンでも構わない。
この場合も、外周領域３００Ｘの第２導電型の環状拡散領域３０３の最内端３０３Ａ及びその近傍部分をアレイパターンあるいは千鳥パターンのコラム領域２０５上に位置させ、最外端３０３Ｂを最外周のいずれのコラム領域２０５よりも外側に位置させることで、第１実施形態と同様の効果が得られる。 "Design change example of the first embodiment"
The pattern of the column region 205 of the first conductivity type is not limited to the line pattern shown in FIGS. 2A and 2B, and can be appropriately changed in design.
The pattern of the first conductivity type column region 205 may be an array pattern as shown in FIGS. 4A and 4B or a staggered pattern as shown in FIG. 4C.
In this case as well, the innermost end 303A of the second conductivity type annular diffusion region 303 in the outer peripheral region 300X and the vicinity thereof are positioned on the column region 205 of the array pattern or the staggered pattern, and the outermost end 303B is positioned at any of the outermost periphery. By locating outside the column region 205, the same effect as in the first embodiment can be obtained.

「第２実施形態」
図面を参照して、本発明に係る第２実施形態の半導体装置の構成について説明する。図５は本実施形態の半導体装置の要部断面図である。第１実施形態と同じ構成要素については同じ参照符号を付して、説明を省略する。 “Second Embodiment”
The configuration of the semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a fragmentary cross-sectional view of the semiconductor device of this embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施形態の半導体装置２の基本構成は第１実施形態と同様であり、本実施形態では外周領域３００Ｘの第２導電型の環状拡散領域３０３が間隙を空けて複数の領域に分割されている。本実施形態では第２導電型の環状拡散領域３０３が２つの分割領域３０３Ｐ１（内側）、３０４Ｐ２（外側）に分割されている。   The basic configuration of the semiconductor device 2 of this embodiment is the same as that of the first embodiment. In this embodiment, the second conductivity type annular diffusion region 303 in the outer peripheral region 300X is divided into a plurality of regions with a gap. . In the present embodiment, the annular diffusion region 303 of the second conductivity type is divided into two divided regions 303P1 (inner side) and 304P2 (outer side).

本実施形態において、第２導電型の環状拡散領域３０３の最内端３０３Ａと最外端３０３Ｂの位置は第１実施形態と同様である。すなわち、第２導電型の環状拡散領域３０３の最内端３０３Ａ（最内の分割領域３０３Ｐ１の内端に相当）及びその近傍部分は第２導電型のコラム領域２０５上に位置され、最外端３０３Ｂ（最外の分割領域３０３Ｐ２の外端に相当）は最外周の第２導電型のコラム領域２０５よりも外側に位置されている。   In the present embodiment, the positions of the innermost end 303A and the outermost end 303B of the second conductivity type annular diffusion region 303 are the same as in the first embodiment. That is, the innermost end 303A of the second conductivity type annular diffusion region 303 (corresponding to the inner end of the innermost divided region 303P1) and the vicinity thereof are located on the second conductivity type column region 205, and the outermost end 303B (corresponding to the outer end of the outermost divided region 303P2) is located on the outer side of the outermost peripheral column region 205 of the second conductivity type.

本実施形態においても、第１実施形態と同様の効果が得られる。
さらに、本実施形態の半導体装置２によれば、第２導電型の環状拡散領域３０３が複数の分割領域に３０３Ｐ１、３０３Ｐ２に分割されているので、それぞれの端面のｐ／ｎ接合で横方向の電界を分担して負担することで、横方向の電界にさらに強い半導体装置２が得られる。第２導電型の環状拡散領域３０３の分割数や複数の分割領域の間隙は、適宜設計できる。 Also in this embodiment, the same effect as the first embodiment can be obtained.
Furthermore, according to the semiconductor device 2 of the present embodiment, since the second conductivity type annular diffusion region 303 is divided into a plurality of divided regions 303P1 and 303P2, the lateral direction at the p / n junction of each end face By sharing and sharing the electric field, the semiconductor device 2 that is stronger against the electric field in the lateral direction can be obtained. The number of divisions of the second conductivity type annular diffusion region 303 and the gaps between the plurality of division regions can be appropriately designed.

「第３実施形態」
図面を参照して、本発明に係る第３実施形態の半導体装置の構成について説明する。図６は本実施形態の半導体装置の要部断面図である。第１実施形態と同じ構成要素については同じ参照符号を付して、説明を省略する。 “Third Embodiment”
A configuration of a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a fragmentary cross-sectional view of the semiconductor device of this embodiment. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

本実施形態の半導体装置３の基本構成は第１実施形態と同様であり、本実施形態では、素子形成領域２００Ｘにおいて、断面視、第２導電型のベース領域２０３と第２導電型のコラム領域２０５とが離間している。素子形成領域２００Ｘの第２導電型のベース領域２０３と外周領域３００Ｘの第２導電型の環状拡散領域３０３とは好ましくは同一プロセスで形成されるので、素子形成領域２００Ｘの第２導電型のベース領域２０３と第２導電型のコラム領域２０５の関係と同様に、外周領域３００Ｘでは断面視、第２導電型の環状拡散領域３０３と第２導電型のコラム領域２０５とが離間している。   The basic configuration of the semiconductor device 3 of the present embodiment is the same as that of the first embodiment. In the present embodiment, in the element formation region 200X, the second conductivity type base region 203 and the second conductivity type column region are viewed in cross section. 205 is spaced apart. Since the second conductivity type base region 203 of the element formation region 200X and the second conductivity type annular diffusion region 303 of the outer peripheral region 300X are preferably formed by the same process, the second conductivity type base of the element formation region 200X is formed. Similar to the relationship between the region 203 and the second conductivity type column region 205, in the outer peripheral region 300X, the second conductivity type annular diffusion region 303 and the second conductivity type column region 205 are separated from each other in a cross-sectional view.

本実施形態においても、第１実施形態と同様の効果が得られる。
さらに、本実施形態においては、素子形成領域２００Ｘにおいて、断面視、第２導電型のベース領域２０３と第２導電型のコラム領域２０５とが離間しているので、素子形成領域２００Ｘにおいてトレンチゲート側面のオン電流の経路が広くなり、第１実施形態よりもオン抵抗の低減が図られる。
また、素子形成領域２００Ｘにおいて、断面視、第２導電型のベース領域２０３と第２導電型のコラム領域２０５とが離間して独立しているので、これらの設計の最適化が容易である。同様に、外周領域３００Ｘにおいて、断面視、第２導電型の環状拡散領域３０３と第２導電型のコラム領域２０５とが離間して独立しているので、これらの設計の最適化が容易である。 Also in this embodiment, the same effect as the first embodiment can be obtained.
Further, in the present embodiment, the second conductivity type base region 203 and the second conductivity type column region 205 are separated from each other in the element formation region 200X. The on-current path becomes wider, and the on-resistance can be reduced than in the first embodiment.
Further, in the element formation region 200X, since the second conductivity type base region 203 and the second conductivity type column region 205 are separated and independent in a cross-sectional view, it is easy to optimize these designs. Similarly, in the outer peripheral region 300X, the second conductive type annular diffusion region 303 and the second conductive type column region 205 are separated and independent from each other in cross-sectional view, and it is easy to optimize these designs. .

本実施形態においても、外周領域３００Ｘの第２導電型の環状拡散領域３０３を、図５に示した半導体装置２のように、複数の分割領域に分割してもよい。   Also in the present embodiment, the annular diffusion region 303 of the second conductivity type in the outer peripheral region 300X may be divided into a plurality of divided regions as in the semiconductor device 2 shown in FIG.

「設計変更」
本発明は上記実施形態に限らず、本発明の趣旨を逸脱しない範囲内において適宜設計変更可能である。
上記実施形態では、ＳＪ構造を有するＭＯＳＦＥＴを備えた半導体装置を例に説明したが、ＳＪ構造を有するＩＧＢＴ（Insulated Gate Bipolar Transistor）等を備えた半導体装置にも適用できる。 "Design changes"
The present invention is not limited to the above embodiment, and can be appropriately modified within a range not departing from the gist of the present invention.
In the above embodiment, the semiconductor device including the MOSFET having the SJ structure has been described as an example. However, the present invention can also be applied to a semiconductor device including an IGBT (Insulated Gate Bipolar Transistor) having the SJ structure.

１〜３ 半導体装置
１０１ 第１導電型の半導体基板
２００ ＭＯＳＦＥＴ（トランジスタ素子）
２００Ｘ 素子形成領域
２０１ 半導体層
２０２ 第１導電型のドリフト領域
２０３ 第２導電型のベース領域
２０３Ｂ 第２導電型のベース領域の外端
２０４ 第１導電型のソース領域
２０５ 第２導電型のコラム領域
２０６ ゲート絶縁膜
２０７ ゲート電極
２１０ 層間絶縁膜
２１１ ソース電極
２１２ ドレイン電極
３００Ｘ 外周領域
３０３ 第２導電型の環状拡散領域
３０３Ａ 第２導電型の環状拡散領域の最内端
３０３Ｂ 第２導電型の環状拡散領域の最外端
３０３Ｐ１、３０３Ｐ２ 第２導電型の環状拡散領域の分割領域
３０６ フィールド絶縁膜
３０７ フィールド電極 1-3 Semiconductor device 101 First conductivity type semiconductor substrate 200 MOSFET (transistor element)
200X element formation region 201 semiconductor layer 202 first conductivity type drift region 203 second conductivity type base region 203B outer end 204 of second conductivity type base region first conductivity type source region 205 second conductivity type column region 206 Gate insulating film 207 Gate electrode 210 Interlayer insulating film 211 Source electrode 212 Drain electrode 300X Outer peripheral region 303 Second conductivity type annular diffusion region 303A Inner end 303B of second conductivity type annular diffusion region Second conductivity type annular diffusion Outermost ends 303P1 and 303P2 of the regions Divided regions 306 of the second conductivity type annular diffusion region Field insulating film 307 Field electrode

Claims (5)

半導体基板の一方の面に半導体層が形成された基板に、
前記半導体層内に、第１導電型のドリフト領域と第２導電型のコラム領域とが基板面方向に並列された並列構造と、当該並列構造の上方に形成された第２導電型のベース領域とを有する少なくとも１つのトランジスタ素子が形成された半導体装置であって、
前記少なくとも１つのトランジスタ素子が形成された素子形成領域より外側の外周領域には、前記半導体層内に、前記トランジスタ素子の前記並列構造と同一構造である、第１導電型のドリフト領域と第２導電型のコラム領域との並列構造と、前記トランジスタ素子の前記ベース領域の側方に当該ベース領域から離間して平面視環状に形成された第２導電型の環状拡散領域とが形成されており、
前記外周領域の前記第２導電型の環状拡散領域は、最内端及びその近傍部分が前記コラム領域上に位置され、最外端が最外周の前記コラム領域よりも外側に位置されており、
前記外周領域の前記半導体層上に、前記第２導電型の環状拡散領域を覆うフィールド絶縁膜が積層された半導体装置。 On a substrate having a semiconductor layer formed on one side of the semiconductor substrate,
A parallel structure in which a first conductivity type drift region and a second conductivity type column region are arranged in parallel in the substrate surface direction in the semiconductor layer, and a second conductivity type base region formed above the parallel structure. A semiconductor device in which at least one transistor element is formed,
In the outer peripheral region outside the element formation region where the at least one transistor element is formed, a drift region of the first conductivity type and the second structure are the same as the parallel structure of the transistor elements in the semiconductor layer. A parallel structure with a conductive type column region and a second conductive type annular diffusion region formed in an annular shape in plan view and spaced apart from the base region are formed on the side of the base region of the transistor element. ,
The annular diffusion region of the second conductivity type in the outer peripheral region, the innermost end and the vicinity thereof are positioned on the column region, the outermost end is positioned outside the outermost column region,
A semiconductor device in which a field insulating film covering the annular diffusion region of the second conductivity type is stacked on the semiconductor layer in the outer peripheral region. 前記フィールド絶縁膜上に前記トランジスタ素子のゲート電極に電気的に接続されたフィールド電極が積層された請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a field electrode electrically connected to a gate electrode of the transistor element is stacked on the field insulating film. 前記素子形成領域において、断面視、前記ベース領域と前記コラム領域とが互いに接し、前記外周領域において、断面視、前記第２導電型の環状拡散領域と前記コラム領域とが互いに接した請求項１又は２に記載の半導体装置。   The cross-sectional view, the base region and the column region are in contact with each other in the element formation region, and the annular region of the second conductivity type and the column region are in contact with each other in the outer peripheral region. Or the semiconductor device of 2. 前記素子形成領域において、断面視、前記ベース領域と前記コラム領域とが離間し、
前記外周領域において、断面視、前記第２導電型の環状拡散領域と前記コラム領域とが離間した請求項１又は２に記載の半導体装置。 In the element formation region, a cross-sectional view, the base region and the column region are separated,
3. The semiconductor device according to claim 1, wherein, in the outer peripheral region, the annular diffusion region of the second conductivity type and the column region are separated from each other in a cross-sectional view. 前記外周領域の前記第２導電型の環状拡散領域が、平面視、複数の領域に分割された請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the second conductivity type annular diffusion region in the outer peripheral region is divided into a plurality of regions in plan view.
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