JP7524527B2 - Super-junction semiconductor device and method for manufacturing the same - Google Patents

Description

This invention relates to a superjunction semiconductor device and a method for manufacturing a superjunction semiconductor device.

In a typical n-channel vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor), of the multiple semiconductor layers formed in the semiconductor substrate, the n-type conduction layer (drift layer) is the semiconductor layer with the highest resistance. The electrical resistance of this n-type drift layer has a large effect on the on-resistance of the entire vertical MOSFET. The on-resistance of the entire vertical MOSFET can be reduced by reducing the thickness of the n-type drift layer and shortening the current path.

However, in a vertical MOSFET, the depletion layer spreads to the highly resistive n-type drift layer in the off state, so that the vertical MOSFET also has the function of maintaining the breakdown voltage. Therefore, if the n-type drift layer is thinned to reduce the on-resistance, the distance over which the depletion layer spreads in the off state is shortened, so that the breakdown field strength is easily reached at a low applied voltage, and the breakdown voltage is reduced. On the other hand, in order to increase the breakdown voltage of a vertical MOSFET, the thickness of the n-type drift layer must be increased, and the on-resistance increases. This relationship between on-resistance and breakdown voltage is called a trade-off relationship, and it is generally difficult to improve both of these trade-off relationships. It is known that this trade-off relationship between on-resistance and breakdown voltage also exists in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), bipolar transistors, and diodes.

The super junction (SJ) structure is known as a semiconductor device structure that solves the problems described above. For example, a MOSFET with a super junction structure (hereinafter, SJ-MOSFET) is known. Figure 19 is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

19, the SJ-MOSFET 150 is made of a wafer in which an n-type drift layer 102 is grown on a highly doped n ⁺ -type semiconductor substrate 101. A p-type column region 104 is provided which extends from the surface of the wafer through the n-type drift layer 102 and reaches the n ⁺ -type semiconductor substrate 101.

In addition, the n-type drift layer 102 has a parallel structure (hereinafter referred to as a parallel pn region) in which p-type regions (p-type column regions 104) and n-type regions (portions of the n-type drift layer 102 sandwiched between adjacent p-type column regions 104, hereinafter referred to as n-type column regions 103) that extend in a direction perpendicular to the substrate main surface and have a narrow width in a plane parallel to the substrate main surface are alternately arranged in a plane parallel to the substrate main surface. The p-type column regions 104 and n-type column regions 103 that constitute the parallel pn region are regions with a high impurity concentration corresponding to the n-type drift layer 102. In the parallel pn region, by making the impurity concentrations contained in the p-type column regions 104 and n-type column regions 103 approximately equal, a pseudo non-doped layer can be created in the off state to achieve high voltage resistance.

A p-type base region 105 is provided on the parallel pn region on the side of the active region 130 where an element is formed and through which a current flows when the SJ-MOSFET 150 is in an on-state. An n ⁺ -type source region 106 is provided inside the p-type base region 105. A gate insulating film 107 is provided across the surfaces of the p-type base region 105 and the n-type column region 103. A gate electrode 108 is provided on the surface of the gate insulating film 107, and an insulating film 113 is provided so as to cover the gate electrode 108. A source electrode 110 is provided on the n ⁺ -type source region 106, and a drain electrode 114 is provided on the back surface of the n ⁺ -type semiconductor substrate 101.

In the edge termination region 140 of the SJ-MOSFET 150 that surrounds the active region 130, a parallel pn region and an insulating film 113 are provided in the n-type drift layer 102, similar to the active region 130, and a drain electrode 114 is provided on the back surface of the n ⁺ -type semiconductor substrate 101.

In addition, in a power semiconductor element, the edge termination region 140 must also maintain a breakdown voltage, just like the active region 130. In order to obtain a high breakdown voltage in the edge termination region 140, known techniques include structures in which a field plate, a resurf, a guard ring, etc. are formed. FIG. 19 shows an SJ-MOSFET 150 having a resurf structure. In the SJ-MOSFET 150, when maintaining a breakdown voltage, the resurf region 117 is partially or completely depleted, thereby alleviating the electric field concentration in the edge termination region 140. The resurf region 117 may also be connected to a parallel pn region. In this case, a depletion layer extends from the junction of the parallel pn region connected to the resurf region 117, and the drift layer is completely depleted at a low voltage. As the voltage increases, the parallel pn region performs a guard ring effect, and the depletion layer further extends from the adjacent parallel pn regions, and the depletion layers combine with each other to form a depletion layer when completely depleted, thereby ensuring a high breakdown voltage.

For example, in an SJ-MOSFET having an n-type pillar layer 2 and a p-type pillar layer 3 in an element portion and an n-type pillar layer 10 and a p-type pillar layer 11 in an element termination portion, a high-resistance n ^-type layer 12 is provided on the upper surfaces of the n-type pillar layer 10 and the p-type pillar layer 11 in the element termination portion, an outermost p-type pillar layer 14 is provided between the n-type pillar layer 2 and the high-resistance n ^-type layer 12 in the element portion, a p-type base layer 4 is provided at the boundary between the element portion and the element termination portion, and a RESURF layer 13 is provided adjacent to the p-type base layer 4 (for example, see Patent Document 1 below).

Also, in an SJ-MOSFET in which the repetition pitch P2 of the second parallel pn layer 15 in the element peripheral portion 3 is narrower than the repetition pitch P1 of the first parallel pn layer 12 in the central portion of the element active portion 1, a semiconductor device is known which includes a p-base region 5 spanning a plurality of first p-type regions 14 and second p-type regions 17 at the boundary between the first parallel pn layer 12 and the second parallel pn layer 15, an n ^- surface region 19 surrounding the first parallel pn layer 12 is provided between the second parallel pn layer 15 and the first main surface, and two or more p ^- type guard ring regions 20 are provided spaced apart from each other on the first main surface side of the n-surface region 19 (see, for example, Patent Document 2 below).

In addition, a semiconductor device is known in which the p-type pillar region 6 in the peripheral region 120 contacts the p-type connection region 17, the p-type connection region 17 is in ohmic contact with the source electrode 10 via the body region 5', and an n-type depletable semiconductor region 18 is provided between the p-type connection region 17 and the first main surface 101, and the n-type depletable semiconductor region 18 has a doping concentration higher than that of the lightly doped semiconductor region 2 between the end of the pn column and the field stopper region 8 provided on the outermost periphery (see, for example, Patent Document 3 below).

JP 2006-5275 A JP 2013-149761 A U.S. Pat. No. 9,281,392

In the parallel pn region, when the amount of impurities in the n-type column region 103 is approximately equal to the amount of impurities in the p-type column region 104 (charge balance is "1"), the breakdown voltage of the SJ-MOSFET 150 is at its maximum value. However, the amount of impurities in the parallel pn region is prone to variation due to manufacturing variations in semiconductor devices. This can lead to an imbalance in the charge balance, making it easy for a decrease in breakdown voltage to occur. Furthermore, variations in the amount of impurities and the diffusion depth of the impurities in the resurf region 117 can also cause a further decrease in breakdown voltage. This can lead to the problem that elements with low breakdown voltages are likely to be produced.

The purpose of this invention is to provide a super-junction semiconductor device and a method for manufacturing a super-junction semiconductor device that can suppress a decrease in breakdown voltage due to manufacturing variations in order to solve the problems associated with the conventional technology described above.

In order to solve the above-mentioned problems and achieve the object of the present invention, a superjunction semiconductor device according to the present invention has the following features. The superjunction semiconductor device has an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region. A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on a front surface of a semiconductor substrate of a first conductivity type. A first parallel pn structure is provided in the active region on an upper surface of the first semiconductor layer, in which first columns of a first conductivity type and second columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second parallel pn structure is provided in the termination structure on an upper surface of the first semiconductor layer, in which third columns of a first conductivity type and fourth columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A first semiconductor region of a second conductivity type consisting of a plurality of regions spaced apart from each other is provided on a surface of the second parallel pn structure of the termination structure. A second semiconductor region of a second conductivity type is provided on a surface of a second column of a second conductivity type of the first parallel pn structure in the active region. A third semiconductor region of a first conductivity type is selectively provided on a surface layer of the second semiconductor region opposite to the semiconductor substrate side. A gate insulating film is provided in contact with the second semiconductor region. A gate electrode is provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region. The first semiconductor region has a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region. The first region, the second region, the third region, and the fourth region are connected to an electrode provided in the termination structure via the second semiconductor region . Alternatively , any one of the first region, the second region, the third region, and the fourth region has a first portion close to the active region, a second portion farther from the active region than the first portion, and a third portion farther from the active region than the second portion, and an impurity concentration D1 of the first portion, an impurity concentration D2 of the second portion, and an impurity concentration D3 of the third portion satisfy D1:D2=1.5:1 to 1.2:1 and D2:D3=1:0.75 to 1:0.5. In order to solve the above-mentioned problems and achieve the object of the present invention, a superjunction semiconductor device according to the present invention has the following features. The superjunction semiconductor device has an active region through which a current flows, and a termination structure that is disposed outside the active region and has a breakdown voltage structure surrounding the periphery of the active region. A first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is provided on a front surface of a semiconductor substrate of a first conductivity type. A first parallel pn structure is provided in the active region on the upper surface of the first semiconductor layer, in which a first column of a first conductivity type and a second column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A second parallel pn structure is provided in the termination structure on the upper surface of the first semiconductor layer, in which a third column of a first conductivity type and a fourth column of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. A first semiconductor region of a second conductivity type consisting of a plurality of regions spaced apart from each other is provided on a surface of the second parallel pn structure in the termination structure. A second semiconductor region of a second conductivity type is provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region. A third semiconductor region of a first conductivity type is selectively provided in a surface layer of the second semiconductor region opposite to the semiconductor substrate side. A gate insulating film is provided in contact with the second semiconductor region. A gate electrode is provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region. A fourth semiconductor region of a first conductivity type is provided in a portion of the surface of the first semiconductor region opposite to the semiconductor substrate. The first semiconductor region has a first region on the active region side, a second region separate from the first region, a third region separate from the second region, and a fourth region separate from the third region. The impurity concentration of any of the first region, the second region, the third region, and the fourth region increases with increasing distance from the active region.

In addition, in the super junction semiconductor device according to the present invention, in the above-mentioned invention, the first region , the second region, the third region and the fourth region of the first semiconductor region have an annular planar shape.

The superjunction semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the width of the first column and the width of the second column of the first parallel pn structure of the active region are wider than the width of the third column and the width of the fourth column of the second parallel pn structure of the termination structure.

Moreover, in the super junction semiconductor device according to the present invention, in the above-mentioned invention, a fourth semiconductor region of the first conductivity type is provided in a part of a surface of the first semiconductor region opposite to the semiconductor substrate.

In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a super-junction semiconductor device according to the present invention is a method for manufacturing a super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is formed on a front surface of a semiconductor substrate of a first conductivity type. Next, a second step is performed in which a lower first parallel pn structure is formed in the active region of the first semiconductor layer, in which first columns of the first conductivity type and second columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, and a second parallel pn structure is formed in the termination structure of the first semiconductor layer, in which third columns of the first conductivity type and fourth columns of the second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface. Next, in the active region, an upper first parallel pn structure is formed on the surface of the lower first parallel pn structure, and in the termination structure, a first semiconductor region of a second conductivity type is formed on the surface of the second parallel pn structure, the first semiconductor region being composed of a plurality of regions spaced apart from each other. Next, a fourth step is performed to form a second semiconductor region of a second conductivity type on the surface of the second column of the first parallel pn structure in the active region. Next, a fifth step is performed to selectively form a third semiconductor region of a first conductivity type on a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate side. Next, a sixth step is performed to form a gate insulating film in contact with the second semiconductor region. Next, a seventh step is performed to form a gate electrode on the surface of the gate insulating film opposite to the surface in contact with the second semiconductor region. In the third step, the upper first parallel pn structure and the first semiconductor region are simultaneously formed by epitaxial growth and ion implantation.

The method for manufacturing a superjunction semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the opening width of the photoresist for ion implantation when forming the second parallel pn structure is wider than the opening width of the photoresist for ion implantation when forming the first semiconductor region.

The manufacturing method of the super-junction semiconductor device according to the present invention is characterized in that in the third step, impurities are implanted into a plurality of locations by ion implantation, and the first semiconductor region is formed by thermally diffusing the implanted impurities.

The super-junction semiconductor device according to the present invention is characterized in that in the above-mentioned invention, the width w1 of the first region, the width w2 of the second region, the width w3 of the third region, and the width w4 of the fourth region satisfy w1≦w2≦w3≦w4.

The superjunction semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the second parallel pn structure has an inner structure on the active region side and an outer structure that is farther away from the active region than the inner structure, and the length of the fourth column of the outer structure from the top surface of the first semiconductor layer is equal to or less than the length of the fourth column of the inner structure from the top surface of the first semiconductor layer.

The super-junction semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the distance d1 from the depth from the top surface of the first semiconductor layer to the center of the first semiconductor region to the surface of the first portion, the distance d2 from the depth to the surface of the second portion, and the distance d3 from the depth to the surface of the third portion satisfy d1>d2>d3.

According to the above-mentioned invention, the resurf region (first semiconductor region of the second conductivity type) is divided into two or more. As a result, the resurf region closer to the stopper electrode acts as a buffer, and a steep drop in breakdown voltage can be mitigated. This makes it possible to suppress a drop in breakdown voltage due to manufacturing variations. In addition, when charge accumulates on the protective film, the movement of the equipotential lines stops at the point where the resurf region is divided, and the effect of the charge is localized. This makes it possible to suppress fluctuations in breakdown voltage when charge accumulates on the protective film of the semiconductor device.

In addition, because the movement of the equipotential lines stops at the point where the RESURF region is divided, by dividing the RESURF region into four, the effect of the electric charge can be localized more than in a form in which the RESURF region is divided into two, and the breakdown voltage fluctuation when electric charge accumulates on the protective film of the semiconductor device can be further suppressed. In addition, by forming the RESURF region so that it is narrower and has a lower impurity concentration as it moves toward the outside of the element, the breakdown voltage fluctuation when electric charge accumulates on the protective film of the semiconductor device can be further suppressed.

The super-junction semiconductor device and the method for manufacturing the super-junction semiconductor device according to the present invention have the effect of suppressing the decrease in breakdown voltage due to manufacturing variations.

1 is a cross-sectional view showing a structure of an SJ-MOSFET according to a first embodiment. 2 is a plan view of the A-A' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. 2 is a plan view of the B-B' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. 2 is another plan view of the B-B' portion of FIG. 1 showing the structure of the SJ-MOSFET according to the first embodiment. FIG. FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a second embodiment. 1 is a cross-sectional view showing an internal state of potential distribution in an SJ-MOSFET of a comparative example. 2 is a cross-sectional view showing an internal state of a potential distribution of the SJ-MOSFET according to the first embodiment; 11 is a cross-sectional view showing the internal state of the potential distribution of an SJ-MOSFET according to a second embodiment. 1 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 1). FIG. FIG. 2 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 2). FIG. 3 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 3). FIG. 4 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 4). FIG. 5 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 5). FIG. 6 is a cross-sectional view showing a state during manufacturing of the SJ-MOSFET according to the first and second embodiments (part 6). FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a third embodiment. FIG. 11 is a cross-sectional view showing a structure of an SJ-MOSFET according to a fourth embodiment. FIG. 11 is a cross-sectional view showing a detailed structure of a RESURF layer of an SJ-MOSFET according to a fourth embodiment. 1 is a graph showing the relationship between charge balance and breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. 1 is a graph showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. FIG. 1 is a cross-sectional view showing the structure of a conventional SJ-MOSFET.

The preferred embodiments of the superjunction semiconductor device and the method of manufacturing the superjunction semiconductor device according to the present invention will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, in layers and regions marked with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - marked with n or p mean that the impurity concentration is higher or lower than that of layers or regions not marked with them, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, but are not necessarily the same. Note that in the following description of the embodiments and the attached drawings, similar configurations are marked with the same reference numerals, and duplicate explanations will be omitted.

(Embodiment 1)
The super-junction semiconductor device according to the present invention will be described by taking an SJ-MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of an SJ-MOSFET according to a first embodiment. FIG. 2 is a plan view of the A-A' portion of FIG. 1 showing the structure of an SJ-MOSFET according to a first embodiment. FIG. 3 is a plan view of the B-B' portion of FIG. 1 showing the structure of an SJ-MOSFET according to a first embodiment. FIG. 4 is another plan view of the B-B' portion of FIG. 1 showing the structure of an SJ-MOSFET according to a first embodiment. FIG. 1 is a cross-sectional view of the a-a' portion of FIGS. 2 to 4.

The SJ-MOSFET 50 shown in FIG. 1 is an SJ-MOSFET 50 having a MOS (Metal Oxide Semiconductor) gate on the front surface (the surface on the p-type base region 5 side described later) of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon (Si). This SJ-MOSFET 50 has an active region 30 and an edge termination region 40 surrounding the active region 30. The active region 30 is a region through which current flows when in the on state. The edge termination region 40 is a region that relaxes the electric field on the front surface side of the substrate in the drift region and maintains a breakdown voltage. In the active region 30 in FIG. 1, only one unit cell (functional unit of the element) is shown, and other unit cells adjacent to it are omitted. The boundary between the active region 30 and the edge termination region 40 is the end of the p-type base region 5.

The n ⁺ type semiconductor substrate (first conductivity type semiconductor substrate) 1 is a silicon single crystal substrate doped with, for example, phosphorus (P). The n type drift layer (first conductivity type first semiconductor layer) 2 is a low concentration n type drift layer doped with, for example, phosphorus at an impurity concentration lower than that of the n ⁺ type semiconductor substrate. Hereinafter, the n ⁺ type semiconductor substrate 1 and the n type drift layer 2 are collectively referred to as a semiconductor substrate. A MOS gate structure (element structure) is formed on the front surface side of the semiconductor substrate. In addition, a drain electrode 14 is provided on the back surface of the semiconductor substrate.

A first parallel pn region is provided on the active region 30 side of the SJ-MOSFET 50. In the first parallel pn region, n-type column regions 3a and p-type column regions 4a are arranged alternately and repeatedly. The p-type column regions 4a are provided so as not to reach the surface of the n ⁺ -type semiconductor substrate layer 1 from the surface of the n-type drift layer 2. As shown in FIGS. 2 to 4, the planar shape of the n-type column regions 3a and p-type column regions 4a in the active region 30 is a stripe shape.

Furthermore, a p-type base region (second semiconductor region of a second conductivity type) 5 is selectively provided in contact with the p-type column region 4a in the surface layer of the n-type drift layer 2, and an n ⁺ -type source region (third semiconductor region of a first conductivity type) 6 is selectively provided in the surface layer of the p-type base region 5. A gate electrode 8 is provided via a gate insulating film 7 on the surface of a portion of the p-type base region 5 that is sandwiched between the n ⁺ -type source region 6 and the n-type column region 3a. The gate electrode 8 may be provided on the surface of the n-type column region 3a via the gate insulating film 7.

An insulating film 13 is provided on the front surface side of the semiconductor substrate so as to cover the gate electrode 8. A source electrode 10 contacts the n ⁺ type source region 6 and the p type base region 5 through a contact hole opened in an interlayer insulating film (not shown), and is electrically connected to the n ⁺ type source region 6 and the p type base region 5.

The source electrode 10 is electrically insulated from the gate electrode 8 by the insulating film 13. A protective film (not shown), such as a passivation film made of polyimide, is optionally provided on the source electrode 10.

The field plate electrode 15 is disposed outside the source electrode 10 (toward the edge termination region 40) and separated from the source electrode 10. The field plate electrode 15 is provided in a substantially annular shape along the boundary between the active region 30 and the edge termination region 40. The field plate electrode 15 may also function as a gate wiring electrically connected to the gate electrode 8.

A second parallel pn region is also provided on the edge termination region 40 side of the SJ-MOSFET 50. As shown in FIG. 3, the planar shape of the n-type column region 3b and the p-type column region 4b in the edge termination region 40 may be a stripe shape, and as shown in FIG. 4, the planar shape of the n-type column region 3b and the p-type column region 4b in the edge termination region 40 may be a rectangular shape.

Also, as shown in Figures 1 to 4, the width of the n-type column region 3a and the width of the p-type column region 4a in the active region 30 are wider than the width of the n-type column region 3b and the width of the p-type column region 4b in the edge termination region 40, respectively. This allows the impurity concentration of the second parallel pn structure in the edge termination region 40 to be lower than the impurity concentration of the first parallel pn region in the active region 30. This allows the withstand voltage of the edge termination region 40 to be higher than the withstand voltage of the active region 30.

An n-type drift layer 2 is provided outside the second parallel pn region so as to surround the second parallel pn region, and an n ⁺ -type region (not shown) functioning as a channel stopper may be provided on the surface of the n-type drift layer 2. A resurf region (first semiconductor region of a second conductivity type) 17 is provided on the surface of the second parallel pn region. An insulating film 13 is provided on the surfaces of the resurf region 17 and the n-type drift layer 2. In addition, a stopper electrode 16 is provided on the surface of the n ⁺ -type region.

As shown in Figures 1 and 2, in the first embodiment, the resurf region 17 extends toward the stopper electrode 16 so as to overlap the outer end of the field plate electrode 15 in a plan view, and is divided into two or more regions. In the example of Figure 1, the resurf region 17 is divided into two regions: a first resurf region 17a close to the active region 30, and a second resurf region 17b away from the active region 30.

As shown in FIG. 2, the first resurf region 17a and the second resurf region 17b are provided in a circular shape in plan view. The first resurf region 17a and the second resurf region 17b are also electrically connected to the p-type column region 4a of the second parallel pn region. Furthermore, as shown in FIG. 1, a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b may be disposed between the first resurf region 17a and the second resurf region 17b.

An n-type region 18 is provided between the first resurf region 17a and the second resurf region 17b and the insulating film 13 thereover. An end 25 of the first resurf region 17a on the active region 30 side may be in contact with the insulating film 13. The end 25 of the first resurf region 17a may be electrically connected to the field plate electrode 15. The end 25 of the first resurf region 17a may be provided in a ring shape.

As described above, when the breakdown voltage is maintained, the resurf region 17 is partially or completely depleted, thereby alleviating the electric field concentration in the edge termination region 40. By dividing the resurf region 17, the potential in the resurf region 17 can be shared among the regions, and the electric field strength increases partially. Therefore, even if the charge balance is such that there are more p-type impurities in the second parallel pn region due to manufacturing variations, or if the concentration of p-type impurities in the resurf region 17 increases, the resurf region 17b closer to the stopper electrode 16 acts as a buffer, and a steep decrease in breakdown voltage can be alleviated. This makes it possible to suppress the decrease in breakdown voltage due to manufacturing variations.

(Embodiment 2)
Fig. 5 is a cross-sectional view showing the structure of an SJ-MOSFET according to the second embodiment. The portion A-A' in Fig. 5 is the same as the plan view of Fig. 2 showing the structure of the SJ-MOSFET according to the first embodiment. The portion B-B' in Fig. 5 showing the structure of the SJ-MOSFET according to the second embodiment is the same as the plan view of Fig. 3 showing the structure of the SJ-MOSFET according to the first embodiment. The other plan views of the portion B-B' in Fig. 5 showing the structure of the SJ-MOSFET according to the second embodiment are the same as the plan view of Fig. 4.

The second embodiment differs in that there is no p-type column region 4b between the first resurf region 17a and the second resurf region 17b that is not connected to the first resurf region 17a and the second resurf region 17b.

In the second embodiment, the same effect as in the first embodiment can be obtained even if a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b is not disposed between the first resurf region 17a and the second resurf region 17b.

In addition, within one SJ-MOSFET 50, there may be a mixture of a portion in which a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b is disposed between the first resurf region 17a and the second resurf region 17b shown in FIG. 1, and a portion in which a p-type column region 4b that is not connected to the first resurf region 17a and the second resurf region 17b is not disposed between the first resurf region 17a and the second resurf region 17b shown in FIG. 5.

However, when they are mixed, the first resurf region 17a and the second resurf region 17b are separated from each other. In addition, the width w1 of the first resurf region 17a and the width w2 of the second resurf region 17b that is separated from the active region 30 satisfy the relationship described below.

The SJ-MOSFET 50 shown in FIG. 1 is used sealed with a sealing resin such as mold resin. If the sealing resin and the SJ-MOSFET 50 do not adhere well to each other, ionic substances such as moisture may get between the sealing resin and the SJ-MOSFET 50. In this case, charges are accumulated on the protective film of the SJ-MOSFET 50.

Figure 6 is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example differs from the SJ-MOSFET of the first embodiment in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b. As shown in Figure 6, if the resurf region 117 is not divided, the equipotential lines 60 are arranged almost evenly on the resurf region 117. In this state, if charges are accumulated on the surface protection film 70, the equipotential lines 60 move inward (toward the active region 30) or outward (toward the stopper electrode 16). For example, if a positive charge is accumulated, the equipotential lines 60 move inward, and if a negative charge is accumulated, the equipotential lines 60 move outward. In this case, a dense portion of the equipotential lines 60 occurs at the end of the resurf region 117, causing the breakdown voltage to fluctuate.

Figure 7A is a cross-sectional view showing the internal state of the potential distribution of the SJ-MOSFET according to the first embodiment. As shown in Figure 7A, when the resurf region 17 is divided, the interval between the equipotential lines 60 becomes wider at the divided points. When charge accumulates on the surface protective film 70 in this state, even if the equipotential lines 60 move inward or outward, the movement of the equipotential lines 60 stops at the divided points. This makes it possible to localize the effect of the charge. Therefore, it is possible to suppress the breakdown voltage fluctuation when charge accumulates on the protective film of the semiconductor device. In addition, since the movement of the equipotential lines 60 stops at the divided points, the more divisions of the resurf region 17, the more the breakdown voltage fluctuation when charge accumulates can be suppressed.

Figure 7B is a diagram showing the internal state of the potential distribution of the SJ-MOSFET according to the second embodiment. Figure 7B can achieve the same effect as Figure 7A.

When the resurf region 17 is divided into two as shown in Figs. 1 and 5, the ratio of the width w1 of the first resurf region 17a close to the active region 30 to the width w2 of the second resurf region 17b farther from the active region 30 is preferably in the range of 3:7 to 5:5. Here, the width w1 of the first resurf region 17a refers to the length from the inside to the outside of the first resurf region 17a. The same is true for the width w2 of the second resurf region 17b. In other words, the range from when the width w1 of the first resurf region 17a is 3 and the width w2 of the second resurf region 17b is 7 to when the width w1 of the first resurf region 17a is 5 and the width w2 of the second resurf region 17b is 5 is preferable.

In order to maintain the breakdown voltage, it is desirable to completely deplete the resurf region, but the breakdown voltage can also be maintained by partially depleting the resurf region. When the first resurf region 17a on the active region 30 side is partially depleted as shown in Figures 7A and 7B, the spacing between the equipotential lines 60 tends to be wider overall than when the resurf region 117 is completely depleted as shown in Figure 6. In addition, the spacing between the equipotential lines 60 becomes narrower (more dense) in the region sandwiched between the first resurf region 17a and the second resurf region 17b. As a result, the spacing between the equipotential lines 60 in the second resurf region 17b becomes wider, and the electric field is relaxed. By relaxing the electric field on the side closer to the stopper electrode 16, it is possible to suppress the decrease in the breakdown voltage due to the surface charge.

Furthermore, when the resurf region 17 is divided into two, it is preferable that the width w1 of the first resurf region 17a close to the active region 30 is shorter than the width w2 of the second resurf region 17b away from the active region 30 in order to reduce the decrease in breakdown voltage due to surface charges. Also, when the resurf region 17 is divided into three or more regions, it is preferable that the width of the resurf region closest to the stopper electrode 16 is made the longest in order to reduce the decrease in breakdown voltage due to surface charges.

In addition, by providing the n-type region 18 between the resurf region 17 and the insulating film 13, the fluctuation in the breakdown voltage of the edge termination region 40 due to the surface charge can be more stabilized. In addition, the n-type region 18 can reduce the intrusion of holes (positive holes) into the insulating film 13.

(Method of Manufacturing Super-Junction Semiconductor Device According to First and Second Embodiments)
Next, a method for manufacturing the super-junction semiconductor device according to the first and second embodiments will be described. Figures 8 to 13 are cross-sectional views showing the state during the manufacturing process of the SJ-MOSFET 50 according to the first and second embodiments. First, an n ⁺ type semiconductor substrate 1 made of silicon and serving as the n ⁺ type drain layer is prepared. Next, an n type layer 2a having a lower impurity concentration than the n ⁺ type semiconductor substrate 1 is epitaxially grown on the front surface of the n ⁺ type semiconductor substrate 1. The state up to this point is shown in Figure 8.

The n-type layer 2a may be epitaxially grown by doping with an n-type impurity so that the impurity concentration of the n-type layer 2a is, for example, 1.0×10 ¹⁴ /cm ³ or more and 1.0×10 ¹⁷ /cm ³ or less.

Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2a using photolithography technology, for example, from photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form p-type regions 19 in the surface layer of the n-type layer 2a. The state up to this point is shown in FIG. 9. Next, the ion implantation mask 20a is removed.

Next, an n-type layer 2b having the same impurity concentration as the n-type layer 2a is epitaxially grown on the front surface side of the n-type layer 2a. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2b by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2b. Next, the ion implantation mask 20a is removed.

Next, an n-type layer 2c having the same impurity concentration as the n-type layer 2b is epitaxially grown on the front surface side of the n-type layer 2b. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2c by photolithography, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2c. Next, the ion implantation mask 20a is removed.

Next, an n-type layer 2d having the same impurity concentration as the n-type layer 2c is epitaxially grown on the front surface side of the n-type layer 2c. Next, an ion implantation mask 20a having a predetermined opening width is formed on the surface of the n-type layer 2d by photolithography technology, for example, using photoresist. At this time, the opening width w11 of the active region and the pitch P1 of the openings are made wider than the opening width w12 of the edge termination region and the pitch P2 of the openings. Using this ion implantation mask 20a as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2d. This forms the first and second parallel pn regions in the lower part, which are composed of the n-type layers 2a to 2d and the p-type region 19. The state up to this point is shown in FIG. 10.

In the example of Figure 10, ion implantation and epitaxial growth are repeated four times, but this is not limited to this example, and the number of ion implantations and epitaxial growth can be changed as appropriate depending on the target characteristics such as breakdown voltage.

Next, the ion implantation mask 20a is removed. Next, an n-type layer 2e having the same impurity concentration as the n-type layer 2d is epitaxially grown on the front surface side of the n-type layer 2d. Next, an ion implantation mask 20b having a predetermined opening width is formed on the surface of the n-type layer 2e by photolithography technology, for example, using photoresist. At this time, the opening width w13 of the edge termination region and the pitch P3 of the openings are made narrower than the opening width w12 of the edge termination region and the pitch P2 of the openings of the mask formed on the n-type layers 2a to 2d. In addition, the photoresist width w15 at the point where the resurf region 17 is divided into the first resurf region 17a and the second resurf region 17b is made wider than the photoresist width w14 (=P3-w13) of the edge termination region. Using this ion implantation mask 20b as a mask, ion implantation 21 of p-type impurities, for example boron (B), is performed to form a p-type region 19 in the surface layer of the n-type layer 2e. As a result, first and second upper parallel pn regions consisting of the n-type layer 2e and the p-type region 19 are formed in the active region 30, and a resurf region 17 is formed in the edge termination region 40. The state up to this point is shown in FIG. 11. Next, the ion implantation mask 20b is removed.

Next, n-type layer 2f, which has the same impurity concentration as n-type layer 2e, is epitaxially grown on the front surface side of n-type layer 2e. The state up to this point is shown in Figure 12.

Next, a heat treatment (annealing) is performed to activate the p-type regions 19. This heat treatment diffuses the injected impurities, and the diffused impurities connect vertically to form p-type column regions 4a, 4b. In addition, because the p-type regions 19 formed in the n-type layer 2e are spaced closely together, the diffused impurities connect horizontally to form the RESURF region 17.

Here, in the edge termination region 40, the mask opening width is narrower than in the active region 30, so the amount of impurities implanted in one location is smaller and the amount of diffusion is smaller. Therefore, the impurities do not reach the surface of the n-type region 2f during heat treatment. As a result, the n-type region 18 is formed on the upper part of the resurf region 17. On the other hand, in the active region 30, the amount of impurities is large and the amount of diffusion is large, so the impurities reach the surface of the n-type region 2f and the p-type column region 4a is exposed on the surface. Depending on the amount of impurities, the impurities may not reach the surface of the n-type region 2f even in the active region 30, but since ion implantation is performed when forming the p-type base region 5, in the active region 30, the p-type column region 4a and the p-type base region 5 are connected and the p-type region is exposed on the surface. The state up to this point is shown in FIG. 13.

Next, a mask having desired openings is formed, for example, from resist, on the surfaces of the n-type column region 3a and the p-type column region 4a on the active region 30 side by photolithography. Then, using this resist mask as a mask, p-type impurities are ion-implanted by ion implantation. As a result, a p-type base region 5 is formed in the entire surface region of the p-type column region 4a and in part of the surface region of the n-type column region 3a. Next, the mask used during the ion implantation to form the p-type base region 5 is removed.

Next, a mask having desired openings is formed on the surface of the p-type base region 5 by photolithography, for example, using a resist. Then, using this resist mask as a mask, n-type impurity ions are implanted by ion implantation. As a result, an n ⁺ -type source region 6 is formed in a part of the surface region of the p-type base region 5. Next, the mask used during the ion implantation to form the n ⁺ -type source region 6 is removed.

Next, a heat treatment (annealing) is performed to activate the p-type base region 5 and the n ⁺ -type source region 6. The order in which the p-type base region 5 and the n ⁺ -type source region 6 are formed can be changed in various ways.

Next, the front surface side of the semiconductor substrate is thermally oxidized to form a gate insulating film 7. Next, a polycrystalline silicon layer doped with, for example, phosphorus is formed as a gate electrode 8 on the gate insulating film 7. Next, the polycrystalline silicon layer is patterned and selectively removed, leaving a polycrystalline silicon layer on a portion of the p-type base region 5 sandwiched between the n ⁺ -type source region 6 and the n-type column region 3a. At this time, the polycrystalline silicon layer may be left on the n-type column region 3a.

Next, for example, phosphorus glass (PSG: Phospho Silicate Glass) is formed as the insulating film 13 so as to cover the gate electrode 8. Next, the insulating film 13 and the gate insulating film 7 are patterned and selectively removed. For example, the insulating film 13 and the gate insulating film 7 on the n ⁺ type source region 6 are removed to form a contact hole and expose the n ⁺ type source region 6. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

Next, the source electrode 10, the field plate electrode 15, and the stopper electrode 16 are formed by sputtering, and the source electrode 10, the field plate electrode 15, and the stopper electrode 16 are patterned by photolithography and etching. At this time, the source electrode 10 is embedded in the contact hole, and the n ⁺ type source region 6 and the source electrode 10 are electrically connected. Note that a tungsten plug or the like may be embedded in the contact hole via a barrier metal.

Next, for example, a nickel film is formed as the drain electrode 14 on the surface (the back surface of the semiconductor base) of the n ⁺ type semiconductor substrate 1. Then, a heat treatment is performed to form an ohmic junction between the n ⁺ type semiconductor substrate 1 and the drain electrode 14. This completes the SJ-MOSFET 50 shown in FIG.

As described above, according to the first and second embodiments, the resurf region is divided into two or more. This allows the resurf region closer to the stopper electrode to act as a buffer, mitigating the steep drop in breakdown voltage. This makes it possible to suppress the drop in breakdown voltage due to manufacturing variations. Furthermore, when charge accumulates on the protective film, the movement of the equipotential lines stops at the point where the resurf region is divided, and the effect of the charge is localized. This makes it possible to suppress the fluctuation in breakdown voltage when charge accumulates on the protective film of the semiconductor device.

(Embodiment 3)
14 is a cross-sectional view showing the structure of an SJ-MOSFET according to embodiment 3. Embodiment 3 differs from embodiments 1 and 2 in that the resurf region 17 is divided into four regions: a first resurf region 17a, a second resurf region 17b, a third resurf region 17c, and a fourth resurf region 17d.

In the third embodiment, the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d preferably have a relationship of w1≦w2≦w3≦w4. In FIG. 14, the end 25 of the first resurf region 17a is a part of the p-type base region 5, and the first resurf region 17a may be connected to the field plate electrode 15a via the p-type base region 5. Similarly, the second resurf region 17b, the third resurf region 17c, and the fourth resurf region 17d may be connected to the field plate electrode 15b, the field plate electrode 15c, and the field plate electrode 15d via the p-type base region 5, respectively.

The field plate electrode 15a may function as a gate electrode electrically connected to the gate electrode 8. However, if the field plate electrodes 15b, 15c, and 15d are electrically connected to the gate electrode 8, they will have the same potential as the gate electrode 8 and will not be able to maintain the breakdown voltage. Therefore, the field plate electrodes 15b, 15c, and 15d are not electrically connected to the gate electrode 8.

The p-type column region 4c and the p-type column region 4d arranged at both ends of the third resurf region 17c may or may not be in contact with the third resurf region 17c.

As described above, in the third embodiment, the resurf region is divided into four. This makes it possible to alleviate the steep drop in breakdown voltage, as in the first and second embodiments, and to suppress the drop in breakdown voltage due to manufacturing variations. Furthermore, since the movement of the equipotential lines stops at the point where the resurf region is divided, the third embodiment can localize the effect of charge more than the first and second embodiments in which the resurf region is divided into two. Therefore, the third embodiment can suppress the breakdown voltage fluctuation when charge accumulates on the protective film of the semiconductor device more than the first and second embodiments.

(Embodiment 4)
15 is a cross-sectional view showing the structure of an SJ-MOSFET according to the fourth embodiment. The fourth embodiment differs from the third embodiment in the impurity concentration of the fourth resurf region 17d and the length of the outer p-type column region 4b. In the fourth embodiment, similarly to the third embodiment, the width w1 of the first resurf region 17a, the width w2 of the second resurf region 17b, the width w3 of the third resurf region 17c, and the width w4 of the fourth resurf region 17d preferably have a relationship of w1≦w2≦w3≦w4.

15, in the fourth embodiment, the second parallel pn structure in the edge termination region 40 is composed of an inner structure S1 on the inside of the element (active region 30 side) and an outer structure S2 on the outside of the element (stopper electrode 16 side) that is farther away from the active region 30 than the inner structure S1. The length t2 from the surface of the n-type drift layer of the p-type column region 4b of the outer structure S2 may be shorter than or equal to the length t1 from the surface of the n-type drift layer of the p-type column region 4b of the inner structure S1 (length t2 may be equal to or less than length t1 (t2≦t1)). Note that the p-type column region 4c and the p-type column region 4d arranged at both ends of the third resurf region 17c may or may not be in contact with the third resurf region 17c.

Figure 16 is a cross-sectional view showing a detailed structure of the resurf layer of the SJ-MOSFET according to the fourth embodiment. Figure 16 is an enlarged view of the fourth resurf region 17d. As shown in Figure 16, the width of the fourth resurf region 17d becomes narrower as it approaches the outside of the element. Also, the impurity concentration of the fourth resurf region 17d becomes lower as it approaches the outside of the element. The fourth resurf region 17d has a first portion 17d1 on the inside of the element (the side closer to the active region 30), a second portion 17d2 that is farther from the active region 30 than the first portion 17d1, and a third portion 17d3 on the outside of the element that is farther from the active region 30 than the second portion 17d2. The (diffusion) distance from the resurf region center depth t3 of the first portion 17d1 to the surface is d1, the impurity concentration is D1, the (diffusion) distance from the resurf region center depth t3 of the second portion 17d2 to the surface is d2, the impurity concentration is D2, the (diffusion) distance from the resurf region center depth t3 of the third portion 17d3 to the surface is d3, and the impurity concentration is D3. In this case, it is preferable that d1>d2>d3, D1:D2=1.5:1 to 1.2:1, and D2:D3=1:0.75 to 1:0.5.

In the fourth embodiment, only the fourth resurf region 17d is shaped so that its width becomes narrower and its impurity concentration becomes lower toward the outside of the element, but the first resurf region 17a, the second resurf region 17b, and the third resurf region 17c on the inside may be shaped in a similar manner.

As explained above, in the fourth embodiment, the fourth RESURF region is shaped so that the width becomes narrower and the impurity concentration becomes lower as it moves toward the outside of the element. This makes it possible for the fourth embodiment to suppress the breakdown voltage fluctuation when charge accumulates on the protective film of the semiconductor device more effectively than the first to third embodiments.

Figure 17 is a graph showing the relationship between charge balance and breakdown voltage in the SJ-MOSFETs according to the first, third and fourth embodiments and the SJ-MOSFET of the comparative example. The SJ-MOSFET of the comparative example differs from the SJ-MOSFET of the first embodiment in that the resurf region 117 is not divided into the first resurf region 17a and the second resurf region 17b as shown in Figure 6. In Figure 17, the vertical axis indicates the breakdown voltage of the SJ-MOSFET in V. The horizontal axis indicates the charge balance, with charge balance "1" indicating a state in which the amount of impurities in the n-type column regions 3a and 3b is approximately equal to the amount of impurities in the p-type column regions 4a and 4b in the first and second parallel pn regions, the side closer to the origin than charge balance "1" (the (n-rich) side) indicating a state in which the amount of n-type impurities is greater, and the side farther from the origin than charge balance "1" (the (p-rich) side) indicating a state in which the amount of p-type impurities is greater.

As shown in FIG. 17, in the case of charge balance "1", the SJ-MOSFETs according to the first, third and fourth embodiments have the same breakdown voltage as the SJ-MOSFET of the comparative example. Furthermore, even in a state where the charge balance is unbalanced (a state where the amount of either the n-type or p-type impurity is greater), the SJ-MOSFETs according to the first, third and fourth embodiments have a smaller drop in breakdown voltage than the SJ-MOSFET of the comparative example. Furthermore, in a state where the charge balance is unbalanced, the SJ-MOSFETs according to the third and fourth embodiments have a smaller drop in breakdown voltage than the SJ-MOSFET of the first embodiment.

The same effect can be obtained with the SJ-MOSFET according to the second embodiment. In addition, the same effect can be obtained even if the cross-sectional shape shown in FIG. 1 according to the first embodiment and the cross-sectional shape shown in FIG. 5 according to the second embodiment are mixed in one SJ-MOSFET.

Figure 18 is a graph showing the relationship between the surface charge and the breakdown voltage in the SJ-MOSFETs according to the first, third, and fourth embodiments and the comparative SJ-MOSFET. In Figure 18, the vertical axis shows the breakdown voltage of the SJ-MOSFET in V. The horizontal axis shows the surface charge. On the horizontal axis, the position of 0 indicates a state in which the surface charge is zero, the position closer to the origin than the position of 0 (the negative (-) side) indicates a state in which there is more negative charge, and the position farther from the origin than the position of 0 (the positive (+) side) indicates a state in which there is more positive charge. Figure 18 also shows the relationship between the surface charge and the breakdown voltage in the case of a charge balance of "1". The surface charge is the charge accumulated in a surface protective film (such as the surface protective film 70 shown in Figures 6, 7A, and 7B) arranged on the top surface of the superjunction semiconductor device (SJ-MOSFET).

As shown in FIG. 18, when there is zero surface charge, the SJ-MOSFETs according to the first, third, and fourth embodiments have the same breakdown voltage as the SJ-MOSFET of the comparative example. The SJ-MOSFET of the first embodiment has the same breakdown voltage as the SJ-MOSFET of the comparative example, even when there is more negative charge. On the other hand, when there is more positive charge, the SJ-MOSFET of the first embodiment experiences less of a decrease in breakdown voltage than the SJ-MOSFET of the comparative example.

The SJ-MOSFETs according to the third and fourth embodiments have less drop in withstand voltage than the SJ-MOSFET of the comparative example, even when there is more negative charge or more positive charge. Furthermore, the SJ-MOSFET according to the third embodiment has the least drop in withstand voltage when there is more positive charge. The SJ-MOSFET according to the fourth embodiment has the least drop in withstand voltage when there is more negative charge.

The same effect can be obtained with the SJ-MOSFET according to the second embodiment. In addition, the same effect can be obtained even if the cross-sectional shape shown in FIG. 1 according to the first embodiment and the cross-sectional shape shown in FIG. 5 according to the second embodiment are mixed in one SJ-MOSFET.

In the above, the present invention has been described with reference to an example in which a MOS gate structure is constructed on the first main surface of a silicon substrate, but the present invention is not limited to this, and various changes can be made to the type of semiconductor (e.g., silicon carbide (SiC)), the surface orientation of the main surface of the substrate, and the like. Also, in each embodiment of the present invention, the first conductivity type is p-type and the second conductivity type is n-type, but the present invention is equally valid even if the first conductivity type is n-type and the second conductivity type is p-type.

As described above, the super-junction semiconductor device and the method for manufacturing the super-junction semiconductor device according to the present invention are useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines, etc.

1, 101 n ⁺ type semiconductor substrate 2, 102 n type drift layer 2a to 2f n type layer 3a, 3b, 103 n type column region 4a, 4b, 4c, 4d 104 p type column region 5, 105 p type base region 6, 106 n ⁺ type source region 7, 107 gate insulating film 8, 108 gate electrode 10, 110 source electrode 13, 113 insulating film 14, 114 drain electrode 15 field plate electrode 15a field plate electrode 15b field plate electrode 15c field plate electrode 15d field plate electrode 16 stopper electrode 17, 117 resurf region 17a first resurf region 17b second resurf region 17c third resurf region 17d fourth resurf region 18 n type region 19 p type region 20a, 20b ion implantation mask 21 ion implantation 25 End of first resurf region 30, 130 Active region 40, 140 Edge termination region 50, 150 SJ-MOSFET
60 Equipotential line 70 Surface protective film w1 Width of first resurf region w2 Width of second resurf region w3 Width of third resurf region w4 Width of fourth resurf region w11 Opening width of active region w12 Opening width of edge termination region w13 Opening width of edge termination region w14 Photoresist width of edge termination region w15 Photoresist width P1 at a location divided into first resurf region 17a and second resurf region 17b Pitch of openings (active region)
P2 Pitch of openings (edge termination area)
P3 Pitch of openings (edge termination area)

Claims (12)

A super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region,
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a first parallel pn structure provided in the active region, the first columns having a first conductivity type and second columns having a second conductivity type being repeatedly and alternately arranged in a plane parallel to the front surface, the first semiconductor layer being provided on an upper surface of the first semiconductor layer;
a second parallel pn structure provided in the termination structure, in which third columns of a first conductivity type and fourth columns of a second conductivity type are provided on an upper surface of the first semiconductor layer and are repeatedly and alternately arranged in a plane parallel to the front surface;
a first semiconductor region of a second conductivity type, the first semiconductor region being formed of a plurality of regions spaced apart from one another and provided on a surface of the second parallel pn structure of the termination structure;
a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region;
a third semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor region;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region;
Equipped with
the first semiconductor region has a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region;
a first region, a second region, a third region, and a fourth region, each of which is connected to an electrode provided in the termination structure portion via the second semiconductor region; A super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region,
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a first parallel pn structure provided in the active region, the first columns having a first conductivity type and second columns having a second conductivity type being repeatedly and alternately arranged in a plane parallel to the front surface, the first semiconductor layer being provided on an upper surface of the first semiconductor layer;
a second parallel pn structure provided in the termination structure, in which third columns of a first conductivity type and fourth columns of a second conductivity type are provided on an upper surface of the first semiconductor layer and are repeatedly and alternately arranged in a plane parallel to the front surface;
a first semiconductor region of a second conductivity type, the first semiconductor region being formed of a plurality of regions spaced apart from one another and provided on a surface of the second parallel pn structure of the termination structure;
a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region;
a third semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor region;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region;
a fourth semiconductor region of the first conductivity type provided on a portion of a surface of the first semiconductor region opposite to the semiconductor substrate;
Equipped with
the first semiconductor region has a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region;
1. A super-junction semiconductor device, comprising: a first region, a second region, a third region, and a fourth region, the impurity concentration of which increases as the first region approaches the active region. A super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region,
a semiconductor substrate of a first conductivity type;
a first semiconductor layer of a first conductivity type provided on a front surface of the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
a first parallel pn structure provided in the active region, the first columns having a first conductivity type and second columns having a second conductivity type being repeatedly and alternately arranged in a plane parallel to the front surface, the first semiconductor layer being provided on an upper surface of the first semiconductor layer;
a second parallel pn structure provided in the termination structure, in which third columns of a first conductivity type and fourth columns of a second conductivity type are provided on an upper surface of the first semiconductor layer and are repeatedly and alternately arranged in a plane parallel to the front surface;
a first semiconductor region of a second conductivity type, the first semiconductor region being formed of a plurality of regions spaced apart from one another and provided on a surface of the second parallel pn structure of the termination structure;
a second semiconductor region of a second conductivity type provided on a surface of the second column of the second conductivity type of the first parallel pn structure in the active region;
a third semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor region on the opposite side to the semiconductor substrate;
a gate insulating film in contact with the second semiconductor region;
a gate electrode provided on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region;
Equipped with
the first semiconductor region has a first region on the active region side, a second region separated from the first region, a third region separated from the second region, and a fourth region separated from the third region;
any one of the first region, the second region, the third region, and the fourth region has a first portion close to the active region, a second portion farther from the active region than the first portion, and a third portion farther from the active region than the second portion;
The super-junction semiconductor device is characterized in that an impurity concentration D1 of the first portion, an impurity concentration D2 of the second portion, and an impurity concentration D3 of the third portion satisfy D1:D2=1.5:1 to 1.2:1 and D2:D3=1:0.75 to 1:0.5. A superjunction semiconductor device according to any one of claims 1 to 3, characterized in that the first region, the second region, the third region, and the fourth region of the first semiconductor region have a circular planar shape. A superjunction semiconductor device according to any one of claims 1 to 4, characterized in that the width of the first column and the width of the second column of the first parallel pn structure of the active region are wider than the width of the third column and the width of the fourth column of the second parallel pn structure of the termination structure. 6. The super- junction semiconductor device according to claim 1, further comprising a fourth semiconductor region of the first conductivity type in a portion of the surface of the first semiconductor region opposite to the semiconductor substrate. 1. A method for manufacturing a super-junction semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the active region, comprising:
a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a semiconductor substrate of a first conductivity type, the first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate;
a second step of forming a lower first parallel pn structure in the active region of the first semiconductor layer, in which first columns of a first conductivity type and second columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface, and a second parallel pn structure in the termination structure portion of the first semiconductor layer, in which third columns of a first conductivity type and fourth columns of a second conductivity type are repeatedly and alternately arranged in a plane parallel to the front surface;
a third step of forming an upper first parallel pn structure on a surface of the lower first parallel pn structure in the active region to form a first parallel pn structure, and a third step of forming a first semiconductor region of a second conductivity type consisting of a plurality of regions spaced apart from each other on a surface of the second parallel pn structure in the termination structure;
a fourth step of forming a second semiconductor region of a second conductivity type on a surface of the second column of the first parallel pn structure in the active region;
a fifth step of selectively forming a third semiconductor region of a first conductivity type in a surface layer of the second semiconductor region on an opposite side to the semiconductor substrate;
a sixth step of forming a gate insulating film in contact with the second semiconductor region;
a seventh step of forming a gate electrode on a surface of the gate insulating film opposite to a surface in contact with the second semiconductor region;
Including,
a first semiconductor region formed on the first semiconductor substrate by epitaxial growth and ion implantation, the first semiconductor region being formed on the first semiconductor substrate by epitaxial growth and ion implantation, and the second semiconductor region being formed on the first semiconductor substrate by epitaxial growth and ion implantation. The method for manufacturing a superjunction semiconductor device according to claim 7, characterized in that the opening width of the photoresist for ion implantation when forming the second parallel pn structure is wider than the opening width of the photoresist for ion implantation when forming the first semiconductor region. The method for manufacturing a superjunction semiconductor device according to claim 7 or 8, characterized in that in the third step, impurities are implanted into a plurality of locations by ion implantation, and the first semiconductor region is formed by thermally diffusing the implanted impurities. The super-junction semiconductor device according to any one of claims 1 to 3, characterized in that the width w1 of the first region, the width w2 of the second region, the width w3 of the third region, and the width w4 of the fourth region satisfy w1 ≦ w2 ≦ w3 ≦ w4. the second parallel pn structure has an inner structure on the active region side and an outer structure farther away from the active region than the inner structure;
The superjunction semiconductor device according to any one of claims 1 to 3 and 10, characterized in that the length of the fourth column of the outer structure from the top surface of the first semiconductor layer is less than or equal to the length of the fourth column of the inner structure from the top surface of the first semiconductor layer. The superjunction semiconductor device according to claim 3, characterized in that the distance d1 from the depth from the top surface of the first semiconductor layer to the center of the first semiconductor region to the surface of the first portion, the distance d2 from the depth to the surface of the second portion, and the distance d3 from the depth to the surface of the third portion satisfy d1>d2>d3.

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