JP2019036591A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method, for providing a high breakdown voltage semiconductor device with high reliability.SOLUTION: A semiconductor device 1 includes: a semiconductor substrate 10 made of silicon carbide; a first insulation film 11; a first electrode 15; a second electrode 14 including a bonding part 14a and a peripheral edge part 14b; and a second insulation film 17. When cross-sectional viewing the semiconductor substrate 10 in a plane surface orthogonal to a scribe line L between the two bonding parts 14a and 14a while passing through the adjacent two bonding parts 14a and 14a, the sum of widths D1 and D2 of the second insulation films 17 and 17 between the two bonding parts 14a and 14a and a second inter-electrode distance X obtained by a total sum of an interference D3 of the two second insulation films 17 and 17 satisfy the following equation: X>Vmax/(1.8×10V/cm) in a relationship of upper limit voltage Vmax of an inverse bias voltage applied to between the first electrode 15 and the bonding part 14a of the second electrode 14 in a breakdown voltage inspection executed to a semiconductor element region.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

  When a withstand voltage test is performed in a wafer state in a manufacturing process of a high withstand voltage semiconductor device, there is a problem that discharge occurs on the wafer surface.

  The discharge between the electrode in the semiconductor element region to be subjected to the withstand voltage test and the scribe line surrounding the semiconductor element region has been dealt with by providing an insulating film on the scribe line (for example, Patent Document 1) -3).

JP, 2009-267032, A JP, 2013-187438, A JP, 2013-191632, A

  By the way, as the upper limit value of the reverse bias voltage in the withstand voltage test rises, discharge occurs stochastically between the adjacent electrode and the scribe line rather than between the electrode and the scribe line to be subjected to the withstand voltage test. I found out that

  This problem arises because, in the withstand voltage test, as the reverse bias voltage value rises, the potential at the adjacent electrode is inevitably randomly fluctuated. For this reason, it is difficult to provide a reliable high withstand voltage semiconductor device.

  The present invention has been made in view of such problems, and an object thereof is to provide a semiconductor device for providing a highly reliable high withstand voltage semiconductor device and a method of manufacturing the same.

In a semiconductor device according to one aspect of the present invention, an ohmic junction is formed with a semiconductor substrate made of silicon carbide, a first insulating film formed on one main surface of the semiconductor substrate, and the other main surface of the semiconductor substrate. In each of a plurality of semiconductor element regions defined by scribing lines of the semiconductor substrate and the first electrode to be formed, the one main surface is formed in the exposed opening to form a Schottky junction with the semiconductor substrate In each of the semiconductor element region and the second electrode including the portion, the peripheral portion in contact with the first insulating film, and the semiconductor element region, when the semiconductor base is viewed in plan from the one main surface side, A second insulating film covering the first insulating film so as to expose the junction and exposing the first insulating film on the scribe line; When the semiconductor substrate is viewed in a cross section along a plane perpendicular to the scribe line between the two junctions passing through the junction, the width of the two second insulating films between the two junctions A second inter-electrode distance X given by the sum of the sum and the distance between the two second insulating films is the first electrode and the second electrode in a breakdown voltage test performed on the semiconductor element region. In the relationship with the upper limit value Vmax of the reverse bias voltage applied between the junction and the junction, X> Vmax / (1.8 × 10 ⁴ V / cm) is satisfied.

Further, a method of manufacturing a semiconductor device according to an aspect of the present invention includes the steps of preparing a semiconductor substrate made of silicon carbide, forming a semiconductor substrate, and forming a first insulating film on one main surface of the semiconductor substrate. A step of forming an insulating film, a step of forming a first electrode for forming an ohmic junction with the semiconductor substrate on the other main surface of the semiconductor substrate, and a scribe line of the semiconductor substrate In each of the semiconductor element region, an opening forming step of removing a part of the first insulating film to form an opening in which the one main surface is exposed in each of a plurality of semiconductor element regions; A second electrode forming step of forming in the opening a second electrode including a junction forming a semiconductor substrate and a Schottky junction and a peripheral edge contacting the first insulating film, and the semiconductor element region smell When the semiconductor substrate is viewed in plan from the one main surface side, the junction is exposed on the opening and the first insulating film is exposed on the scribe line. A second insulating film forming step of forming a second insulating film covering the first insulating film; and an upper limit between the first electrode and the junction of the second electrode with respect to the semiconductor element region. And a withstand voltage test step of applying a reverse bias voltage of a value Vmax to perform a withstand voltage test, and in the second insulating film forming step, passing the two adjacent joints adjacent to each other to form the second joint When the semiconductor substrate is viewed in cross section in a plane orthogonal to the scribe line, the sum of the widths of the two second insulating films between the two junctions and the second insulating film of the two second insulating films The second inter-electrode distance X given by the sum of the distance and The second insulating film is formed to satisfy X> Vmax / (1.8 × 10 ⁴ V / cm).

  According to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, the discharge generation rate between adjacent electrodes can be suppressed to 3% or less. Therefore, a highly reliable high breakdown voltage semiconductor device can be provided.

It is a top view showing composition of a semiconductor device concerning a first embodiment. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. It is a flowchart which shows the manufacturing method of the semiconductor device which concerns on 1st embodiment. FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment. It is a photograph of the state in which the discharge occurred between adjacent electrodes in the pressure | voltage resistant test process. FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device of the second embodiment. It is the graph which showed Examples 1-3 of this invention with the comparative example.

First Embodiment
Hereinafter, the first embodiment of the present invention will be described with reference to FIGS. 1 to 9.

(Structure of semiconductor device)
The semiconductor device according to the present embodiment is a semiconductor device provided with scribe lines for manufacturing a plurality of vertical Schottky barrier diode elements (semiconductor elements). The configuration of the semiconductor device according to the present embodiment will be described below with reference to FIGS. 1 and 2.

  In addition, this embodiment is concretely described in order to understand the meaning of invention better, and unless there is particular specification, it does not limit this invention. Further, in the drawings used in the following description, for the sake of easy understanding of the features of the present invention, the main parts may be enlarged for convenience, and the dimensional ratio of each component may be the same as the actual one. Not necessarily.

  As shown in FIG. 1, in the semiconductor device 1 according to the present embodiment, the first insulating film 11 is provided so as to cover a plurality of scribe lines L extending in the longitudinal direction and the lateral direction in plan view. The scribe line L is a line indicating a position at which the semiconductor device 1 is cut, and the first insulating film 11 is exposed on the scribe line L. The semiconductor device 1 is cut along the scribe line L using, for example, a diamond cutter. Thereby, a plurality of semiconductor devices (chips) are manufactured.

  In each of the plurality of semiconductor element regions defined by the scribe line L, the second insulating film 17 is annularly provided. The bonding portion 14 a which is a part of the second electrode 14 is exposed to the inside of the second insulating film 17.

  2 crosses the two junctions 14a and 14a adjacent to each other and crosses the scribe line L between the two junctions 14a and 14a in the region surrounded by the broken line in FIG. It is sectional drawing (AA arrow sectional drawing) which carried out the cross sectional view by the plane. As shown in FIG. 2, the semiconductor device 1 includes a semiconductor base 10, a first insulating film 11, a first electrode 15, a second electrode 14, and a second insulating film 17. The semiconductor device 1 further includes a guard ring region 12 and a third insulating film 16.

The semiconductor substrate 10 is made of silicon carbide (SiC). The semiconductor substrate 10 includes a semiconductor substrate 10 a made of n ⁺ -type silicon carbide containing a high concentration of impurities, and a drift layer 10 b made of n ⁻ -type silicon carbide containing a low concentration of impurities.

As the semiconductor substrate 10a made of n ⁺ -type silicon carbide, one having an n-type impurity concentration of 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ⁻³ and a thickness of 30 μm to 400 μm can be used. As the crystal polymorphism of n ⁺ -type silicon carbide, for example, 4H can be used. As the drift layer 10 b, one having an n-type impurity concentration of 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ and a thickness of ³ μm to 20 μm can be used. Drift layer 10 b constitutes one main surface F 1 of semiconductor substrate 10. The semiconductor substrate 10 a constitutes the other main surface F 2 of the semiconductor substrate 10.

  The first insulating film 11 is formed on one main surface F1 of the semiconductor substrate 10 so as to cover the scribe line L. The first insulating film 11 is formed of phosphorous glass (PSG). The material forming the first insulating film is not limited to PSG. For example, a thermal oxide film / PSG laminated film in which a thermal oxide film is added to the base may be used.

  The first electrode 15 is formed on the other main surface F2 of the semiconductor substrate 10. The first electrode 15 forms an ohmic junction with the other main surface F2. The first electrode 15 is formed of, for example, nickel (Ni).

  As will be described later, a portion of the one main surface F1 of the semiconductor substrate 10 which is not covered by the first insulating film 11 is an opening 13 where the one main surface F1 is exposed. The opening 13 exists in each of the plurality of semiconductor element regions defined by the scribe line L. That is, the plurality of openings 13 are formed in the first insulating film 11.

  The second electrode 14 is formed to cover the opening 13 in each of the plurality of semiconductor element regions defined by the scribe line L. The second electrode 14 includes a bonding portion 14 a and a peripheral portion 14 b. The second electrode 14 forms a Schottky junction with the semiconductor substrate 10. The second electrode 14 is formed of, for example, titanium (Ti).

  The bonding portion 14 a is formed in the opening 13. On one main surface F1 of the semiconductor substrate 10, a Schottky junction is formed at the junction 14a of the second electrode 14. As described above, on the other main surface F2 of the semiconductor substrate 10, an ohmic junction is formed in the first electrode 15. Therefore, each of the plurality of semiconductor element regions defined by the scribe line L functions as a Schottky barrier diode.

  The peripheral portion 14 b is located around the bonding portion 14 a and is in contact with the first insulating film 11. The peripheral portion 14 b is formed in an annular shape so as to cover the edge of the first insulating film 11 in plan view.

  When the semiconductor substrate 10 is viewed in plan, a guard ring region 12 made of a p-type semiconductor is annularly formed in a region of the drift layer 10b located outside the junction 14a. The guard ring region 12 contains, for example, aluminum (Al) or boron (B) as an impurity. The inner edge portion of the guard ring area 12 is in contact with the joint portion 14 a in a plan view. The outer edge portion of the guard ring region 12 is in contact with the first insulating film 11 in plan view.

The guard ring region 12 includes a high concentration guard ring region 12 a and a low concentration guard ring region 12 b. The high concentration guard ring area 12 a is annularly provided on the inner side when the guard ring area 12 is viewed in plan. The high concentration guard ring region 12 a is a layer having a relatively high impurity concentration (p type impurity concentration is 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ ). The high concentration guard ring region 12 a is provided to overlap the peripheral portion 14 b in plan view. In the illustrated example, a part of the high concentration guard ring region 12a is covered with the first insulating film 11, but the invention is not limited thereto. The low density guard ring region 12 b is annularly provided outside the guard ring region 12 in plan view. The low concentration guard ring region 12 b is a layer having a relatively low impurity concentration (p type impurity concentration is 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ ). The low concentration guard ring region 12 b is covered with the second insulating film 17 in plan view.

  The third insulating film 16 is annularly provided on the first insulating film 11 in plan view. The third insulating film 16 is formed on the first insulating film 11 so as to surround the peripheral portion 14 b of the second electrode 14. The third insulating film 16 is formed of, for example, silicon nitride (SiN).

  The second insulating film 17 is annularly provided in plan view so as to cover the outer peripheral portion of the bonding portion 14 a of the second electrode 14 and the peripheral portion of the opening 13 of the first insulating film 11. The second insulating film 17 is provided to cover the entire peripheral portion 14 b and the entire third insulating film 16. The second insulating film 17 is formed of, for example, polyimide.

  As shown in FIG. 2, when the semiconductor substrate 10 is viewed in a cross section in a plane perpendicular to the scribe line L passing through the two adjacent joints 14 a and 14 a and being adjacent to each other, The sum of the widths D1 and D2 of the two second insulating films 17 and 17 between the bonding portions 14a and 14a and the distance D3 of the two second insulating films 17 and 17 is the distance between the second electrodes X Define as In the breakdown voltage test performed on the semiconductor element region, the upper limit value of the reverse bias voltage applied between the first electrode 15 and the bonding portion 14 a of the second electrode 14 is set to Vmax.

The second insulating film 17 is provided so that the second inter-electrode distance X satisfies X> Vmax / (1.8 × 10 ⁴ V / cm) in relation to Vmax. Thereby, in the pressure | voltage resistant test, the discharge generation rate between adjacent electrodes can be suppressed. Therefore, a highly reliable high breakdown voltage semiconductor device can be provided.

It is desirable that the second insulating film 17 be provided so that the second inter-electrode distance X satisfies X> Vmax / (1.5 × 10 ⁴ V / cm) in relation to Vmax. Thereby, in the pressure | voltage resistant test, the discharge generation rate between adjacent electrodes can further be suppressed. Therefore, a highly reliable high breakdown voltage semiconductor device can be provided.

(Method of manufacturing semiconductor device)
Hereinafter, with reference to FIGS. 3 to 8, a method of manufacturing a semiconductor device according to the present embodiment will be described.

  As shown in FIG. 3, in the method of manufacturing a semiconductor device according to the present embodiment, a semiconductor base preparation step S1, a first insulating film formation step S3, a first electrode formation step S5, and an opening formation step S6. A second electrode forming step S7, a second insulating film forming step S8, and a withstand voltage inspection step S9 are included. The method for manufacturing a semiconductor device according to the present embodiment further includes an impurity ion implantation step S2 and a third insulating film formation step S4.

  Hereinafter, each step of the method of manufacturing a semiconductor device according to the present embodiment will be described using FIGS. 4 to 8. 4 to 7 show cross-sectional views in one semiconductor element region.

(S1: semiconductor substrate preparation process)
First, a semiconductor substrate preparation step S1 shown in FIG. 4A is performed. In the semiconductor substrate preparation step S1, an n ^-- type silicon carbide epitaxial layer (drift) is formed on the upper surface of an n ⁺ -type silicon carbide single crystal substrate (semiconductor substrate) 10a (thickness: 350 μm, impurity concentration: 1 × 10 ¹⁹ cm ^-3 ). The semiconductor substrate 10 is prepared by forming a layer 10b (thickness: 13.5 μm, impurity concentration: 5 × 10 ¹⁵ cm ⁻³ ) by chemical vapor deposition (CVD).

(S2: Impurity ion implantation process)
Next, an impurity ion implantation step S2 shown in FIG. 4 (b) is performed. In the impurity ion implantation step S2, first, one main surface F1 of the semiconductor substrate 10 is cleaned. Next, an oxide film is formed on one main surface F1, and a resist is applied on the oxide film by spin coating. Thereafter, a mask (not shown) having an opening at a portion corresponding to the high concentration guard ring region 12a or the low concentration guard ring region 12b is formed by photolithography. In this state, p-type impurity ions (for example, aluminum ions) of a conductivity type reverse to that of the semiconductor substrate 10 are introduced into one main surface F1 of the semiconductor substrate 10 using ion implantation. After ion implantation, the mask is removed. Thereby, a guard ring region 12 including the high concentration guard ring region 12 a and the low concentration guard ring region 12 b is formed. In the impurity ion implantation step S2, the high concentration guard ring region 12a and the low concentration guard ring region 12b may be formed separately, for example. Thereafter, the impurities are electrically activated by heating at a high temperature of 1500 ° C. or more.

(S3: First insulating film forming process)
Next, a first insulating film forming step S3 shown in FIG. 5A is performed. In the first insulating film forming step S3, first, phosphorus glass (PSG) is laminated on one main surface F1 of the semiconductor substrate 10 by chemical vapor deposition (CVD) to form the insulating film layer 110. After the insulating film layer 110 is formed, heat treatment is performed. When the first insulating film is a thermal oxide film / PSG laminated film, the semiconductor substrate 10 is thermally oxidized in an atmosphere of 1000 ° C. or higher in oxygen gas, and then phosphorus glass (PSG) is formed by chemical vapor deposition (CVD). And the insulating film layer 110 can be formed. Additional heat treatment may be performed in an atmosphere of 700 ° C. or higher as baking treatment of phosphorus glass (PSG).

(S4: Third insulating film forming step)
Next, a third insulating film forming step S4 shown in FIG. 5 (b) is performed. In the third insulating film forming step S4, first, silicon nitride (SiN) is stacked on the surface of the first insulating film 11 by chemical vapor deposition (CVD). The resist is then applied by spin coating. Next, a mask (not shown) having an opening at a portion corresponding to the third insulating film 16 is formed by photolithography. Thereafter, silicon nitride (SiN) in the opening is removed by dry etching or the like.

(S5: first electrode forming step)
Next, the first electrode forming step S5 shown in FIG. 6A is performed. In the first electrode formation step S5, first, a metal (for example, nickel (Ni)) is sputtered on the other main surface F2 of the semiconductor substrate 10 to form a metal film. Thereafter, the metal and silicon carbide are alloyed by heat treatment to form the first electrode 15.

(S6: Opening formation process)
Next, an opening forming step S6 shown in FIG. 6 (b) is performed. In the opening forming step S6, first, a resist is applied to the surface of the insulating film layer 110 by spin coating. Then, a mask (not shown) having an opening at a portion corresponding to the opening 13 is formed by photolithography. The opening 13 is provided such that the peripheral edge thereof overlaps the high concentration guard ring area 12 a in a plan view. After the mask formation, the insulating film layer 110 is etched using buffered hydrofluoric acid to expose one main surface F1 of the semiconductor substrate 10. Thus, the opening 13 and the first insulating film 11 are formed. After the formation of the opening 13 and the first insulating film 11, the resist is removed.

(S7: second electrode forming step)
Next, a second electrode forming step S6 shown in FIG. 7A is performed. In the second electrode formation step S6, first, a metal such as titanium (Ti) is sputtered or vapor-deposited on the main surface F1 to form a metal film. The resist is applied by spin coating. Then, the second electrode 14 is formed by photolithography and etching. Thereafter, the metal and silicon carbide are alloyed by heat treatment to complete the second electrode 14.

(S8: second insulating film forming step)
Next, a second insulating film forming step S8 shown in FIG. 7B is performed. In the second insulating film formation step S8, first, polyimide is applied to the surfaces of the second electrode 14 and the first insulating film 11 by spin coating. The second insulating film 17 is formed by photolithography. Thereby, the semiconductor device 1 is formed.

(S9: pressure resistance inspection process)
Finally, a withstand voltage inspection step S9 shown in FIG. 8 is performed. In the withstand voltage inspection step S9, first, the semiconductor device 1 is mounted on the wafer prober stage PS. In the semiconductor device 1, one of the plurality of semiconductor element regions defined by the scribe line L is selected to be an inspection region AT. The tip of the probe PR is brought into contact with the joint 14a of the inspection area AT. A reverse bias voltage V is applied between the wafer prober stage PS and the probe PR to perform a withstand voltage test on the inspection area AT.

  When the reverse bias voltage V becomes high, it is inevitable that the potential at the junction 14a of another semiconductor element region (adjacent region AN) adjacent to the inspection region AT is incidentally randomly fluctuated. Thus, as the upper limit value Vmax of the reverse bias voltage V in the withstand voltage inspection step S9 increases, as shown by the thick arrow in FIG. 8, between the two adjacent junctions 14 a and 14 a beyond the scribe line L. Discharge occurs stochastically. FIG. 9 is a photograph showing the moment when a discharge occurs between the inspection area AT and the adjacent area AN.

In the second insulating film forming step S8, the second insulating film 17 passes through two adjacent bonding portions 14a, 14a adjacent to each other, and is a semiconductor substrate in a plane orthogonal to the scribe line L between the two bonding portions 14a, 14a. 10 when viewed in cross section, the sum of the widths D1 and D2 of the two second insulating films 17 and 17 between the two junctions 14a and 14a, and the distance D3 between the two second insulating films 17 and 17 and A second inter-electrode distance X given by the sum of the above, is provided so as to satisfy X> Vmax / (1.8 × 10 ⁴ V / cm) in relation to Vmax. As a result, in the withstand voltage inspection step S9, it is possible to suppress the rate of discharge between the two adjacent bonding portions 14a and 14a. Therefore, a highly reliable high breakdown voltage semiconductor device can be provided.

In the second insulating film forming step S8, the second insulating film 17 is provided such that the distance X between the second electrodes satisfies X> Vmax / (1.5 × 10 ⁴ V / cm) in relation to Vmax. Is desirable. As a result, in the breakdown voltage inspection step S9, it is possible to further suppress the discharge generation rate between the two adjacent bonding portions 14a and 14a. Therefore, a highly reliable high breakdown voltage semiconductor device can be provided.

Second Embodiment
Hereinafter, a second embodiment of the present invention will be described mainly with reference to FIG. The parts common to the first embodiment will not be described.

(Structure of semiconductor device)
The semiconductor device of this embodiment is configured in the same manner as the first embodiment, except that the first insulating film 11 is formed of silicon dioxide (SiO ₂ ) (see FIG. 2). The semiconductor device of this embodiment exhibits the same effect as that of the first embodiment.

(Method of manufacturing semiconductor device)
The semiconductor device manufacturing method according to the present embodiment includes the same semiconductor substrate preparation step S1, the first insulating film formation step S3, the first electrode formation step S5, and the opening formation step S6 as in the first embodiment. A second electrode forming step S7, a second insulating film forming step S8, and a withstand voltage inspection step S9 are included. Further, the method of manufacturing a semiconductor device according to the present embodiment further includes an impurity ion implantation step S2 and a third insulating film formation step S4.

However, in the present embodiment, as shown in FIG. 10, in the first insulating film formation step S3 (see FIG. 3), one main surface F1 of the semiconductor substrate 10 is thermally oxidized in an oxygen atmosphere. , growing the insulating film layer 111 made of silicon dioxide (SiO _2).

  In the opening step S6 (see FIG. 3), a resist is applied by spin coating. A mask (not shown) having an opening at a portion corresponding to the opening 13 is formed by photolithography. After the mask formation, the insulating film layer 111 is etched using buffered hydrofluoric acid to expose one main surface F1 of the semiconductor substrate 10. Thus, the opening 13 and the first insulating film 11 are formed (see FIG. 6B).

  The method of manufacturing a semiconductor device according to this embodiment has the same effect as that of the first embodiment.

  As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form. For example, although the second insulating film 17 is formed of polyimide, other insulating materials can also be used. Further, although the first insulating film 11 is formed of phosphorus glass or silicon dioxide, other insulating materials can also be used. Further, although the guard ring region 12 is provided in the semiconductor substrate 10, the guard ring region 12 can be omitted. Besides, various design changes can be made within the scope of the matters described in the claims.

[Example]
Hereinafter, examples of the present invention will be shown.

The semiconductor devices used in Examples 1 to 3 and the comparative example are obtained by changing the distance X between the electrodes in the structure (see FIG. 2) of the semiconductor device shown in the first embodiment described above. The inter-electrode distance X is as follows.
Example 1 X = 1310 μm (Vmax / X ≒ 1.3 × 10 ⁴ V / cm)
Example 2 X = 1110 μm (Vmax / X ≒ 1.5 × 10 ⁴ V / cm)
Example 3 X = 943 μm (Vmax / X ≒ 1.8 × 10 ⁴ V / cm)
(Comparative example) X = 776 μm (Vmax / X 2.2 2.2 × 10 ⁴ V / cm)

  With respect to each of these semiconductor devices, a square wave having a maximum voltage value of about Vmax = 1700 V and a pulse width of 50 ms, which is the withstand voltage inspection step S9 (see FIGS. 3 and 8) in the method of manufacturing the semiconductor device Was applied.

  The results are shown in the graph of FIG. The first horizontal axis on the lower side of the graph is X [μm], and the vertical axis is the discharge rate [%] between adjacent electrodes. The upper second horizontal axis of the graph indicates the value of Vmax / X [V / cm] corresponding to X of the first horizontal axis.

  According to the results shown in FIG. 11, the discharge rate is about 3% in Example 1, and the discharge rate is almost 0% in Examples 2 and 3 compared to the discharge rate of the comparative example was about 28%. Met. That is, according to the semiconductor device and the semiconductor device manufacturing method of the embodiment of the present invention, it has been confirmed that the discharge generation rate between adjacent electrodes can be suppressed to about 3% or less.

DESCRIPTION OF SYMBOLS 1 semiconductor device 10 semiconductor base 11 first insulating film 12 guard ring region 13 opening 14a junction 14b peripheral edge 14 second electrode 15 first electrode 17 second insulating film L scribing Line F1: One main surface F2: Other main surface S1: Semiconductor substrate preparation process S2: Impurity ion implantation process S3: First insulating film formation process S5: First electrode formation process S6: Opening formation process S7: Second Electrode formation process S8 ... second insulating film formation process S9 ... breakdown voltage inspection process

Claims (7)

A semiconductor substrate made of silicon carbide,
A first insulating film formed on one of the main surfaces of the semiconductor substrate;
A first electrode that forms an ohmic junction with the other main surface of the semiconductor substrate;
In each of a plurality of semiconductor element regions defined by scribe lines of the semiconductor substrate, the first main surface is formed in an exposed opening, and a junction forming a Schottky junction with the semiconductor substrate; A second electrode including a peripheral portion in contact with the insulating film;
In each of the semiconductor element regions, when the semiconductor substrate is viewed in plan from the one main surface side, the junction is exposed on the opening and the first insulating film on the scribe line A second insulating film covering the first insulating film such that
Including
When the semiconductor substrate is viewed in a cross section in a plane perpendicular to the scribe line between the two adjacent junctions passing through the two adjacent junctions, two of the second junctions between the two junctions A second inter-electrode distance X given by the sum of the width of two insulating films and the distance between the two second insulating films is the first electrode and the first electrode in a breakdown voltage test performed on the semiconductor element region In the relationship with the upper limit value Vmax of the reverse bias voltage applied between the second electrode and the junction, X> Vmax / (1.8 × 10 ⁴ V / cm) is satisfied.
Semiconductor device. The second inter-electrode distance X satisfies X> Vmax / (1.5 × 10 ⁴ V / cm) in relation to the upper limit value Vmax of the reverse bias voltage.
The semiconductor device according to claim 1. The second insulating film is formed of polyimide,
The semiconductor device according to claim 1. The first insulating film is formed of phosphorus glass or silicon dioxide
The semiconductor device according to any one of claims 1 to 3. A guard ring region is provided on the semiconductor substrate,
The semiconductor device according to any one of claims 1 to 4. A semiconductor substrate preparation step of preparing a semiconductor substrate made of silicon carbide;
A first insulating film forming step of forming a first insulating film on one main surface of the semiconductor substrate;
A first electrode forming step of forming a first electrode forming an ohmic junction with the semiconductor substrate on the other main surface of the semiconductor substrate;
An opening forming step of removing a part of the first insulating film to form an opening in which the one main surface is exposed in each of a plurality of semiconductor element regions defined by scribe lines of the semiconductor substrate; ,
In each of the semiconductor element regions, a second electrode is formed in the opening, and a second electrode including a bonding portion forming a Schottky junction with the semiconductor substrate and a peripheral portion in contact with the first insulating film. Process,
In each of the semiconductor element regions, when the semiconductor substrate is viewed in plan from the one main surface side, the junction is exposed on the opening and the first insulating film on the scribe line Forming a second insulating film covering the first insulating film so as to expose the second insulating film;
A withstand voltage inspection step of applying a reverse bias voltage of upper limit value Vmax between the first electrode and the junction of the second electrode to the semiconductor element region to perform a withstand voltage inspection;
Including
In the step of forming the second insulating film, when the semiconductor substrate is viewed in a cross section in a plane perpendicular to the scribe line between the two adjacent bonding portions passing through the adjacent two bonding portions, The second inter-electrode distance X given by the sum of the widths of the two second insulating films between junctions and the distance between the two second insulating films is X> Vmax / (1.8 × 10 Forming the second insulating film so as to satisfy ⁴ V / cm),
Semiconductor device manufacturing method. Between the semiconductor substrate preparation step and the first insulating film formation step, an impurity ion implantation step of implanting impurity ions of the opposite conductivity type to the semiconductor substrate to one main surface of the semiconductor substrate is further performed. Including
A method of manufacturing a semiconductor device according to claim 6.