JP6163922B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device having a trench structure in which a groove (trench) is provided in a drift region, and a manufacturing method thereof.

  Conventionally, a trench type diode in which a rectifying junction is formed after providing a groove in a drift region of a semiconductor substrate is known. The trench diode can obtain a higher breakdown voltage and a lower reverse current than a planar diode having a rectifying junction parallel to the surface of the semiconductor substrate. If the reverse characteristics are similar, the trench diode can obtain a lower forward voltage than the planar diode.

  As a prior art of such a trench type diode, for example, a diode described in Patent Document 1 is known. According to this prior art, a groove is provided in a first conductive type semiconductor substrate, and a second conductive type layer provided at the bottom of the groove is formed so as to spread on both sides of the groove. A cathode electrode is formed on the substrate.

JP 2007-128926 A

  However, according to the above prior art, since the electric field relaxation region of the second conductivity type is provided in the entire groove bottom portion, when a forward voltage is applied, a potential barrier due to a PN junction is added to the groove bottom region. The rising voltage of the forward current increases. Further, when a forward current flows through the semiconductor region (cathode region) between the trenches, a potential barrier due to the PN junction between the second conductivity type layer and the semiconductor substrate affects both sides of the cathode region. Therefore, according to the prior art, there is a problem that the rising voltage of the forward current becomes high as a diode. This problem becomes more serious in the case of SiC having a wide band gap because the potential barrier of the PN junction is much higher than that of Si.

  In order to solve the above problems, the present invention is formed in one end portion of the drift region of the first conductivity type, a groove formed in the surface of the drift region, and the bottom surface of the groove, and in the other end portion. And a second conductivity type electric field relaxation region that is not formed. The drift region is formed only on one side surface of the convex portion sandwiched between the two grooves, the first electrode is formed so as to cover the groove, and the second electrode is formed on the back surface of the semiconductor substrate. ing.

  According to the present invention, the electric field relaxation region of the second conductivity type is formed at one end portion of the bottom surface of the groove and is not formed at the other end portion. For this reason, when a reverse voltage is applied, a high reverse withstand voltage and a small reverse leakage current can be maintained at the same level as the conventional one by the depletion layer extending from the electric field relaxation region formed at one end. In addition, when a forward voltage is applied, a region that is not blocked by the depletion layer extending from the electric field relaxation region is expanded, so that a semiconductor device in which the rising voltage of the forward current is reduced can be provided.

It is sectional drawing explaining 1st Embodiment of the semiconductor device which concerns on this invention. FIG. 6 is a cross-sectional view in order of the steps, illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view in order of the steps, illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view in order of the steps, illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is sectional drawing explaining the difference in the characteristic of a conventional example and the semiconductor device of 1st Embodiment. FIG. 6 is a cross-sectional view in order of the steps for explaining a modification of the semiconductor device manufacturing method according to the first embodiment. It is process order sectional drawing explaining the manufacturing method of the semiconductor device in 2nd Embodiment. It is process order sectional drawing explaining the manufacturing method of the semiconductor device in 2nd Embodiment. It is sectional drawing explaining the characteristic of the semiconductor device of 2nd Embodiment. It is process order sectional drawing explaining the manufacturing method of the semiconductor device in 3rd Embodiment. It is process order sectional drawing explaining the manufacturing method of the semiconductor device in 3rd Embodiment. It is sectional drawing explaining the characteristic of the semiconductor device of 3rd Embodiment. FIG. 6A is a plan view and FIG. 5B is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment. It is (a) top view and (b) sectional view explaining the characteristic of the semiconductor device of a 4th embodiment. 8A is a plan view of a semiconductor device according to a fifth embodiment, and FIG. It is (a) top view and (b) sectional view explaining the characteristic of the semiconductor device of a 5th embodiment.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the first conductivity type is N-type, the second conductivity type is P-type, the first electrode is an anode electrode, and the second electrode is a cathode electrode. However, it is clear that the present invention can be realized even if the first conductivity type is changed to the P type and the second conductivity type is changed to the N type by exchanging the N type and the P type.

<First Embodiment>
[Description of Structure of Semiconductor Device]
FIG. 1 is a cross-sectional view illustrating the structure of a first embodiment of a semiconductor device according to the present invention. In FIG. 1, an N − type drift region 3 made of an N type low concentration N− type silicon carbide epitaxial layer is formed on the surface of a first conductivity type N type high concentration N + type silicon carbide substrate 1. Yes. Here, the + and − symbols indicate the high and low concentrations of the introduced impurity. A plurality of grooves 5 having a pair of side surfaces and a bottom surface are formed in parallel on the surface of the N − -type drift region 3. A second conductivity type P-type electric field relaxation region 7 is formed at one end of a side surface 5a of the groove 5 and a bottom surface 5b connected to the side surface 5a.

  An anode electrode 9 that is a first electrode is formed so as to cover the groove 5, in other words, to fill the groove 5 and connect between the adjacent grooves 5. For the anode electrode 9, it is desirable to use a material obtained by adding a P-type impurity to polycrystalline silicon that forms a heterojunction with the N − type drift region 3 or a metal material that forms a Schottky junction with the N − type drift region 3. . In the former case, the semiconductor device is a heterojunction diode, and polycrystalline silicon is a material having a band gap different from that of silicon carbide constituting the N − type drift region 3. In the latter case, the semiconductor device becomes a Schottky junction diode, and can also be called a unipolar diode. On the back surface of the N + type silicon carbide substrate 1, a cathode electrode 11 as a second electrode is formed using a metal material that forms an ohmic junction with the N + type silicon carbide substrate 1.

[Description of manufacturing method]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to cross-sectional views in order of the processes in FIGS. First, as shown in FIG. 2A, a semiconductor substrate in which an N − type drift region 3 made of an N − type silicon carbide epitaxial layer is formed on an N + type silicon carbide substrate 1 is prepared. For this purpose, an epitaxial layer may be grown on the surface of the N + type silicon carbide substrate 1 to form the N− type drift region 3, or a silicon carbide substrate having a commercially available epitaxial layer may be used.

  Next, in the step shown in FIG. 2B, the P-type region 15 is formed by performing ion implantation 101 of P-type impurities in the N − -type drift region 3 using the oxide film mask 13. In order to form the oxide film mask 13, an Si oxide film is formed on the entire surface of the N − type drift region 3, and the formed oxide film is patterned by a general photolithography method to form the oxide film mask 13. To do. At this time, etching is performed using a patterned resist as a mask for a Si oxide film as a base material of the oxide film mask 13. As an etching method, wet etching using hydrofluoric acid or dry etching such as reactive ion etching can be used. Next, the resist is removed with oxygen plasma or sulfuric acid. Aluminum (Al) or boron (B) can be used as the P-type impurity. At this time, by performing ion implantation while the temperature of the semiconductor substrate is heated to about 600 ° C., occurrence of crystal defects in the implanted region can be suppressed.

  Next, in FIG. 2C, a pattern in which only the groove forming portion is opened with a resist 17 is formed on the oxide film mask 13, and the oxide film mask 13 in the groove forming portion is etched to open.

  Next, in FIG. 3A, after the resist 17 is removed, an oxide film 19 serving as a base material for the sidewall is formed on the entire surface. Next, in FIG. 3B, the whole is dry-etched to form a sidewall 21 at the end of the oxide film opening in the groove forming portion, and the end of the oxide film opening in the groove forming portion is the P-type region 15. Overlap within the range.

  Next, in FIG. 3C, the groove 5 is formed by dry etching the exposed portions of the N − -type drift region 3 and the P-type region 15 using the oxide film mask 13 and the sidewall 21 as a mask. At this time, etching is not performed deeper than the lowermost portion of the P-type region 15. By this dry etching, the P-type electric field relaxation region 7 is formed so as to cover one side surface 5a of the groove 5 and the corner of the end portion of the bottom surface 5b connected to the side surface.

  Next, in FIG. 4A, the anode electrode 9 is formed so as to cover the groove 5, in other words, to fill the groove 5 and connect between the adjacent grooves 5. The material of the anode electrode 9 at this time is preferably a material obtained by adding a P-type impurity to polycrystalline silicon that forms a heterojunction with the N − type drift region 3 or a metal material that forms a Schottky junction with the N − type drift region 3. .

  When the material for forming the anode electrode 9 is a metal material that forms a Schottky junction with the N − type drift region 3, the anode electrode 9 can be formed by a vacuum deposition method.

  A material that forms a Schottky junction with N − type drift region 3 is a metal material having a work function larger than the electron affinity of N − type silicon carbide that is the material of N − type drift region 3. For example, the electron affinity of the material of the N − type drift region 3 is 3.6 [eV]. As a metal material meeting this condition, aluminum (work function: 4.4 [eV]), gold (5.2 [eV]), tungsten (4.4 [eV]), platinum (5.3 [eV]) ) Etc. can be used.

  When the material for forming the anode electrode 9 is polycrystalline silicon that forms a heterojunction with the N − type drift region 3, the polycrystalline silicon is deposited, and P-type impurities are ion-implanted into the polycrystalline silicon.

  Next, in FIG. 4B, the cathode electrode 11 is formed on the back surface of the N + type silicon carbide substrate 1. In order to form cathode electrode 11, a metal such as Ti or Ni that is in ohmic contact with N + -type silicon carbide is annealed on the back surface of N + -type silicon carbide substrate 1 after vacuum deposition.

[Description of operation]
Next, a difference in operation between the semiconductor device of the present embodiment shown in FIG. 1 and the semiconductor device according to the prior art (Japanese Patent Laid-Open No. 2007-128926) will be described with reference to FIG. The spread of the depletion layer in FIG. 5 illustrates a calculation result by the device simulation apparatus T-CAD of SYNOPSYS.

[Conventional reverse voltage characteristics]
As shown in FIG. 5A, in the prior art, the P-type electric field relaxation region 107 is formed over the entire groove bottom portion to cover the both ends of the groove bottom. When a reverse voltage is applied to the anode electrode 9 with respect to the cathode electrode 11 as a reference, the barrier current between the semiconductor and the anode electrode 9 prevents the electrons on the anode electrode side from moving to the semiconductor side. Not flowing. However, reverse leakage current flows from the cathode electrode 11 to the anode electrode 9 from the location where the electric field concentration occurs. In the case of a trench structure diode, the electric field concentrates at the end of the trench and reverse leakage current flows. When a reverse voltage is applied in the structure of the prior art, the depletion layer 191 extends from the anode electrode 9, the depletion layer 123 extends from the P-type electric field relaxation region 107, and the entire anode electrode 9 is covered with the depletion layer. By this operation, reverse leakage current from the end of the groove is suppressed.

[Conventional forward voltage characteristics]
As shown in FIG. 5B, when a forward voltage is applied to the anode electrode 9 with the cathode electrode 11 as a reference, electrons on the semiconductor side move to the anode electrode 9 side, and the cathode from the anode electrode 9 moves to the cathode. A forward current flows to the electrode 11. At this time, since the entire bottom of the groove is a PN junction, the forward voltage flowing through the bottom of the groove has a very high rising voltage due to the potential barrier of the PN junction. Further, the depletion layer 125 due to the PN junction remains in the P-type electric field relaxation region 107, and the path of the forward current 129 flowing between the grooves is narrowed from both sides. Narrow.

[Reverse Voltage Characteristics of this Embodiment]
As shown in FIG. 5C, in the structure of the semiconductor device of the present embodiment, a P-type electric field relaxation region 7 is provided at one end of the groove. For this reason, when a reverse voltage is applied, the depletion layer 23 extends from the P-type electric field relaxation region 7 and the electric field at the groove end is relaxed. Since P-type electric field relaxation region 7 is disposed along one side surface of the groove, the other side surface of the groove where no electric field relaxation region is provided and the groove end are covered with a depletion layer from P-type electric field relaxation region 7. Can do. Because of this operation, the value of the reverse leakage current in the present embodiment can be lowered to the same level as the structure of the prior art.

[Forward voltage characteristics of this embodiment]
As shown in FIG. 5D, in this embodiment, since the P-type electric field relaxation region 7 is provided only on one side surface of the groove, the forward direction is increased by the potential barrier of the PN junction as compared with the prior art. The area of the region where the current rising voltage becomes very high becomes very small. In addition, a depletion layer 25 caused by the potential of the PN junction remains around the P-type electric field relaxation region 7 installed at one end of the groove 5, which prevents forward current. However, forward currents 27 and 29 can flow in the region excluding one end of the bottom of the groove and around the other end where the P-type electric field relaxation region 7 is not provided, without being disturbed by the depletion layer. . Because of this operation, the rising voltage of the forward current in this embodiment can be made lower than that in the prior art.

[Effect of this embodiment]
According to the present embodiment described above, the P-type electric field relaxation region 7 is installed at the end of one side surface 5a of the groove 5 and the bottom surface 5b connected to the side surface 5a, and the protrusion sandwiched between the adjacent grooves 5 is provided. The P-type electric field relaxation region 7 is installed only on one side surface of the part. Thereby, when a reverse voltage is applied, the electric field concentrated on both ends of the groove can be relaxed by the depletion layer 23 extending from the P-type electric field relaxation region 7. Further, when a forward voltage is applied, a current path is secured around the other end of the groove where the P-type electric field relaxation region 7 is not provided, so that the rising voltage of the forward current can be reduced. With this effect, it is possible to obtain a large forward current with the same forward voltage while ensuring reverse voltage characteristics equivalent to those of the prior art. Further, the rising voltage of the forward current can be lowered as compared with the prior art.

  Further, according to the present embodiment, the P-type electric field relaxation region 7 is installed at a position deeper than the bottom of the groove 5, so that when the reverse voltage is applied, the end and bottom of the groove are also at the P-type electric field relaxation region 7. The electric field can be relaxed by a depletion layer from

  Further, according to the present embodiment, in the adjacently arranged grooves 5, the P-type electric field relaxation region 7 is formed only at the end on the same side of all the grooves 5. Thereby, only by forming the P-type electric field relaxation region 7 at one end portion of one groove 5, the electric field relaxation at the other groove end portion where the P-type electric field relaxation region 7 of the adjacent groove 5 is not provided is also obtained. be able to.

  In addition, according to the present embodiment, after forming the P type region of silicon carbide serving as the base material of the electric field relaxation region, the sidewall 21 is formed on the oxide film mask 13 and the end of the sidewall 21 is the P type region of silicon carbide. It was formed to hang inside. Therefore, by the process of forming the groove 5 by dry etching using the oxide film mask 13 and the sidewall 21 as a mask, the P-type electric field relaxation region is formed on one side surface of the groove 5 and the end of the bottom surface connected thereto by self-alignment 7 can be formed.

[Modification of First Embodiment]
Next, a modification of the method for manufacturing the semiconductor device of the present embodiment will be described with reference to the sectional views in the order of steps in FIG. The structure of the semiconductor device of this modification is almost the same as that of FIG. 1, but the method for forming the P-type electric field relaxation region is different.

  First, as shown in FIG. 6A, a groove 5 is formed by dry etching using an oxide film mask 13 on a semiconductor substrate in which an N− type drift region 3 of silicon carbide is formed on an N + type silicon carbide substrate 1. Form.

  Next, as shown in FIG. 6B, P-type impurities are ion-implanted from one side of the groove 5 into the groove 5 and the bottom end of the groove connected to the side surface from an oblique direction. A P-type electric field relaxation region 31 is formed. The angle in the oblique direction for ion implantation is an angle at which the ions 105 are irradiated so as to hit one side surface of the groove 5 and the bottom end portion of the groove connected to the side surface. Thereafter, an anode electrode and a cathode electrode (not shown) are formed by the same method as in the first embodiment.

  With the manufacturing method of this modification, the P-type electric field relaxation region 31 can be formed on one side surface of the groove and the bottom surface end portion of the groove connected to the side surface with a small number of steps.

Second Embodiment
[Description of Structure of Semiconductor Device]
Next, the structure of the second embodiment of the semiconductor device according to the present invention will be described with reference to FIG. In the present embodiment, the shape of the groove 39 is a tapered shape that widens upward and becomes narrower toward the bottom surface 39a of the groove. Then, the P-type electric field relaxation region on the side surface of the groove is removed, and the P-type electric field relaxation region 43 is provided only at one end of the bottom surface 39a of the groove 39.

[Description of manufacturing method]
Next, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. First, in FIG. 7A, a groove 33 is formed in the N − type drift region 3 of silicon carbide by the same method as in the first embodiment. The state of FIG. 7A is a state in which the oxide film mask 13 and the sidewalls 21 are removed from the state of FIG. 3C of the first embodiment. The groove 33 is provided with the P-type electric field relaxation region 7 only on one side surface of the groove and the end portion of the bottom surface of the groove connected to the side surface.

  Next, in FIG. 7B, the surface of the N − type drift region 3 in which the groove 33 is formed is thermally oxidized at about 900 to 1300 ° C. to form an oxide film 35. At this time, the oxidation rate on the side surface closer to the opening side is higher than the oxidation rate on the bottom surface of the groove. Therefore, it is possible to form an oxide film 35 having a shape in which the groove side surface is deeply oxidized while leaving the P-type electric field relaxation region 7a at the bottom portion by thermal oxidation. This oxide film 35 is a sacrificial oxide film that is later removed by hydrofluoric acid etching.

  Next, in FIG. 7C, after this thermal oxidation, the oxide film 35 is removed by hydrofluoric acid etching, whereby the groove 37 from which the side P-type field relaxation region 7 is removed can be formed.

  Next, as shown in FIG. 8A, the formation of a sacrificial oxide film by thermal oxidation and the hydrofluoric acid etching of the sacrificial oxide film are repeated to form a P-type electric field relaxation region 43 only at one end of the bottom surface. The formed tapered groove 39 is formed.

  Next, as shown in FIG. 8B, the anode electrode 9 and the cathode electrode 11 are formed by the same method as in the first embodiment, and the manufacture of the semiconductor device is completed.

[Description of operation]
Next, the operation of the semiconductor device of this embodiment will be described with reference to FIG.

[Reverse voltage characteristics]
FIG. 9A is a cross-sectional view illustrating the state of the depletion layer when a reverse voltage is applied to the semiconductor device of this embodiment. When a reverse voltage is applied, not only the depletion layer 45 extending from the anode electrode 9 but also the P-type electric field relaxation region 43 is formed at one end of the groove, so that the depletion layer 47 spreads from there. The electric field at the groove end is relaxed. Further, since the groove 39 has a tapered shape that is wide at the top and narrows toward the groove bottom, an effect of reducing the electric field at the end of the groove 39 is obtained.

[Forward voltage characteristics]
FIG. 9B is a cross-sectional view for explaining the state and current of the depletion layer when a forward voltage is applied to the semiconductor device of this embodiment. At the time of forward voltage application, in the structure of this embodiment, the depletion layer 49 remains in the P-type electric field relaxation region 43 formed at one end of the tapered groove 39 as in the first embodiment. Hinder forward current. However, the forward current 51 can flow around the other groove end where the P-type electric field relaxation region 43 is not provided without being blocked by the depletion layer. Further, since the P-type electric field relaxation region on the side surface of the groove is removed by an oxidation and etching process, the forward current 53 from the side surface of the groove also flows.

[Effect of this embodiment]
By using the groove side surface oxidation and oxide film removal process of this embodiment, the P-type electric field relaxation region 7 on one side surface of the tapered groove is removed, and a P-type electric field is applied only to one end portion of the groove bottom. A groove 39 having a shape leaving the relaxation region 43 can be formed.

  As shown in FIG. 7A, the shape of the semiconductor device of the present embodiment is such that the N − type drift region 3 of silicon carbide is etched under an etching condition such that a tapered shape is formed when the groove 39 is formed. Can also be obtained.

  Further, since the anode electrode 9 is formed so as to cover the groove 39 having a shape in which the P-type electric field relaxation region 43 is left only at one end portion of the groove bottom, the one where the P-type electric field relaxation region 43 of the groove 39 is formed. The contact between the anode electrode 9 and the N − type drift region 3 can also be obtained from the side surface. For this reason, if it is the same forward voltage, more forward currents can be sent than before. Further, the rising voltage of the forward current can be lowered as compared with the prior art.

<Third Embodiment>
[Description of Structure of Semiconductor Device]
Next, the structure of the third embodiment of the semiconductor device according to the present invention will be described with reference to FIG. This embodiment is a heterojunction diode (HJD) of SiC and Si in which the material of the anode electrode is polycrystalline silicon.

  In the present embodiment, a tapered groove 39 is formed in the N − -type drift region 3 as in the second embodiment. A P-type anode region 65 that makes a high barrier barrier between the SiC interface is embedded in the groove 39, and an N-type anode region 67 that makes a low barrier barrier between the SiC interface in the convex portion between the grooves. Adhere. The P-type anode region 65 and the N-type anode region 67 constitute an anode electrode 69. Other configurations are the same as those in the first and second embodiments.

[Description of manufacturing method]
Next, with reference to FIGS. 10 and 11, a method for manufacturing the semiconductor device of this embodiment will be described. First, using the process of the second embodiment, as shown in FIG. 10A, a groove 39 in which a P-type electric field relaxation region 43 is formed only at one end of the groove bottom is formed. This state is the same as FIG. 8A of the second embodiment.

  Next, as shown in FIG. 10B, a polycrystalline silicon film 55 is deposited so as to fill the trench 39 and cover the convex portion between the trench 39. Next, as shown in FIG. 10C, the polycrystalline silicon film 55 is covered with a patterned resist 57 except for the upper portion of the groove on the surface. Next, using the resist 57 as a mask, P-type impurities are implanted into the polycrystalline silicon film 55 by ion implantation 97 to form a P-type impurity implantation region 59.

  Next, as shown in FIG. 11A, after removing the resist 57, the surface of the P-type impurity implantation region 59 is covered with a patterned resist 61. Next, using the resist 61 as a mask, N-type impurities are implanted into the polycrystalline silicon film 55 by ion implantation 99 to form an N-type impurity implantation region 63.

  Next, impurity activation annealing is performed in the polycrystalline silicon to form a P-type impurity implantation region 59 to a P-type anode region 65 and an N-type impurity implantation region 63 to an N-type anode region 67. The P-type anode region 65 and the N-type anode region 67 constitute an anode electrode 69. Then, a cathode electrode 11 is formed on the back surface of the N + type silicon carbide substrate 1 by the same method as in the first embodiment. This state is shown in FIG.

[Description of operation]
Next, the operation of the semiconductor device of the third embodiment will be described with reference to FIG.

[Reverse voltage characteristics]
As shown in FIG. 12A, when a reverse voltage is applied, the depletion layer 71 spreads from the P-type anode region 65 and covers the N-type anode region 67 having a low barrier so that the electric field is relaxed. Further, the depletion layer 73 extends from the P-type electric field relaxation region 43 provided at one end of the groove bottom, and covers the other end of the groove bottom where the P-type electric field relaxation region 43 is not provided, so that the electric field is generated. The concentrated electric field at the groove end is relaxed.

[Forward voltage characteristics]
As shown in FIG. 12B, when a forward voltage is applied, a forward current flows from the anode electrode 69 to the cathode electrode 11. At this time, the depletion layer 77 remains in the vicinity of the P-type electric field relaxation region 43, but a path for passing the forward current 75 is ensured near the side surface of the groove where the P-type electric field relaxation region 43 is not provided. Therefore, a forward current 75 larger than that in the conventional example can be passed.

[Description of effects]
In the present embodiment, the P-type anode region 65 with a high barrier is disposed inside the groove, and the N-type anode region 67 with a low barrier is disposed on the convex portion between the grooves. With this configuration, when a reverse voltage is applied, the depletion layer 71 extends from the P-type anode region 65 having a high barrier from the end of the groove to the other groove end, and leakage current can be suppressed. Thereby, the characteristic of the high reverse withstand voltage and few reverse leakage currents equivalent to the past can be acquired. Further, the depletion layer 73 extending from the P-type electric field relaxation region 43 provided at one groove end can further relax the electric field concentrated on the groove end.

  When a forward voltage is applied, a large forward current can flow through the N-type anode region 67 having a low barrier. Since the groove end portion where the P-type electric field relaxation region 43 is not provided is provided, the forward current that is not inhibited by the depletion layer 77 remaining in the P-type electric field relaxation region 43 when the forward voltage is applied. A route is secured. As a result, more forward current than the conventional one can flow with the same forward voltage as the conventional one. Further, the rising voltage of the forward current can be lowered as compared with the prior art.

[Modification of Third Embodiment]
As a modification of the present embodiment, two types of Schottky barriers that form different heights when bonded to the N-type drift region 3 of silicon carbide instead of the P-type anode region 65 and the N-type anode region 67 are used. An anode electrode made of one of these metals can also be formed.

  That is, in this modification, instead of the P-type anode region 65, the first metal that forms the first Schottky junction having the first height Schottky barrier when bonded to the silicon carbide N-type drift region 3. Use materials. Further, instead of the N-type anode region 67, a second Schottky junction having a second Schottky barrier lower than the first height when bonded to the N-type drift region 3 of silicon carbide is formed. A metal material is used. Specific examples of the first and second metal materials include aluminum (work function: 4.4 [eV]), gold (5.2 [eV]), tungsten (4.4 [eV]), platinum (5 .3 [eV]) and so on. The metal having the larger work function becomes the first metal material, and the metal having the smaller work function becomes the second metal material.

  According to this modification, the semiconductor device becomes a Schottky junction diode, and there is an effect that a lower forward voltage can be obtained as compared with the third embodiment.

<Fourth embodiment>
Next, a fourth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

[Description of structure]
FIG. 13A is a plan view of the semiconductor device of this embodiment, and FIG. 13B is a cross-sectional view taken along the line AA ′ in FIG. The semiconductor device according to the present embodiment has a structure in which multiple annular grooves 79a, 79b, and 79c are arranged in an N− type drift region 3 of silicon carbide formed on the surface of the N + type silicon carbide substrate 1. Yes. In the present embodiment, the P-type electric field relaxation region 81 is formed on the outer peripheral side of the grooves 79a, 79b, and 79c, and the P-type electric field relaxation region 81 is not formed on the inner peripheral side of the grooves 79a, 79b, and 79c. . For this reason, the P-type electric field relaxation region 81 is formed on one side surface of the convex portion sandwiched between the grooves, and the P-type electric field relaxation region 81 is not formed on the other side surface side. . Then, a P-type anode region 80 made of P-type polycrystalline silicon is formed inside the grooves 79a, 79b, 79c, and an N-type anode region 82 made of N-type polycrystalline silicon is formed in the convex portion between the grooves. Is formed. The P-type anode region 80 and the N-type anode region 82 constitute an anode electrode. A cathode electrode 11 is formed on the back surface of N + type silicon carbide substrate 1.

  In the present embodiment, a triple annular groove is shown, but the number of multiplexed grooves is not limited to three, and any number may be used as long as it is two or more. In this embodiment, the annular groove has a quadrilateral shape with Rs at the corners. However, it may be a pentagon or more polygonal shape or a concentric groove.

[Description of manufacturing method]
The manufacturing method of the semiconductor device according to the present embodiment is the same as that of the third embodiment, and is therefore omitted.

[Description of operation]
Next, the operation of the semiconductor device of this embodiment will be described with reference to FIG.

[Reverse voltage characteristics]
In the structure of this embodiment, as in the third embodiment, not only the depletion layer 83 extending from the anode electrode (P-type anode region 80) when a reverse voltage is applied, but also a P-type electric field at one end of the groove bottom. Since relaxation region 81 is provided, depletion layer 85 extends from P-type electric field relaxation region 81. The depletion layer 83 and the depletion layer 85 alleviate the electric field at the end to the other end of the groove bottom.

[Description of effects]
When a reverse voltage is applied, the electric field concentrates on the outer ends of the groove bottoms of the multiple annular grooves 79a, 79b, and 79c. Therefore, each of the P-type electric field relaxation regions 81 (FIG. 13B) for relaxing the electric field It is installed at the outer edge of the groove. For this reason, the electric field at the groove bottom end can be further relaxed. When a forward voltage is applied, a depletion layer remains in the vicinity of the P-type electric field relaxation region 81, but a path through which a forward current flows near the side surface of the groove where the P-type electric field relaxation region 81 is not installed Is secured. For this reason, the rising voltage of the forward current can be lowered as compared with the conventional example.

<Fifth Embodiment>
Next, a fifth embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

[Description of structure]
FIG. 15A is a plan view of the semiconductor device of this embodiment, and FIG. 15B is a cross-sectional view taken along the line AA ′ in FIG. The semiconductor device according to the present embodiment has a structure in which grooves 87 are arranged in a lattice shape that intersects perpendicularly in the vertical and horizontal directions in the N− type drift region 3 formed on the surface of the N + type silicon carbide substrate 1. The N − -type drift region 89 serving as a convex portion between the lattice-like grooves 87 has a cellular quadrilateral shape. In the present embodiment, the P-type electric field relaxation region 81 is formed so as to be in contact with the two adjacent sides on the left and lower sides of the rectangular cell-shaped N-type drift region 89. For this reason, the P-type electric field relaxation region 81 is formed on one side surface of the convex portion sandwiched between the grooves, and the P-type electric field relaxation region 81 is not formed on the other side surface side. . In addition, a P-type anode region 88 made of P-type polycrystalline silicon is formed inside the groove 87, and an N-type anode region 91 made of N-type polycrystalline silicon is formed in the convex portion between the grooves. . The P-type anode region 88 and the N-type anode region 91 constitute an anode electrode. A cathode electrode 11 is formed on the back surface of N + type silicon carbide substrate 1.

[Description of operation]
Next, the operation of the semiconductor device of this embodiment will be described with reference to FIG.

[Reverse voltage characteristics]
In the structure of this embodiment, as in the third embodiment, not only the depletion layer 83 extending from the anode electrode (P-type anode region 88) but also the P-type electric field relaxation at one end of the groove bottom when a reverse voltage is applied. Since the region 81 is provided, the depletion layer 85 extends from the P-type electric field relaxation region 81. The depletion layer 83 and the depletion layer 85 alleviate the electric field at the end to the other end of the groove bottom.

[Description of effects]
In the present embodiment, the grooves 87 are arranged in a lattice shape, and the P-type electric field relaxation region 81 that relaxes the electric field is formed by two adjacent sides of the rectangular cell-shaped N − -type drift region 89 partitioned by the lattice of the grooves 87. Is arranged. For this reason, when a reverse voltage is applied, the groove end portions of the remaining two sides where the P-type electric field relaxation region 81 of the lattice-like groove 87 is not installed are used in the depletion layer 83 as in the third and fourth embodiments. , 85, and the reverse voltage characteristics similar to the conventional one can be maintained. When a forward voltage is applied, a depletion layer remains in the vicinity of the P-type electric field relaxation region 81, but a path through which a forward current flows near the side surface of the groove where the P-type electric field relaxation region 81 is not installed Is secured. For this reason, the rising voltage of the forward current can be lowered as compared with the conventional example.

1 N + type silicon carbide substrate (first conductivity type semiconductor substrate)
3 N-type drift region (first conductivity type drift region)
5 groove 5a side surface 5b bottom surface 7 P-type electric field relaxation region (second conductivity type electric field relaxation region)
9 Anode electrode (first electrode)
11 Cathode electrode (second electrode)

Claims (16)

A first conductivity type semiconductor substrate;
A drift region of a first conductivity type formed on the surface of the semiconductor substrate;
A groove formed in the surface of the drift region;
An electric field relaxation region of a second conductivity type formed at one end of the bottom surface of the groove and not formed at the other end;
A first electrode formed to cover the groove;
A second electrode formed on the back surface of the semiconductor substrate;
With
2. The semiconductor device according to claim 1, wherein the electric field relaxation region is formed only on one side surface of a convex portion sandwiched between two adjacent grooves.   2. The semiconductor device according to claim 1, wherein the first electrode is formed of a material different from a material of the drift region and becomes a unipolar diode.   The semiconductor device according to claim 1, wherein the first electrode is made of a semiconductor material having a band gap different from that of the drift region.   The first conductivity type is an N type, and the first electrode is formed of a material having a work function larger than an electron affinity of a material of the drift region. Semiconductor device.   5. The electric field relaxation region of the second conductivity type formed at one end of the bottom surface of the groove is formed to a position deeper than the bottom surface of the groove. 2. The semiconductor device according to claim 1. The first electrode is formed of polycrystalline silicon of the second conductivity type in the groove, and the first conductive type polycrystalline silicon is deposited on the convex portion sandwiched between the two adjacent grooves. the semiconductor device according to formed to claim 1 or claim 3, or claim 5, characterized in.   The first electrode is formed of a material that forms a first Schottky barrier having a first height when contacting the drift region in the groove, and the convex portion sandwiched between two adjacent grooves is the 3. The semiconductor device according to claim 1, wherein the semiconductor device is made of a material that forms a second Schottky barrier lower than the first height when contacting the drift region.   A plurality of the grooves are arranged in parallel, and a second conductivity type electric field relaxation region formed at one end portion of the bottom surface of the groove is formed at an end portion on the same side of all the grooves. The semiconductor device according to any one of claims 1 to 7. In the planar structure of the semiconductor device,
The groove is formed in a plurality of annularly or concentrically arranged,
8. The semiconductor according to claim 1, wherein an electric field relaxation region of the second conductivity type is formed at an end portion of a bottom surface connected to a side surface on an outer peripheral side of the groove. apparatus. In the planar structure of the semiconductor device,
The grooves are arranged in a grid, said grooves, one side of the first direction, and the second conductive at an end portion of the bottom surface that connects one side of the direction perpendicular to the first direction, the The semiconductor device according to claim 1, wherein a type electric field relaxation region is formed. A second conductivity type electric field relaxation region is formed by ion implantation using the patterned first mask on the surface of the semiconductor substrate in which the first conductivity type drift region is formed on the surface of the first conductivity type semiconductor substrate. A first step;
A second step of removing a portion of the first mask to form a second mask and exposing a portion of the surface of the drift region;
A third step of forming an oxide film on the surface of the exposed drift region, the surface and the side surface of the second mask;
A fourth step of forming a sidewall covering a part of the surface of the electric field relaxation region on a side surface of the second mask by dry etching the oxide film;
A fifth step of etching the drift region and the electric field relaxation region using the second mask and the sidewall as a mask to form a groove;
A sixth step of forming a first electrode so as to cover the groove after removing the second mask and the sidewall;
A seventh step of forming a second electrode on the back surface of the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:   In the fourth step, an end of the sidewall is disposed in the electric field relaxation region, and in the fifth step, one of the bottom surfaces of the grooves is etched by etching the drift region and the electric field relaxation region. The method for manufacturing a semiconductor device according to claim 11, wherein an end portion is covered with the electric field relaxation region.   In the fifth step, the drift region is etched so that the side surface of the groove has a tapered shape, the electric field relaxation region on the side surface of the groove is removed, and only at one end of the bottom surface of the groove The method of manufacturing a semiconductor device according to claim 11, wherein an electric field relaxation region is formed.   After the fifth step, a sacrificial oxide film is formed on the side surface of the groove by thermal oxidation, and then the sacrificial oxide film is etched to remove the electric field relaxation region on the side surface of the groove. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of forming only at one end of the bottom surface of the groove. The sixth step includes
Depositing a polycrystalline silicon film on the surface of the semiconductor substrate in which the groove is formed;
A second conductivity type impurity implantation region in which a second conductivity type impurity is selectively implanted into the polycrystalline silicon film inside the trench, and a second selective conductivity in the polysilicon film between two adjacent trenches. Forming a first conductivity type impurity implantation region into which an impurity of one conductivity type is implanted;
A first electrode having a second conductivity type polycrystalline silicon region and a first conductivity type polycrystalline silicon region is formed by activating annealing the second conductivity type impurity implantation region and the first conductivity type impurity implantation region. And a process of
15. The method of manufacturing a semiconductor device according to claim 11, further comprising: The sixth step includes forming a first Schottky junction by depositing a material that forms a Schottky barrier having a first height when contacting the drift region inside the groove;
Forming a second Schottky junction by depositing a material that forms a second Schottky barrier lower than the first height when contacting the drift region on a convex portion between two adjacent grooves; When,
15. The method of manufacturing a semiconductor device according to claim 11, further comprising:

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