JP5669712B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device, more particularly to a method of manufacturing a semiconductor equipment available under high withstand voltage.

  A semiconductor device using SiC (silicon carbide) is known as a device having excellent temperature characteristics and withstand voltage characteristics. However, many problems to be solved remain in the manufacturing technology of a semiconductor device using SiC, and there are many problems especially for a high voltage device. As one of them, it is known that an electric field peak (electric field concentration) occurs in the outer edge portion of the active region of a semiconductor element operating as a power device under a high breakdown voltage. Therefore, in order to realize a device that operates stably even under a high breakdown voltage, an appropriate termination structure that can alleviate electric field concentration around the semiconductor element is required.

  Conventionally, a structure in which a pn junction is provided is used as such a termination structure. Of the p-type region that forms the pn junction, the end of the semiconductor element opposite to the active region has a high electric field. In order to alleviate electric field concentration there, for example, Patent Document 1 proposes a structure in which p-type regions having different concentrations and depths are formed on the end portions. As a method for forming regions having different depths and concentration distributions, as disclosed in Patent Document 2 and Patent Document 3, a method of combining an oxide film as an implantation mask is known.

JP-A-7-99328 JP 2005-135972 A JP-A-2-231711

  However, in order to form a deep p-type region separately at the end of the p-type region, a plurality of ion implantation masks for overlapping p-type regions having different concentrations and depths and a plurality of times of ion implantation are used. An injection process is required. As a result, there is a problem that the manufacturing cost increases. In addition, there is a problem that a highly reliable semiconductor device in which electric field concentration is further reduced is desired.

  Therefore, the present invention has been made in view of the above-described problems, and an object thereof is to provide a technique capable of suppressing an increase in manufacturing cost. Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a termination structure comprising a pn junction is provided on the outer periphery of a semiconductor element, and (a) a first conductivity type on a semiconductor substrate having an off angle. Forming a drift layer, an insulating film, and a resist in this order; and (b) forming a first opening in the insulating film, and forming the first opening and the first opening in the resist. Forming a second opening that exposes the surrounding insulating film, ie, the through insulating film; and (c) implanting a second conductivity type impurity into the drift layer through the insulating film and the resist. Forming an impurity region having the second conductivity type, which forms the pn junction with the drift layer and has an end portion deeper than the central portion, on the drift layer. The concentration of the second conductivity type impurity contained in the impurity region decreases as the impurity region increases from a predetermined depth to the impurity region, and the degree of reduction is more gentle at the end than at the center. It is.

  According to the present invention, the degree of reduction of the impurity concentration in the impurity region is gentler at the end than at the center. Accordingly, since the electric field concentration at the end of the impurity region, that is, the electric field concentration at the end of the semiconductor element can be reduced, the reliability of the semiconductor device can be improved.

  According to the present invention, impurity regions having different depths and concentration changes at the end portion and the central portion can be manufactured in a single ion implantation step, so that the manufacturing cost can be reduced.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment. FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. As shown in FIG. 1, this semiconductor device includes an SiC substrate 1 that is an n-type (first conductivity type) wide band gap semiconductor substrate, an n-type drift layer 2 containing SiC, and a p-type (second type). P-type regions 13 and 23 which are impurity regions of conductivity type, an insulating film 17, an anode electrode (Schottky electrode) 18, a cathode electrode 19, and a metallized electrode (wiring electrode) 20.

  Among these, the SiC substrate 1, the drift layer 2, the anode electrode 18, and the cathode electrode 19 constitute a Schottky barrier diode 51, and the drift layer 2 and the p-type regions 13 and 23 constitute a pn junction 52. . Therefore, in the semiconductor device according to the present embodiment, a termination structure including the pn junction 52 is provided on the outer periphery of the Schottky barrier diode 51 that is a semiconductor element (here, the outer periphery of the anode electrode 18). Next, components of the semiconductor device according to the present embodiment will be described in detail.

  In the present embodiment, SiC substrate 1 has an off angle of 2 ° to 10 ° in the <11-20> direction from the (0001) plane, for example. Here, the SiC substrate 1 will be described below assuming that it has an off angle of 4 ° in the <11-20> direction from the (0001) plane.

Drift layer 2 is formed on SiC substrate 1. The doping concentration and thickness of the drift layer 2 are set according to the withstand voltage assumed in the Schottky barrier diode 51. In the present embodiment, the drift layer 2 has a doping concentration of 5 × 10 ^{14 to} 3 × 10 ¹⁶ cm ⁻³ and the drift layer 2 has a thickness of 4 to 150 μm.

  An anode electrode 18 that is Schottky connected thereto is selectively formed on the upper surface of the drift layer 2, and a metallized electrode 20 is formed on the anode electrode 18. On the upper surface of the drift layer 2 where the anode electrode 18 is not formed, an insulating film 17 covering the end portions of the anode electrode 18 and the metallized electrode 20 is formed. A cathode electrode 19 of a Schottky barrier diode 51 is formed on the bottom surface of the SiC substrate 1.

  As described above, the drift layer 2 and the upper portion of the drift layer 2 located on the outer periphery of the anode electrode 18 (the end of the anode electrode 18 and the outside thereof) (the portion of the drift layer 2 opposite to the SiC substrate 1) The p-type regions 13 and 23 constituting the pn junction 52 are selectively formed. Among these, the p-type region 13 is connected to the end of the anode electrode 18. Specifically, the p-type region 13 is selectively formed in a region including a portion in contact with the edge of the anode electrode 18 in the upper part of the drift layer 2.

  On the other hand, the p-type region 23 is formed outside the anode electrode 18. That is, the p-type region 23 is formed away from the p-type region 13 on the side opposite to the active region of the Schottky barrier diode 51 (the region where the anode electrode 18 of the drift layer 2 is formed) with respect to the p-type region 13. ing. In the present embodiment, a plurality (three in FIG. 1) of such p-type regions 23 are arranged. That is, in the present embodiment, a plurality of p-type regions 13 and 23 are disposed on the outer periphery of the Schottky barrier diode 51 (four in total in FIG. 1). Further, as shown in FIG. 1, in each of the p-type regions 13 and 23, the end portion is deeper than the central portion.

  2 and 3 are diagrams showing a method of manufacturing the semiconductor device according to the present embodiment configured as described above. Next, the said manufacturing method is demonstrated using FIG.2 and FIG.3. In particular, the process for creating the pn junction 52 constituting the termination structure will be described in detail here.

First, drift layer 2 is formed on SiC substrate 1. In the present embodiment, the drift layer 2 is formed so that the impurity concentration region is 5 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ . Subsequently, an oxide film 31 that is an insulating film and a resist 32 are formed in this order on the drift layer 2. In the present embodiment, the thickness of the oxide film 31 is 20 nm. The oxide film 31 may be formed by either dry oxidation or wet oxidation, or may be formed by deposition.

  Next, an opening pattern 32a is formed in the resist 32 by selectively developing and etching the resist 32 by a photolithography process. Then, the first opening 31 a is formed in the oxide film 31 by etching the oxide film 31 using the resist 32 in which the opening pattern 32 a is formed as a mask. The configuration shown in FIG. 2 is obtained by performing the above steps.

  Then, a step of narrowing the resist 32 (step of widening the opening pattern 32a of the resist 32) is performed. That is, as shown in FIG. 3, the second opening 32b exposing the first opening 31a and the oxide film 31 around the first opening 31a (hereinafter also referred to as “through oxide film 31b”). Is formed on the resist 32. Here, as a step of thinning the resist 32, it is conceivable to perform dry etching as described in, for example, Japanese Patent Application Laid-Open No. 2009-49363 for a short time to remove the peripheral portion of the resist 32.

  As described above, in this embodiment, since the thickness of the oxide film 31 is 20 nm, the thickness of the through oxide film 31b is also 20 nm. In addition, the dimension of the through oxide film 31b protruding from the inner wall of the second opening 32b is preferably about 0.3 μm to 1 μm in consideration of the accuracy of etching and the effectiveness for electric field relaxation.

Next, p-type impurities are ion-implanted into the drift layer 2 using the two-layer structure including the oxide film 31 and the resist 32 shown in FIG. That is, p-type impurities are ion-implanted into the drift layer 2 through the oxide film 31 and the resist 32. In the present embodiment, it is assumed that aluminum, which is a p-type impurity, is ion-implanted with an energy of 450 to 500 keV from a direction perpendicular to the surface (crystal plane) of SiC substrate 1. When such ion implantation is performed on the structure as described above, the p-type regions 13 and 23 whose end portions are deeper than the central portion are formed as shown in FIG. In the present embodiment, it is assumed that the p-type regions 13 and 23 are formed so that the impurity concentration region is 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ .

  Here, in the p-type regions 13 and 23, the reason why the end portion under the through oxide film 31b is deeper than the central portion under the first opening portion 31a will be considered.

  In general, in a normal semiconductor substrate such as silicon, the surface is just a plane with respect to the crystal orientation, or at most about 2 ° from the crystal orientation even if it has an off angle. When ions are implanted into such a normal semiconductor substrate from the direction perpendicular to the surface, a channeling phenomenon occurs in which impurities reach a position deeper than the desired depth through a gap in the atomic arrangement in the substrate. Therefore, when ion implantation is performed on a normal semiconductor substrate, in order to suppress this channeling phenomenon, ion implantation is generally performed in an orientation shifted from the vertical direction with respect to the semiconductor substrate surface.

  On the other hand, in order to control crystal polymorphism, the surface of the SiC substrate has an off angle of 4 ° to 8 ° with respect to the crystal orientation and 2 ° to 10 ° even if the range is broadly estimated. Therefore, even if ions are implanted from the vertical direction without shifting with respect to the SiC substrate surface, the channeling phenomenon is originally suppressed. As a result, it is considered that the impurities ion-implanted into the drift layer 2 through the first opening 31a and the second opening 32b reach only a relatively shallow position from the surface of the p-type regions 13 and 23. On the other hand, the impurities ion-implanted into the drift layer 2 through the through oxide film 31b and the second opening 32b are appropriately scattered in the through oxide film 31b so that the channeling phenomenon is likely to occur. , 23 is considered to have reached a relatively deep position from the surface.

  As a result, the impurity ion-implanted through the through oxide film 31b and the second opening 32b is closer to the surface of the p-type regions 13 and 23 than the impurity ion-implanted through the first opening 31a and the second opening 32b. It is considered that the p-type regions 13 and 23 that have reached a deep position and whose end portions are deeper than the central portion are formed.

  FIG. 4 is a diagram showing the result of examining the change in the concentration of the p-type impurity contained in the p-type regions 13 and 23 formed by the ion implantation according to the present embodiment in the depth direction from the surface. is there. In FIG. 4, the plot “◯” indicates the concentration of the p-type impurity on the “one-dot chain line a” in FIG. Similarly, in FIG. 4, the “+” plot indicates the concentration of the p-type impurity on the “one-dot chain line b” in FIG. 3, that is, the concentration of the p-type impurity at the ends of the p-type regions 13 and 23.

  As can be seen from FIG. 4, the concentration of the p-type impurity contained in the p-type regions 13 and 23 decreases with increasing depth from the predetermined depth of the p-type regions 13 and 23, and the degree of the reduction (inclination in FIG. 3). ) Is gentler at the end than at the center. Further, the p-type impurities contained in the p-type regions 13 and 23 reach deeper at the end than at the center.

  After the p-type regions 13 and 23 are formed by the above ion implantation, the resist 32 and the oxide film 31 shown in FIG. 3 are removed. Thereafter, the structure obtained by the above steps is annealed to activate impurities (ions) implanted in various impurity regions such as the p-type regions 13 and 23. Then, the Schottky barrier diode 51 is completed by forming the cathode electrode 19, the anode electrode 18, the metallized electrode 20, and the insulating film 17.

  According to the semiconductor device according to the present embodiment configured as described above, the degree of reduction in the concentration of the p-type impurity in the p-type regions 13 and 23 is more gradual at the end than at the center. Therefore, since the electric field concentration at the ends of the p-type regions 13 and 23, that is, the electric field concentration at the end of the Schottky barrier diode 51 can be reduced, the reliability of the semiconductor device can be improved.

  Further, according to the semiconductor device of the present embodiment, a plurality of p-type regions 13 and 23 as described above are arranged on the outer periphery of the Schottky barrier diode 51. Therefore, the electric field concentration at the end of the Schottky barrier diode 51 can be further relaxed, and the reliability of the semiconductor device can be further improved.

  In addition, according to the method for manufacturing a semiconductor device according to the present embodiment, p-type regions 13 and 23 having different depths and concentration changes in the end portion and the central portion can be manufactured in a single ion implantation step. Therefore, the manufacturing cost can be reduced.

  In the above description, the p-type regions 13 and 23 are formed in which both end portions are more slowly changing in concentration than the central portion and reach deeper. However, the present invention is not limited to this, and only the outer end portion (the end portion opposite to the Schottky barrier diode 51) forms the p-type regions 13 and 23 whose concentration change is gentler than the central portion and reaches deeper. You may do it. In order to form such p-type regions 13 and 23, for example, as the second opening 32b shown in FIG. 3, the opening that exposes the first opening 31a and the through oxide film 31b only on the outside is exposed. May be formed.

In the above description, the thickness of the through oxide film 31b is assumed to be 20 nm. Here, in FIG. 5, the energy concentration is 450 keV, the ion implantation amount is 3 × 10 ¹³ cm ⁻² , and the impurity concentration when the p-type impurity aluminum is ion-implanted into the drift layer 2 is examined in the depth direction. Results are shown. As shown in FIG. 5, the concentration when the through oxide film 31b having a thickness of 20 to 100 nm is provided is lower in the depth direction than the concentration when the through oxide film 31b is not provided. The degree is moderate. Therefore, the through oxide film 31b having a thickness of 20 to 100 nm can be used under the above ion implantation conditions. Note that the through insulating film described as the through oxide film 31b is not limited to the oxide film as long as it is an amorphous insulating film having a density similar to that of the silicon oxide film. It is considered that the thickness of the through insulating film to be included should be changed as appropriate depending on the material, ion implantation conditions, and types of impurities.

In the above description, the drift layer 2 is ion-implanted with aluminum, which is a p-type impurity. FIG. 6 shows the result of examining the impurity concentration in the depth direction when various oxides are ion-implanted with the thickness of the through oxide film 31b being 20 nm. Here, the energy is 110 keV, the ion implantation amount is 1.4 × 10 ¹³ cm ⁻² , the result of ion implantation of aluminum (Al), the energy is 250 keV, and the ion implantation amount is 3.0 × 10 ¹² cm. ^-2 is the result of ion implantation of boron (B) as a p-type impurity, and the energy is 350 keV, the ion implantation amount is 5.3 × 10 ¹³ cm ^-2 , and nitrogen (N) as an n-type impurity And the result of ion implantation.

  As shown in FIG. 6, even when boron is used, the concentration when the through oxide film 31b is present is more moderately reduced in the depth direction than the concentration when the through oxide film 31b is not present. Therefore, boron can be used instead of aluminum. Even when nitrogen is used, the concentration in the presence of the through oxide film 31b is less gradual in the depth direction than the concentration in the absence of the through oxide film 31b. Therefore, an n-type region having the same tendency as the profile of the p-type regions 13 and 23 described above can be formed in the p-type semiconductor layer.

  In the above description, the SiC substrate 1 has been described as an example. However, any semiconductor substrate having an off angle may be used, and it can be applied to a silicon substrate or a GaN substrate.

<Embodiment 2>
The configuration of the semiconductor device according to the second embodiment of the present invention is substantially the same as that of the first embodiment. In the present embodiment, the manufacturing method is different from that in the first embodiment. In the present embodiment, the same or similar parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  7 and 8 are views showing a method of manufacturing the semiconductor device according to the present embodiment, and correspond to FIGS. 2 and 3, respectively. Hereinafter, the manufacturing method will be described with reference to FIGS.

  First, the drift layer 2, the oxide film 31 that is an insulating film, and the resist 32 are formed on the SiC substrate 1 in this order. Then, the resist 32 is selectively developed and etched by a photolithography process, thereby forming an opening pattern 32a in the resist 32. Then, the first opening 31 a is formed in the oxide film 31 by etching the oxide film 31 using the resist 32 in which the opening pattern 32 a is formed as a mask. At this time, as shown in FIG. 7, the etching conditions for the oxide film 31 are appropriately set so that the oxide film 31 has a tapered shape having a lateral width of, for example, 0.3 μm or more and 1 μm or less around the first opening 31a. select.

  Then, as in Embodiment Mode 1, a step of thinning the resist is performed. Since the oxide film 31 is etched as described above, as shown in FIG. 8, the through oxide film 31b according to the present embodiment has a tapered shape around the first opening 31a. Next, ion implantation is performed in the same manner as in the first embodiment. In this embodiment, since ions are implanted through the through oxide film 31b having a tapered shape, the p-type region 13 not only has the structure described in the first embodiment but also has a gradual change in concentration in the lateral direction. , 23 are formed in the drift layer 2.

  Then, similar to the first embodiment, the resist 32 and the oxide film 31 are removed and annealed, and then the cathode electrode 19, the anode electrode 18, the metallized electrode 20, and the insulating film 17 are formed. The Schottky barrier diode 51 is completed.

  According to the method of manufacturing a semiconductor device according to the present embodiment as described above, not only can the same effect as in the first embodiment be obtained, but also the p-type region 13 in which the concentration change is gentle in the lateral direction. , 23 can be formed in the drift layer 2. Therefore, the electric field concentration at the end of the Schottky barrier diode 51 can be further relaxed, and the reliability of the semiconductor device can be further improved.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 SiC substrate, 2 drift layer, 13, 23 p-type region, 31 oxide film, 31a first opening, 31b through oxide film, 32 resist, 32b second opening, 51 Schottky barrier diode, 52 pn junction.

Claims (5)

A method of manufacturing a semiconductor device in which a termination structure comprising a pn junction is provided on the outer periphery of a semiconductor element,
(A) forming a first conductivity type drift layer, an insulating film, and a resist in this order on a semiconductor substrate having an off angle ;
(B) A first opening is formed in the insulating film, and a second opening that exposes the first opening and the through insulating film that is the insulating film around the first opening is formed in the resist. Forming, and
( C) Impurities of the second conductivity type are ion-implanted into the drift layer through the insulating film and the resist, so that the drift layer and the pn junction are formed, and the end portion is more than the center portion. Forming a deep impurity region having the second conductivity type on the drift layer ;
The concentration of the impurity of the second conductivity type contained in the impurity region decreases as the impurity region becomes deeper from a predetermined depth, and the degree of reduction is more gentle at the end portion than at the central portion. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device , wherein the semiconductor substrate is a SiC substrate having an off angle of 2 to 10 degrees from a (0001) plane. A method of manufacturing a semiconductor device according to claim 1 or 2,
The through insulating film is Ru der than 100nm or less 20nm thickness, a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to any one of claims 1 to 3 ,
The through insulating film, that has a first opening near the tapered, a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 4,
The method of manufacturing a semiconductor device, wherein the tapered shape has a lateral width of 0.3 μm or more and 1 μm or less .

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