JP5811930B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide (hereinafter referred to as SiC) semiconductor device.

  Conventionally, a SiC semiconductor device including a Schottky barrier diode (hereinafter referred to as SBD) has been proposed (see, for example, Patent Documents 1 and 2). In the SBD, as shown in FIG. 9A, after forming the Schottky electrode J2 on the surface of the drift layer J1 made of SiC, the junction electrode J3 and the surface electrode J4 are formed on the surface of the Schottky electrode J2. It is structured. For example, Ti or Ni is generally used for the bonding electrode J3, and Al or the like is generally used for the surface electrode J4.

JP 2007-149839 A JP 2008-210938 A

  However, in order to investigate the secular change due to the acceleration test, a durability test or a high-temperature energization test was conducted, and it was confirmed that an element leading to breakdown was generated.

  It is presumed that the occurrence of such an element that breaks down is due to the following mechanism. First, as shown in FIG. 9B, when the SBD is manufactured, Ti constituting the junction electrode J3 and the surface electrode J4 is formed on the Schottky electrode J2 by the pinhole formed on the Schottky electrode J2 or the particle J5. Al or the like enters, and contact between SiC and Ti or Al occurs. When the load due to use is applied in this state, the temperature of the element rises, and with this temperature rise, the ohmic contact between Ti and SiC or the contact area between SiC due to Al migration increases. It is considered that the characteristics change with such a change in the contact state between SiC and Ti or Al, and current concentration locally occurs in that portion during use, leading to element breakdown.

  Specifically, when the reverse leakage waveform is examined, as shown in FIG. 10 (a), the characteristics indicating the relationship between the reverse voltage and the reverse current are in the initial stage of use due to the characteristic variation due to use. Compared with the normal waveform (solid line), the waveform changed to a waveform (broken line) in which a high reverse current was generated at a lower reverse voltage. Further, when the forward waveform is examined, as shown in FIG. 10B, the characteristic indicating the relationship between the forward voltage and the forward current is a normal waveform (solid line) in the initial stage of use due to the characteristic variation due to use. ) In comparison with (), a waveform (broken line) in which the forward current increases even at a lower forward voltage. Also from such a change in characteristics, it is considered that the element has been destroyed based on the mechanism as described above.

  Such a SiC semiconductor device that causes element destruction due to use is preferably manifested in the manufacturing stage from the viewpoint of product reliability, etc., and can be removed as a defective chip before it goes on the market.

  In view of the above points, the present invention provides a SiC semiconductor device in which defective chips can be removed and only good chips can be selected by performing a process in which whether or not element destruction will occur in the manufacturing stage is revealed in the future. It aims at providing the manufacturing method of.

  In order to achieve the above object, in the present invention, the step of forming the bonding electrode (8) on the surface of the Schottky electrode (4), and the barrier height of the bonding electrode is higher than that of the Schottky electrode after the bonding electrode is formed. The first annealing process at a lower temperature, the step of forming the surface electrode (9) on the surface of the bonding electrode, and the second annealing at the temperature at which the constituent material of the surface electrode causes migration after the surface electrode is formed. And a step of selecting a good chip and a defective chip by performing good / bad judgment based on the characteristics of the Schottky barrier diode (10) after the first and second annealing treatments. It is characterized by being.

  As described above, after the formation of the bonding electrode, the first annealing treatment is performed at a temperature at which the barrier height of the bonding electrode is lower than that of the Schottky electrode. Even after the surface electrode is formed, the annealing process is performed at a temperature at which the constituent material of the surface electrode causes migration. As a result, whether or not element destruction will occur in the future can be made apparent at the manufacturing stage, and in the process of determining good or defective, it is possible to remove defective chips and select only good chips.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a cross-sectional view of an SiC semiconductor device according to a first embodiment of the present invention. FIG. 2 is a top surface layout diagram of the SiC semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing process of the SiC semiconductor device shown in FIG. 1. FIG. 4 is a cross-sectional view showing a manufacturing step of the SiC semiconductor device following FIG. 3. It is the expanded sectional view which expanded a part of Drawing 4 (c)-Drawing 4 (e). 5 is a chart showing the relationship between the barrier height and the annealing temperature of the constituent material of the Schottky electrode 4 and the constituent material of the bonding electrode 8. It is sectional drawing of the SiC semiconductor device concerning 2nd Embodiment of this invention. FIG. 8 is a top surface layout diagram of the SiC semiconductor device shown in FIG. 7. It is a partial expanded sectional view of SBD. 10 is a graph showing a reverse leakage waveform and forward characteristics of the SBD shown in FIG. 9.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A first embodiment of the present invention will be described. First, the structure of the SiC semiconductor device manufactured by the manufacturing method of the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 1 corresponds to the AA cross-sectional view of FIG.

As shown in FIG. 1, the SiC semiconductor device is formed using an n ⁺ type substrate 1 made of silicon carbide having an impurity concentration of about 2 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , for example. When the upper surface of the n ⁺ -type substrate 1 is the main surface 1a and the lower surface opposite to the main surface 1a is the back surface 1b, a dopant concentration lower than that of the substrate 1 on the main surface 1a, for example, 1 × 10 ¹⁴ to 1 × An n ⁻ type layer 2 made of silicon carbide having an impurity concentration of about 10 ¹⁷ cm ⁻³ is laminated. The SBD 10 is formed in the cell portion of the SiC semiconductor substrate constituted by the n ⁺ -type substrate 1 and the n ⁻ -type layer 2, and the termination structure is formed in the outer peripheral region of the SiC semiconductor device. Yes.

Specifically, an insulating film 3 made of, for example, a silicon oxide film is formed on the surface of the n ⁻ type layer 2. In the insulating film 3, an opening 3a is partially formed in the cell portion. For example, Mo (molybdenum) is used so as to make Schottky contact with the n ⁻ type layer 2 in the opening 3a of the insulating film 3. A configured Schottky electrode 4 is formed. An ohmic electrode 5 made of, for example, Ni (nickel), Ti (titanium), Mo, Au (gold) or the like is formed so as to be in contact with the back surface of the n ⁺ type substrate 1. Thereby, SBD10 is comprised. Any layout may be used for the top surface of the SBD 10, but in the present embodiment, each corner is rounded as shown in FIG.

Further, as a termination structure formed in the outer peripheral region of the SBD 10, a p-type RESURF layer 6 is formed on the outer edge portion of the Schottky electrode 4 so as to be in contact with the Schottky electrode 4 on the surface layer portion of the n ⁻ -type layer 2. In addition, a plurality of p-type guard ring layers 7 and the like are arranged so as to further surround the outer periphery of the p-type RESURF layer 6 to form a termination structure. The p-type RESURF layer 6 and the p-type guard ring layer 7 are formed using, for example, Al as an impurity. For example, the p-type RESURF layer 6 and the p-type guard ring layer 7 are formed with an impurity concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁹ cm ^−3. Yes. By disposing the p-type RESURF layer 6 and the p-type guard ring layer 7, the electric field can extend over a wide range on the outer periphery of the SBD 10, and the electric field concentration can be reduced. For this reason, a proof pressure can be improved.

  Further, a bonding electrode 8 and a surface electrode 9 are sequentially laminated on the surface of the Schottky electrode 4. The bonding electrode 8 is made of, for example, a metal material such as Ti or Ni, is provided as a barrier layer between the Schottky electrode 4 and the surface electrode 9, and is set to a barrier height lower than that of the Schottky electrode 4. Yes. The surface electrode 9 is made of a metal material such as Al, and serves as a pad to which a bonding wire or the like is connected. With such a structure, the SBD 10 is configured.

  In the SiC semiconductor device provided with the SBD 10 having such a structure, the Schottky electrode 4 is used as an anode, the ohmic electrode 5 is used as a cathode, and a voltage exceeding the Schottky barrier is applied to the Schottky electrode 4 to thereby form the Schottky electrode. A current is passed between 4 and the ohmic electrode. In addition, since the p-type RESURF layer 6 and the p-type guard ring layer 7 are provided for the outer peripheral region, the equipotential lines can be extended over a wide range without deviation. As a result, a high breakdown voltage element can be obtained.

  Next, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 3 and 4 show cross sections during the manufacturing process of the SiC semiconductor device shown in FIG. 1, the p-type guard ring layer 7 is omitted for simplification.

First, as shown in FIG. 3A, a SiC semiconductor substrate is prepared in which an n ⁻ type layer 2 is epitaxially grown on a main surface 1a of an n ⁺ type substrate 1 having, for example, a Si surface or a C surface as a main surface 1a. Next, as shown in FIG. 3B, after an oxide film 11 serving as an ion implantation mask made of LTO (low-temperature oxide) or the like is disposed using a CVD apparatus or the like, A resist 12 is applied to the substrate.

Subsequently, as shown in FIG. 3C, the resist 12 is patterned by photolithography, and the resist 12 is subjected to RIE (Reactive Ion Etching) or ICP (Inductively Coupled Plasma) etcher using CHF ₃ or CF ₄ gas. The oxide film 11 is removed in the opening portion. Thereby, regions where the p-type RESURF layer 6 and the p-type guard ring layer 7 are to be formed in the oxide film 11 are opened.

  Then, as shown in FIG. 3D, after the p-type impurity such as aluminum or boron is ion-implanted using the oxide film 11, the oxide film 11 is removed by HF. Thereby, the p-type RESURF layer 6 and the p-type guard ring layer 7 are formed. Here, the case where the p-type RESURF layer 6 and the p-type guard ring layer 7 are formed at the same time has been described. However, when these layers are formed at different concentrations and different depths, they may be formed by separate steps. .

Further, as shown in FIG. 3E, the surface of the n ⁻ type layer 2 on which the p-type RESURF layer 6 and the like are formed is capped with a carbon layer 13 formed by carbonizing a resist, for example. Then, cap annealing, that is, activation annealing of p-type impurities contained in the p-type RESURF layer 6 and the like is performed in this state. For example, it heats in the range of 1600-2000 degreeC. Thereby, the ion-implanted atoms are activated.

Thereafter, as shown in FIG. 4A, the carbon layer 13 is removed. For example, the carbon layer 13 is removed using oxygen (O ₂ ) plasma by an ashing device or by performing an oxidation treatment in an O ₂ atmosphere after raising the temperature of the oxidation furnace at 600 ° C. or higher. Then, after performing a flattening process as necessary, an insulating film 3 is formed on the surface of the n ⁻ -type layer 2 and the p-type RESURF layer 6 as shown in FIG. Opening 3a is formed in

Then, as shown in FIG. 4C, a Schottky electrode 4 made of Mo or the like is deposited on the surface of the n ⁻ type layer 2 including the surfaces of the p type RESURF layer 6 and the p type guard ring layer 7. Alternatively, after forming a film by sputtering or the like, a step of patterning the Schottky electrode 4 into a desired shape is performed. At this time, if there is a possibility that the chip is determined to be a defective chip later, as shown in FIG. 5A, the Schottky electrode 4 is partially lifted due to the presence of the particle 20, or the Schottky electrode 4 is present. A pinhole 21 may be formed on the surface.

Subsequently, as shown in FIG. 4D, a bonding electrode 8 made of Ti, Ni, or the like is formed on the surface of the Schottky electrode 4 by vapor deposition or sputtering, and the bonding electrode 8 is formed in a desired shape. A patterning process is performed. At this time, as for the case where the Schottky electrode 4 was partially lifted due to the presence of the particles 20 and the case where the pinhole 21 was formed in the Schottky electrode 4, as shown in FIG. In some cases, the constituent material of the bonding electrode 8 may enter and be in contact with the underlying n ⁻ -type layer 2.

  In such a state, when a forward voltage or a reverse voltage is applied in a good / bad determination process described later, the characteristic is that the chip is basically a defective chip. However, depending on the contact area and the temperature at which the bonding electrode 8 is formed, it is still a defective chip at the initial stage of product completion, that is, before a load is applied due to use, in the process of determining good or defective. May not appear as a characteristic. In such a case, it will be determined as a good chip to become a defective chip in future use, and the reliability of the product may be impaired.

  For this reason, after forming the bonding electrode 8, an annealing process (first annealing process) is performed, so that a defective chip is revealed in a future chip that becomes a defective chip by use, and is a defective chip. So that the characteristic indicating That is, it is considered that the characteristic change due to the bonding electrode 8 occurs when the barrier height is lower than that of the Schottky electrode 4 in the defective portion. For this reason, if the annealing process performed after forming the bonding electrode 8 is performed under the condition that the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4, it is a defective chip in the good / bad determination process. The characteristic which shows that appears.

Therefore, the annealing process is performed as a temperature condition in which the barrier height of the bonding electrode 8 is lower than the barrier height of the Schottky electrode 4 with respect to the n ⁻ -type layer 2. Specifically, as shown in FIG. 6, when the annealing process is not performed or the annealing temperature is low, the barrier height of the Schottky electrode 4 and the barrier height of the bonding electrode 8 are equal or the former is lower than the latter. However, when the annealing temperature is increased, the barrier height of the bonding electrode 8 is lower than the barrier height of the Schottky electrode 4. This relationship is established when the Schottky electrode 4 is made of Mo and the bonding electrode 8 is made of Ti, and the annealing temperature is 500 ° C. or more, and the Schottky electrode 4 is made of Mo. In addition, when the joining electrode 8 is made of Ni, it is confirmed that the annealing temperature is established at 700 ° C. or higher. Therefore, the annealing process is performed under a temperature condition that satisfies this relationship. As for the annealing treatment, the higher the temperature, the larger the difference between the barrier height of the Schottky electrode 4 and the barrier height of the bonding electrode 8, but it is necessary to be below the melting point of the metal constituting them. The temperature condition is preferably 1100 ° C. or lower.

Thereafter, as shown in FIG. 4E, a surface electrode 9 made of Al or the like is formed on the surface of the bonding electrode 8 by vapor deposition or sputtering, and then the surface electrode 9 is patterned into a desired shape. Perform the process. At this time, as shown in FIG. 5D, the Schottky electrode 4 partially lifted due to the presence of the particles 20, and the one where the pinhole 21 is formed in the Schottky electrode 4, In some cases, the constituent material of the surface electrode 9 may enter and be in contact with the n ⁻ -type layer 2 serving as a base. The surface electrode 9 n in the manufacturing stage ^- even not in contact with the mold layer 2, the migration of the material of the surface electrode 9 due to a load by using a surface electrode 9 n ^- -type layer 2 in contact There are things to do.

However, the defect caused only by the surface electrode 9 coming into contact with the n ⁻ -type layer 2 cannot be revealed by the annealing process performed after the formation of the bonding electrode 8 described above. However, the characteristic indicating a defective chip does not appear. For this reason, an annealing process (second annealing process) is performed even after the surface electrode 9 is formed, thereby revealing a defective portion and causing a characteristic indicating a defective chip to appear.

Specifically, the change in the characteristics due to the surface electrode 9 occurs when the surface electrode 9 comes into contact with the n ⁻ -type layer 2 due to migration of the constituent material of the surface electrode 9 based on the load due to use. Annealing treatment is performed at a temperature at which the constituent material 9 causes migration. In the case where the surface electrode 9 is made of Al, migration can be caused, for example, by performing an annealing process at a temperature of 100 ° C. or higher. As a result, a defective portion can be made obvious and a characteristic indicating a defective chip can be exhibited. However, if the annealing process is performed at a temperature higher than the evaporation temperature of the constituent material of the surface electrode 9, the surface electrode 9 will not function. For example, when the surface electrode 9 is made of Al, the annealing process is performed at a temperature of 650 ° C. or lower. Like to do.

Thereafter, although not shown, an ohmic electrode 5 is formed by forming a metal layer made of nickel, titanium, molybdenum, gold or the like on the back surface 1b side of the n ⁺ type substrate 1. Thereafter, an inspection voltage is applied between the surface electrode 9 and the ohmic electrode 5, and a forward voltage and a reverse voltage are applied between the anode and the cathode, thereby performing a good / bad determination process. In other words, the characteristics indicating the relationship between the forward voltage and the forward current when the forward voltage is applied, and the characteristics indicating the relationship between the reverse voltage and the reverse current when the reverse voltage is applied are monitored. To do.

At this time, as described above, since the annealing process is performed at a temperature at which the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4 after the bonding electrode 8 is formed, the bonding electrode 8 is n ⁻ type. If it is in contact with layer 2, it will appear as a property. Further, as described above, since the annealing treatment is performed at a temperature at which the constituent material of the surface electrode 9 causes migration even after the surface electrode 9 is formed, the surface electrode 9 is in contact with the n ⁻ type layer 2. If it does, it will appear as a characteristic. For this reason, in the manufacturing stage, with respect to a chip that can become a defective chip based on the load due to use, the characteristics of the defective chip can be made to appear in the good / bad determination process. Accordingly, if the characteristics shown by the solid lines in FIGS. 10A and 10B are adopted as good chips, and the characteristics shown by the broken lines are selected as defective chips, it is determined in the manufacturing stage in the future. It is also possible to remove chips that can be defective chips.

  In this way, the manufacturing process of the SiC semiconductor device including the SBD 10 shown in FIG. 1 is completed, and the SiC semiconductor device is completed.

  As described above, in the manufacturing method of the SiC semiconductor device of this embodiment, after the bonding electrode 8 is formed, the annealing process is performed at a temperature at which the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4. Yes. Even after the surface electrode 9 is formed, the annealing process is performed at a temperature at which the constituent material of the surface electrode 9 causes migration. As a result, whether or not element destruction will occur in the future can be made apparent at the manufacturing stage, and in the process of determining good or defective, it is possible to remove defective chips and select only good chips.

(Second Embodiment)
A second embodiment of the present invention will be described. The present embodiment is a junction barrier Schottky diode (hereinafter referred to as JBS) by adding a p-type layer to the SBD 10 with respect to the first embodiment, and is otherwise the same as the first embodiment. Therefore, only a different part from 1st Embodiment is demonstrated.

As shown in FIG. 7, the Schottky electrode 4 and the inner side (inner peripheral side) of the p-type RESURF layer 6 located closest to the cell part among the parts constituting the termination structure, A plurality of p-type layers 30 configured to be in contact with each other are formed. As shown in FIG. 8, the plurality of p-type layers 30 have the same width and are arranged in stripes at equal intervals. Each p-type layer 30 is laid out symmetrically at the contact point of the Schottky electrode 4 with the n ⁻ -type layer 2, and the outermost one is arranged away from the RESURF layer 6. However, the layout may overlap with the RESURF layer 6. Such a p-type layer 30 is composed of, for example, an impurity concentration of about 5 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ , and the interval between the p-type layers 30 is about 0.3 to 5.0 μm and has a width. The depth is about 0.3 to 5.0 μm and the depth is about 0.3 to 1.0 μm.

With such a structure, the SiC semiconductor device made into JBS is configured by providing the p-type layer 30 with respect to the SBD 10. Such an SiC semiconductor device also basically performs the same operation as that of the SiC semiconductor device of the first embodiment, but with respect to the outer peripheral region, a plurality of p-type layers disposed below the Schottky electrode 4 when turned off. n 30 ^- by extending toward the mold layer 2 depletion, n sandwiched p-type layer 30 ^- -type layer 2 is completely depleted. For this reason, the effect that it becomes possible to reduce the leakage current at the time of reverse voltage application is also acquired.

  The manufacturing method described in the first embodiment can also be applied to such a method of manufacturing a SiC semiconductor device. That is, after the bonding electrode 8 is formed, annealing is performed at a temperature at which the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4. Even after the surface electrode 9 is formed, annealing is performed at a temperature at which the constituent material of the surface electrode 9 causes migration. Thereby, it is possible to obtain the same effect as in the first embodiment. As a method of manufacturing the SiC semiconductor device of this embodiment, a manufacturing process of the p-type layer 30 is added to the first embodiment, but the p-type RESURF layer 6 and the p-type guard ring layer 7 are formed. At this time, the p-type layer 30 may be formed at the same time. Of course, when the p-type RESURF layer 6 or the p-type guard ring layer 7 and the p-type layer 30 are formed at different concentrations or different depths, they may be formed by separate steps.

(Other embodiments)
In each of the above embodiments, the annealing material is performed at a temperature at which the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4 after the bonding electrode 8 is formed, and the constituent material of the surface electrode 9 migrates after the surface electrode 9 is formed. The annealing process performed at the temperature to raise was implemented as a different process. However, these may be performed simultaneously after the surface electrode 9 is formed. However, in this case, it is necessary to make the temperature higher than the temperature at which the barrier height of the bonding electrode 8 is lower than that of the Schottky electrode 4 and lower than the evaporation temperature of the surface electrode 9.

In the embodiments described above, the first conductivity type is n-type, the second conductivity type is p-type, the main surface 1a of the n ⁺ -type substrate 1 n ^- -type layer 2 is formed, n ^- against the mold layer 2 The case where the present invention is applied to the SiC semiconductor device in which the p-type RESURF layer 6 and the like are formed has been described. However, the present invention can also be applied to a SiC semiconductor device in which the conductivity type of each part is reversed so that the first conductivity type is p-type and the second conductivity type is n-type.

1 n ⁺ type substrate 1a main surface 1b back surface 2 n ⁻ type layer 3 insulating film 4 Schottky electrode 5 ohmic electrode 6 p-type RESURF layer 7 p-type guard ring layer 8 bonding electrode 9 surface electrode 10 SBD
30 p-type layer

Claims (6)

A silicon carbide semiconductor substrate is formed by forming a first conductivity type layer (2) on the main surface of a substrate (1) made of silicon carbide of the first conductivity type having a main surface (1a) and a back surface (1b). (1, 2) are configured, and a Schottky electrode (4) that is brought into Schottky contact with the surface of the first conductivity type layer on the surface of the first conductivity type layer; A bonding electrode (8) as a formed barrier layer and a surface electrode (9) constituting a pad formed on the surface of the bonding electrode are provided, and an ohmic formed on the back surface of the substrate A silicon carbide semiconductor device having a Schottky barrier diode (10) comprising an electrode (5),
Forming the bonding electrode on the surface of the Schottky electrode;
Performing a first annealing process at a temperature at which the barrier height of the bonding electrode is lower than that of the Schottky electrode after the bonding electrode is formed;
Forming the surface electrode on the surface of the bonding electrode;
After formation of the surface electrode, and a second annealing process the material of the surface electrodes is carried out at a temperature that causes the migration,
A step of selecting a good chip and a defective chip by performing good / bad determination based on characteristics of the Schottky barrier diode after the first and second annealing treatments. A method for manufacturing a silicon semiconductor device. In the step of forming the bonding electrode, the bonding electrode is made of Ti,
2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in the step of performing the first annealing treatment, a temperature of the first annealing treatment is set to 500 ° C. or more and 1100 ° C. or less. In the step of forming the bonding electrode, the bonding electrode is made of Ni,
2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein, in the step of performing the first annealing treatment, a temperature of the first annealing treatment is set to 700 ° C. or more and 1100 ° C. or less. In the step of forming the surface electrode, the surface electrode is made of Al,
4. The silicon carbide semiconductor device according to claim 1, wherein in the step of performing the second annealing treatment, a temperature of the second annealing treatment is set to 100 ° C. or more and 650 ° C. or less. 5. Production method.   5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of forming the surface electrode is performed after the step of performing the first annealing treatment.   The junction barrier Schottky diode is formed by forming a second conductivity type layer (30) in a surface layer portion of the first conductivity type layer before forming the Schottky electrode. A method for manufacturing a silicon carbide semiconductor device according to any one of 1 to 5.

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