TW202228284A - Semiconductor strcuture - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 138
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- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
Description
本發明是有關於一種半導體結構,且特別是有關於一種具有浮體場環(floating field ring,FFR)的半導體結構。The present invention relates to a semiconductor structure, and more particularly, to a semiconductor structure having a floating field ring (FFR).
一些半導體元件(如,功率元件)在主接面(main junction)的最邊緣處容易產生崩潰(breakdown)現象。目前的解決方式是藉由環繞半導體元件區的浮體場環來提升半導體元件的崩潰電壓,以防止崩潰現象產生。然而,如何更進一步提升半導體元件的崩潰電壓為目前持續努力的目標。Some semiconductor devices (eg, power devices) are prone to a breakdown phenomenon at the most edge of the main junction. The current solution is to increase the breakdown voltage of the semiconductor element by means of a floating body field ring surrounding the semiconductor element region, so as to prevent the breakdown phenomenon. However, how to further improve the breakdown voltage of the semiconductor element is the goal of continuous efforts at present.
本發明提供一種半導體結構,其可提升半導體元件的崩潰電壓。The present invention provides a semiconductor structure which can increase the breakdown voltage of a semiconductor device.
本發明提出一種半導體結構,包括基底、半導體層、浮體場環結構與嵌入式摻雜區(embedded doped region)。半導體層設置在基底上。半導體層具有第一導電型。浮體場環結構位在半導體層中。浮體場環結構包括至少一個浮體場環。浮體場環具有第二導電型。嵌入式摻雜區位在浮體場環結構下方的半導體層中,且連接於浮體場環結構。嵌入式摻雜區具有第二導電型。The present invention provides a semiconductor structure including a substrate, a semiconductor layer, a floating body field ring structure and an embedded doped region. The semiconductor layer is disposed on the substrate. The semiconductor layer has the first conductivity type. The floating body field ring structure is located in the semiconductor layer. The floating body field ring structure includes at least one floating body field ring. The floating body field ring has a second conductivity type. The embedded doping region is located in the semiconductor layer below the floating body field ring structure and is connected to the floating body field ring structure. The embedded doped region has a second conductivity type.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區可位在整個浮體場環結構的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doped region may be located directly under the entire floating body field ring structure.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區可位在部分浮體場環結構的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doped region may be located directly under part of the floating body field ring structure.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區可僅位在整個浮體場環結構的一側。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doped region may be located only on one side of the entire floating body field ring structure.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區的數量可為一個。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the number of embedded doped regions may be one.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區的數量可為多個。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the number of the embedded doped regions may be multiple.
依照本發明的一實施例所述,在上述半導體結構中,基底可包括半導體元件區。浮體場環結構可環繞半導體元件區。半導體結構更可包括半導體元件。半導體元件可包括第一摻雜區與第二摻雜區。第一摻雜區位在半導體元件區的半導體層中。第一摻雜區可具有第二導電型。第二摻雜區位在基底中,且鄰近於半導體層。第二摻雜區可具有第一導電型。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the substrate may include a semiconductor element region. The floating body field ring structure may surround the semiconductor device region. The semiconductor structure may further include semiconductor elements. The semiconductor element may include a first doped region and a second doped region. The first doped region is located in the semiconductor layer of the semiconductor element region. The first doped region may have the second conductivity type. The second doped region is located in the substrate and adjacent to the semiconductor layer. The second doped region may have the first conductivity type.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區更可位在第一摻雜區的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doping region may be located directly below the first doping region.
依照本發明的一實施例所述,在上述半導體結構中,半導體元件更可包括井區。井區位在半導體元件區的半導體層中。井區可具有第二導電型。第一摻雜區位在井區中。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the semiconductor element may further include a well region. The well region is located in the semiconductor layer of the semiconductor element region. The well region may have the second conductivity type. The first doped region is located in the well region.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區更可位在井區的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doped region may be located directly below the well region.
依照本發明的一實施例所述,在上述半導體結構中,半導體元件更可包括第三摻雜區。第三摻雜區位在浮體場環結構的遠離半導體元件區的一側的半導體層中。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the semiconductor element may further include a third doped region. The third doping region is located in the semiconductor layer on the side of the floating body field ring structure away from the semiconductor element region.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區更位在第三摻雜區的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doping region is further located directly below the third doping region.
依照本發明的一實施例所述,在上述半導體結構中,更可包括第四摻雜區。第四摻雜區位在浮體場環結構與第三摻雜區之間的半導體層中。第四摻雜區可具有第一導電型。According to an embodiment of the present invention, the above-mentioned semiconductor structure may further include a fourth doped region. The fourth doped region is located in the semiconductor layer between the floating body field ring structure and the third doped region. The fourth doped region may have the first conductivity type.
依照本發明的一實施例所述,在上述半導體結構中,嵌入式摻雜區更可位在第四摻雜區的正下方。According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doping region may be located directly below the fourth doping region.
基於上述,在本發明所提出的半導體結構中,由於嵌入式摻雜區位在浮體場環結構下方的半導體層中,且連接於浮體場環結構,因此可擴大空乏區的範圍,進而提升半導體元件的崩潰電壓。另一方面,由於本發明所提出的半導體結構可提升半導體元件的崩潰電壓,因此即使縮小浮體場環結構的面積,也可以維持與現有技術相同的崩潰電壓,且可具有更小的元件尺寸。Based on the above, in the semiconductor structure proposed by the present invention, since the embedded doping region is located in the semiconductor layer below the floating body field ring structure and connected to the floating body field ring structure, the range of the depletion region can be enlarged, thereby improving the breakdown voltage of semiconductor components. On the other hand, since the semiconductor structure proposed in the present invention can increase the breakdown voltage of the semiconductor device, even if the area of the floating body field ring structure is reduced, it can maintain the same breakdown voltage as the prior art, and can have a smaller device size .
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.
圖1為根據本發明一實施例的半導體結構的上視圖。在圖1中,省略圖2A中的部分構件,以清楚地描述圖1中的構件之間的配置關係。圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。圖2B至圖2G為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。在圖2A至圖2G中,相同或相似的構件以相同的符號表示。FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. In FIG. 1 , some components in FIG. 2A are omitted in order to clearly describe the arrangement relationship among the components in FIG. 1 . FIG. 2A is a cross-sectional view of the semiconductor structure along the section line I-I' in FIG. 1 . 2B to 2G are cross-sectional views of the semiconductor structure along the section line I-I' in FIG. 1 according to other embodiments of the present invention. In Figures 2A to 2G, the same or similar components are denoted by the same symbols.
請參照圖1與圖2A,半導體結構10包括基底100、半導體層102、浮體場環結構104與嵌入式摻雜區106。基底100可為半導體基底,如矽基底。此外,基底100可包括半導體元件區R。Referring to FIG. 1 and FIG. 2A , the
半導體層102設置在基底100上。半導體層102的材料例如是磊晶矽等半導體材料。半導體層102具有第一導電型(如,N型)。此外,第一導電型與第二導電型可為不同導電型。第一導電型與第二導電型可分別為N型與P型中的一者與另一者。在本實施例中,第一導電型是以N型為例,且第二導電型是以P型為例,但本發明並不以此為限。在另一些實施例中,第一導電型可為P型,且第二導電型可為N型。The
浮體場環結構104位在半導體層102中。浮體場環結構104可環繞半導體元件區R(圖1)。浮體場環結構104包括至少一個浮體場環104a。在本實施例中,浮體場環104a的數量是以多個為例,但本發明並不以此為限。在另一些實施例中,浮體場環104a的數量可為一個。浮體場環104a具有第二導電型(如,P型)。舉例來說,浮體場環104a可為第二導電型(如,P型)的摻雜區。另外,多個浮體場環104a的寬度W可彼此相同或不同。The floating body
嵌入式摻雜區106位在浮體場環結構104下方的半導體層102中,且連接於浮體場環結構104。嵌入式摻雜區106具有第二導電型(如,P型)。嵌入式摻雜區106可用於擴大空乏區的範圍,進而提升崩潰電壓。The embedded doped
此外,半導體結構10更可包括半導體元件108。半導體元件108可為主動元件,如功率元件。在一些實施例中,半導體元件108例如是金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor,MOSFET)、二極體(diode)或絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)等。In addition, the
半導體元件108可包括摻雜區110與摻雜區112。摻雜區110位在半導體元件區R的半導體層102中。摻雜區110可具有第二導電型(如,P型)。摻雜區112位在基底100中,且鄰近於半導體層102。在一些實施例中,摻雜區112可均勻分布在整個基底100中。摻雜區112可具有第一導電型(如,N型)。The
此外,半導體元件108更可包括井區114與摻雜區116中的至少一者。井區114位在半導體元件區R的半導體層102中。井區114可具有第二導電型(如,P型)。摻雜區110位在井區114中。另外,摻雜區110的摻雜濃度可大於浮體場環104a的摻雜濃度、嵌入式摻雜區106的摻雜濃度與井區114的摻雜濃度。摻雜區116位在浮體場環結構104的遠離半導體元件區R的一側的半導體層102中。另一方面,半導體元件108更可依據元件類型包括其他所需的構件,於此省略其說明。In addition, the
在一些實施例中,依據半導體元件108的類型,摻雜區116可為第一導電型(如,N型)或第二導電型(如,P型)。在一些實施例中,在摻雜區116為第一導電型(如,N型)的情況下,摻雜區116可耦接於摻雜區112,但本發明並不以此為限。In some embodiments, the doped
另外,半導體結構10更可包括摻雜區118。摻雜區118位在浮體場環結構104與摻雜區116之間的半導體層102中。摻雜區118可具有第一導電型(如,N型)。摻雜區118可作為通道終止區(channel stop region)。In addition, the
在本實施例中,如圖2A所示,嵌入式摻雜區106可位在整個浮體場環結構104的正下方,且更可位在摻雜區110的正下方、井區114的正下方、摻雜區118的正下方與摻雜區116的正下方,但本發明並不以此為限。在另一些實施例中,嵌入式摻雜區106可不位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方。此外,嵌入式摻雜區106更可連接於井區114、摻雜區118與摻雜區116,但本發明並不以此為限。在另一些實施例中,嵌入式摻雜區106可不連接於井區114、摻雜區118及/或摻雜區116。In this embodiment, as shown in FIG. 2A , the embedded doped
在另一些實施例中,如圖2E所示,嵌入式摻雜區106可不位在浮體場環結構104的正下方。在另一些實施例中,如圖2B、圖2D、圖2E與圖2F所示,嵌入式摻雜區106可不位在摻雜區110的正下方。在另一些實施例中,如圖2B、圖2D、圖2E與圖2F所示,嵌入式摻雜區106可不位在摻雜區114的正下方。在另一些實施例中,如圖2B至圖2F所示,嵌入式摻雜區106可不位在摻雜區116的正下方。在另一些實施例中,如圖2C至圖2F所示,嵌入式摻雜區106可不位在摻雜區118的正下方。In other embodiments, as shown in FIG. 2E , the embedded doped
在另一些實施例中,嵌入式摻雜區106可僅位在整個浮體場環結構104的一側。舉例來說,如圖2E所示,嵌入式摻雜區106可僅位在整個浮體場環結構104的一側,且遠離半導體元件區R,但本發明並不以此為限。在另一些實施例中,嵌入式摻雜區106可僅位在整個浮體場環結構104的一側,且靠近半導體元件區R。In other embodiments, the embedded doped
此外,如圖2A至圖2D所示,嵌入式摻雜區106可位在整個浮體場環結構104的正下方,亦即嵌入式摻雜區106可位在每個浮體場環104a的正下方,但本發明並不以此為限。在另一些實施例中,如圖2F所示,嵌入式摻雜區106可位在部分浮體場環結構104的正下方。In addition, as shown in FIGS. 2A to 2D , the embedded
另外,如圖2A至圖2F所示,嵌入式摻雜區106的數量是以一個為例,但本發明並不以此為限。在另一些實施例中,如圖2G所示,嵌入式摻雜區106可為多個。在圖2G中,雖然多個嵌入式摻雜區106分別位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方,但本發明並不以此為限。在一些實施例中,多個嵌入式摻雜區106可分別不位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方。In addition, as shown in FIGS. 2A to 2F , the number of the embedded
基於上述實施例可知,在半導體結構10中,由於嵌入式摻雜區106位在浮體場環結構104下方的半導體層102中,且連接於浮體場環結構104,因此可擴大空乏區的範圍,進而提升半導體元件108的崩潰電壓。另一方面,由於半導體結構10可提升半導體元件108的崩潰電壓,因此即使縮小浮體場環結構104的面積,也可以維持與現有技術相同的崩潰電壓,且可具有更小的元件尺寸。此外,當嵌入式摻雜區106的面積越大時(如,圖2A所示),提升半導體元件108的崩潰電壓的效果越好。Based on the above embodiments, in the
綜上所述,在上述實施例的半導體結構中,可藉由位在浮體場環結構下方且連接於浮體場環結構的嵌入式摻雜區來擴大空乏區的範圍,因此可提升半導體元件的崩潰電壓。To sum up, in the semiconductor structure of the above-mentioned embodiments, the range of the depletion region can be enlarged by the embedded doped region located under the floating body field ring structure and connected to the floating body field ring structure, so that the semiconductor structure can be improved. the breakdown voltage of the component.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.
10:半導體結構
100:基底
102:半導體層
104:浮體場環結構
104a:浮體場環
106:嵌入式摻雜區
108:半導體元件
110, 112, 116, 118:摻雜區
114:井區
R:半導體元件區
W:寬度
10: Semiconductor structure
100: base
102: Semiconductor layer
104: Floating body
圖1為根據本發明一實施例的半導體結構的上視圖。 圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 圖2B至圖2G為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. FIG. 2A is a cross-sectional view of the semiconductor structure along the section line I-I' in FIG. 1 . 2B to 2G are cross-sectional views of the semiconductor structure along the section line I-I' in FIG. 1 according to other embodiments of the present invention.
10:半導體結構 10: Semiconductor structure
100:基底 100: base
102:半導體層 102: Semiconductor layer
104:浮體場環結構 104: Floating body field ring structure
104a:浮體場環 104a: Floating Body Field Ring
106:嵌入式摻雜區 106: Embedded doped regions
108:半導體元件 108: Semiconductor Components
110,112,116,118:摻雜區 110, 112, 116, 118: doped regions
114:井區 114: Well District
R:半導體元件區 R: Semiconductor element area
W:寬度 W: width
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