TWI782390B - Semiconductor strcuture - Google Patents

Semiconductor strcuture Download PDF

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TWI782390B
TWI782390B TW110100854A TW110100854A TWI782390B TW I782390 B TWI782390 B TW I782390B TW 110100854 A TW110100854 A TW 110100854A TW 110100854 A TW110100854 A TW 110100854A TW I782390 B TWI782390 B TW I782390B
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doped region
semiconductor
floating body
field ring
body field
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TW110100854A
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TW202228284A (en
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徐懋騰
李世平
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力晶積成電子製造股份有限公司
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Priority to CN202110167922.1A priority patent/CN114744018A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

Abstract

A semiconductor structure including a substrate, a semiconductor layer, a floating field ring structure, and an embedded doped region is provided. The semiconductor layer is disposed on the substrate. The semiconductor layer has a first conductive type. The floating field ring structure is located in the semiconductor layer. The floating field ring structure includes at least one floating field ring. The floating body field ring has a second conductive type. The embedded doped region is located in the semiconductor layer under the floating field ring structure and connected to the floating field ring structure. The embedded doped region has the second conductive type.

Description

半導體結構semiconductor structure

本發明是有關於一種半導體結構，且特別是有關於一種具有浮體場環(floating field ring，FFR)的半導體結構。 The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure having a floating field ring (FFR).

一些半導體元件(如，功率元件)在主接面(main junction)的最邊緣處容易產生崩潰(breakdown)現象。目前的解決方式是藉由環繞半導體元件區的浮體場環來提升半導體元件的崩潰電壓，以防止崩潰現象產生。然而，如何更進一步提升半導體元件的崩潰電壓為目前持續努力的目標。 Some semiconductor devices (eg, power devices) are prone to breakdown at the edge of the main junction. The current solution is to increase the breakdown voltage of the semiconductor element by means of a floating field ring surrounding the semiconductor element region, so as to prevent the breakdown phenomenon. However, how to further increase the breakdown voltage of semiconductor devices is the goal of ongoing efforts.

本發明提供一種半導體結構，其可提升半導體元件的崩潰電壓。 The invention provides a semiconductor structure, which can increase the breakdown voltage of semiconductor elements.

本發明提出一種半導體結構，包括基底、半導體層、浮體場環結構與嵌入式摻雜區(embedded doped region)。半導體層設置在基底上。半導體層具有第一導電型。浮體場環結構位在半導體層中。浮體場環結構包括至少一個浮體場環。浮體場環具有第 二導電型。嵌入式摻雜區位在浮體場環結構下方的半導體層中，且連接於浮體場環結構。嵌入式摻雜區具有第二導電型。 The present invention provides a semiconductor structure, including a substrate, a semiconductor layer, a floating field ring structure and an embedded doped region. The semiconductor layer is disposed on the substrate. The semiconductor layer has a first conductivity type. The floating body field ring structure is located in the semiconductor layer. The floating body field ring structure includes at least one floating body field ring. The floating field ring has the Two conductivity types. The embedded doping region is located in the semiconductor layer under the floating body field ring structure and connected to the floating body field ring structure. The embedded doped region has the second conductivity type.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區可位在整個浮體場環結構的正下方。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region may be located directly under the entire floating body field ring structure.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區可位在部分浮體場環結構的正下方。 According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the embedded doped region may be located directly under a part of the floating body field ring structure.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區可僅位在整個浮體場環結構的一側。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region may be located only on one side of the entire floating body field ring structure.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區的數量可為一個。 According to an embodiment of the present invention, in the above-mentioned semiconductor structure, the number of embedded doped regions may be one.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區的數量可為多個。 According to an embodiment of the present invention, in the above semiconductor structure, the number of embedded doped regions may be multiple.

依照本發明的一實施例所述，在上述半導體結構中，基底可包括半導體元件區。浮體場環結構可環繞半導體元件區。半導體結構更可包括半導體元件。半導體元件可包括第一摻雜區與第二摻雜區。第一摻雜區位在半導體元件區的半導體層中。第一摻雜區可具有第二導電型。第二摻雜區位在基底中，且鄰近於半導體層。第二摻雜區可具有第一導電型。 According to an embodiment of the present invention, in the above semiconductor structure, the base may include a semiconductor element region. The floating body field ring structure can surround the semiconductor element region. The semiconductor structure may further include semiconductor elements. The semiconductor device may include a first doped region and a second doped region. The first doped region is located in the semiconductor layer of the semiconductor element region. The first doped region may have a second conductivity type. The second doped region is located in the base and adjacent to the semiconductor layer. The second doped region may have the first conductivity type.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區更可位在第一摻雜區的正下方。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region can be located directly under the first doped region.

依照本發明的一實施例所述，在上述半導體結構中，半導體元件更可包括井區。井區位在半導體元件區的半導體層中。 井區可具有第二導電型。第一摻雜區位在井區中。 According to an embodiment of the present invention, in the above semiconductor structure, the semiconductor device may further include a well region. The well region is located in the semiconductor layer in the semiconductor element region. The well region may have a second conductivity type. The first doped region is in the well region.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區更可位在井區的正下方。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region can be located directly under the well region.

依照本發明的一實施例所述，在上述半導體結構中，半導體元件更可包括第三摻雜區。第三摻雜區位在浮體場環結構的遠離半導體元件區的一側的半導體層中。 According to an embodiment of the present invention, in the above semiconductor structure, the semiconductor element may further include a third doped region. The third doping region is located in the semiconductor layer on the side of the floating body field ring structure away from the semiconductor element region.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區更位在第三摻雜區的正下方。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region is located directly below the third doped region.

依照本發明的一實施例所述，在上述半導體結構中，更可包括第四摻雜區。第四摻雜區位在浮體場環結構與第三摻雜區之間的半導體層中。第四摻雜區可具有第一導電型。 According to an embodiment of the present invention, the above semiconductor structure may further include a fourth doped region. The fourth doping region is located in the semiconductor layer between the floating body field ring structure and the third doping region. The fourth doped region may have the first conductivity type.

依照本發明的一實施例所述，在上述半導體結構中，嵌入式摻雜區更可位在第四摻雜區的正下方。 According to an embodiment of the present invention, in the above semiconductor structure, the embedded doped region can be located directly under the fourth doped region.

基於上述，在本發明所提出的半導體結構中，由於嵌入式摻雜區位在浮體場環結構下方的半導體層中，且連接於浮體場環結構，因此可擴大空乏區的範圍，進而提升半導體元件的崩潰電壓。另一方面，由於本發明所提出的半導體結構可提升半導體元件的崩潰電壓，因此即使縮小浮體場環結構的面積，也可以維持與現有技術相同的崩潰電壓，且可具有更小的元件尺寸。 Based on the above, in the semiconductor structure proposed by the present invention, since the embedded doping region is in the semiconductor layer below the floating body field ring structure and connected to the floating body field ring structure, the range of the depletion region can be enlarged, thereby improving The breakdown voltage of a semiconductor element. On the other hand, since the semiconductor structure proposed by the present invention can increase the breakdown voltage of the semiconductor element, even if the area of the floating body field ring structure is reduced, the same breakdown voltage as the prior art can be maintained, and the element size can be smaller .

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

10:半導體結構 10:Semiconductor structure

100:基底 100: base

102:半導體層 102: Semiconductor layer

104:浮體場環結構 104: Floating body field ring structure

104a:浮體場環 104a: Floating body field ring

106:嵌入式摻雜區 106: Embedded doping area

108:半導體元件 108: Semiconductor components

110,112,116,118:摻雜區 110, 112, 116, 118: doped regions

114:井區 114: well area

R:半導體元件區 R: semiconductor element area

W:寬度 W: width

圖1為根據本發明一實施例的半導體結構的上視圖。 FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention.

圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 2A is a cross-sectional view of the semiconductor structure along the line I-I' in FIG. 1 .

圖2B至圖2G為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。 2B to 2G are cross-sectional views of semiconductor structures along the line I-I' in FIG. 1 according to other embodiments of the present invention.

圖1為根據本發明一實施例的半導體結構的上視圖。在圖1中，省略圖2A中的部分構件，以清楚地描述圖1中的構件之間的配置關係。圖2A為沿著圖1中的I-I’剖面線的半導體結構的剖面圖。圖2B至圖2G為本發明另一些實施例的沿著圖1中的I-I’剖面線的半導體結構的剖面圖。在圖2A至圖2G中，相同或相似的構件以相同的符號表示。 FIG. 1 is a top view of a semiconductor structure according to an embodiment of the present invention. In FIG. 1 , some components in FIG. 2A are omitted to clearly describe the configuration relationship among the components in FIG. 1 . 2A is a cross-sectional view of the semiconductor structure along the line I-I' in FIG. 1 . 2B to 2G are cross-sectional views of semiconductor structures along the line I-I' in FIG. 1 according to other embodiments of the present invention. In FIGS. 2A to 2G , the same or similar components are denoted by the same symbols.

請參照圖1與圖2A，半導體結構10包括基底100、半導體層102、浮體場環結構104與嵌入式摻雜區106。基底100可為半導體基底，如矽基底。此外，基底100可包括半導體元件區R。 Referring to FIG. 1 and FIG. 2A , the semiconductor structure 10 includes a substrate 100 , a semiconductor layer 102 , a floating body field ring structure 104 and an embedded doped region 106 . The substrate 100 can be a semiconductor substrate, such as a silicon substrate. In addition, the substrate 100 may include a semiconductor element region R. Referring to FIG.

半導體層102設置在基底100上。半導體層102的材料例如是磊晶矽等半導體材料。半導體層102具有第一導電型(如，N型)。此外，第一導電型與第二導電型可為不同導電型。第一導電型與第二導電型可分別為N型與P型中的一者與另一者。在本實施例中，第一導電型是以N型為例，且第二導電型是以P型為 例，但本發明並不以此為限。在另一些實施例中，第一導電型可為P型，且第二導電型可為N型。 The semiconductor layer 102 is disposed on the substrate 100 . The material of the semiconductor layer 102 is, for example, semiconductor materials such as epitaxial silicon. The semiconductor layer 102 has a first conductivity type (eg, N type). In addition, the first conductivity type and the second conductivity type may be different conductivity types. The first conductivity type and the second conductivity type may be one and the other of N type and P type, respectively. In this embodiment, the first conductivity type is N-type as an example, and the second conductivity type is P-type as an example. example, but the present invention is not limited thereto. In other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type.

浮體場環結構104位在半導體層102中。浮體場環結構104可環繞半導體元件區R(圖1)。浮體場環結構104包括至少一個浮體場環104a。在本實施例中，浮體場環104a的數量是以多個為例，但本發明並不以此為限。在另一些實施例中，浮體場環104a的數量可為一個。浮體場環104a具有第二導電型(如，P型)。舉例來說，浮體場環104a可為第二導電型(如，P型)的摻雜區。另外，多個浮體場環104a的寬度W可彼此相同或不同。 The floating body field ring structure 104 is located in the semiconductor layer 102 . The floating body field ring structure 104 can surround the semiconductor device region R ( FIG. 1 ). The floating body field ring structure 104 includes at least one floating body field ring 104a. In this embodiment, the number of floating body field rings 104a is multiple as an example, but the present invention is not limited thereto. In some other embodiments, the number of the floating body field ring 104a may be one. The floating body field ring 104a has a second conductivity type (eg, P-type). For example, the floating body field ring 104a can be a doped region of the second conductivity type (eg, P-type). In addition, the width W of the plurality of floating body field rings 104a may be the same or different from each other.

嵌入式摻雜區106位在浮體場環結構104下方的半導體層102中，且連接於浮體場環結構104。嵌入式摻雜區106具有第二導電型(如，P型)。嵌入式摻雜區106可用於擴大空乏區的範圍，進而提升崩潰電壓。 The embedded doped region 106 is located in the semiconductor layer 102 below the floating body field ring structure 104 and connected to the floating body field ring structure 104 . The embedded doped region 106 has a second conductivity type (eg, P type). The embedded doped region 106 can be used to expand the range of the depletion region, thereby increasing the breakdown voltage.

此外，半導體結構10更可包括半導體元件108。半導體元件108可為主動元件，如功率元件。在一些實施例中，半導體元件108例如是金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor，MOSFET)、二極體(diode)或絕緣閘雙極電晶體(insulated gate bipolar transistor，IGBT)等。 In addition, the semiconductor structure 10 may further include a semiconductor element 108 . The semiconductor device 108 can be an active device, such as a power device. In some embodiments, the semiconductor element 108 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode (diode) or an insulated gate bipolar transistor (insulated gate bipolar). transistor, IGBT), etc.

半導體元件108可包括摻雜區110與摻雜區112。摻雜區110位在半導體元件區R的半導體層102中。摻雜區110可具有第二導電型(如，P型)。摻雜區112位在基底100中，且鄰近於半導 體層102。在一些實施例中，摻雜區112可均勻分布在整個基底100中。摻雜區112可具有第一導電型(如，N型)。 The semiconductor device 108 can include a doped region 110 and a doped region 112 . The doped region 110 is located in the semiconductor layer 102 of the semiconductor device region R. As shown in FIG. The doped region 110 may have a second conductivity type (eg, P type). The doped region 112 is located in the substrate 100 and is adjacent to the semiconductor body layer 102 . In some embodiments, the doped regions 112 may be uniformly distributed throughout the substrate 100 . The doped region 112 may have a first conductivity type (eg, N type).

此外，半導體元件108更可包括井區114與摻雜區116中的至少一者。井區114位在半導體元件區R的半導體層102中。井區114可具有第二導電型(如，P型)。摻雜區110位在井區114中。另外，摻雜區110的摻雜濃度可大於浮體場環104a的摻雜濃度、嵌入式摻雜區106的摻雜濃度與井區114的摻雜濃度。摻雜區116位在浮體場環結構104的遠離半導體元件區R的一側的半導體層102中。另一方面，半導體元件108更可依據元件類型包括其他所需的構件，於此省略其說明。 In addition, the semiconductor device 108 may further include at least one of the well region 114 and the doped region 116 . The well region 114 is located in the semiconductor layer 102 of the semiconductor device region R. As shown in FIG. The well region 114 may have a second conductivity type (eg, P type). The doped region 110 is located in the well region 114 . In addition, the doping concentration of the doping region 110 may be greater than the doping concentration of the floating body field ring 104 a , the doping concentration of the embedded doping region 106 and the doping concentration of the well region 114 . The doped region 116 is located in the semiconductor layer 102 on the side of the floating body field ring structure 104 away from the semiconductor device region R. On the other hand, the semiconductor device 108 may further include other required components according to the device type, and the description thereof is omitted here.

在一些實施例中，依據半導體元件108的類型，摻雜區116可為第一導電型(如，N型)或第二導電型(如，P型)。在一些實施例中，在摻雜區116為第一導電型(如，N型)的情況下，摻雜區116可耦接於摻雜區112，但本發明並不以此為限。 In some embodiments, according to the type of the semiconductor device 108 , the doped region 116 can be of the first conductivity type (eg, N-type) or the second conductivity type (eg, P-type). In some embodiments, if the doped region 116 is of the first conductivity type (eg, N type), the doped region 116 can be coupled to the doped region 112 , but the invention is not limited thereto.

另外，半導體結構10更可包括摻雜區118。摻雜區118位在浮體場環結構104與摻雜區116之間的半導體層102中。摻雜區118可具有第一導電型(如，N型)。摻雜區118可作為通道終止區(channel stop region)。 In addition, the semiconductor structure 10 may further include a doped region 118 . The doped region 118 is located in the semiconductor layer 102 between the floating body field ring structure 104 and the doped region 116 . The doped region 118 may have a first conductivity type (eg, N type). The doped region 118 can serve as a channel stop region.

在本實施例中，如圖2A所示，嵌入式摻雜區106可位在整個浮體場環結構104的正下方，且更可位在摻雜區110的正下方、井區114的正下方、摻雜區118的正下方與摻雜區116的正下方，但本發明並不以此為限。在另一些實施例中，嵌入式摻雜 區106可不位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方。此外，嵌入式摻雜區106更可連接於井區114、摻雜區118與摻雜區116，但本發明並不以此為限。在另一些實施例中，嵌入式摻雜區106可不連接於井區114、摻雜區118及/或摻雜區116。 In this embodiment, as shown in FIG. 2A , the embedded doped region 106 can be located directly below the entire floating body field ring structure 104 , and can be located directly below the doped region 110 and directly below the well region 114 directly below the doped region 118 and directly below the doped region 116 , but the invention is not limited thereto. In other embodiments, embedded doping The region 106 may not be directly below the floating body field ring structure 104 , directly below the doped region 110 , directly below the well region 114 , directly below the doped region 118 and/or directly below the doped region 116 . In addition, the embedded doped region 106 can be further connected to the well region 114 , the doped region 118 and the doped region 116 , but the invention is not limited thereto. In other embodiments, the embedded doped region 106 may not be connected to the well region 114 , the doped region 118 and/or the doped region 116 .

在另一些實施例中，如圖2E所示，嵌入式摻雜區106可不位在浮體場環結構104的正下方。在另一些實施例中，如圖2B、圖2D、圖2E與圖2F所示，嵌入式摻雜區106可不位在摻雜區110的正下方。在另一些實施例中，如圖2B、圖2D、圖2E與圖2F所示，嵌入式摻雜區106可不位在井區114的正下方。在另一些實施例中，如圖2B至圖2F所示，嵌入式摻雜區106可不位在摻雜區116的正下方。在另一些實施例中，如圖2C至圖2F所示，嵌入式摻雜區106可不位在摻雜區118的正下方。 In other embodiments, as shown in FIG. 2E , the embedded doped region 106 may not be directly under the floating body field ring structure 104 . In some other embodiments, as shown in FIG. 2B , FIG. 2D , FIG. 2E and FIG. 2F , the embedded doped region 106 may not be directly under the doped region 110 . In some other embodiments, as shown in FIG. 2B , FIG. 2D , FIG. 2E and FIG. 2F , the embedded doped region 106 may not be located directly under the well region 114 . In some other embodiments, as shown in FIG. 2B to FIG. 2F , the embedded doped region 106 may not be directly below the doped region 116 . In other embodiments, as shown in FIG. 2C to FIG. 2F , the embedded doped region 106 may not be directly below the doped region 118 .

在另一些實施例中，嵌入式摻雜區106可僅位在整個浮體場環結構104的一側。舉例來說，如圖2E所示，嵌入式摻雜區106可僅位在整個浮體場環結構104的一側，且遠離半導體元件區R，但本發明並不以此為限。在另一些實施例中，嵌入式摻雜區106可僅位在整個浮體場環結構104的一側，且靠近半導體元件區R。 In some other embodiments, the embedded doped region 106 may only be located on one side of the entire floating body field ring structure 104 . For example, as shown in FIG. 2E , the embedded doped region 106 may be located only on one side of the entire floating body field ring structure 104 and away from the semiconductor device region R, but the invention is not limited thereto. In some other embodiments, the embedded doped region 106 may only be located on one side of the entire floating body field ring structure 104 and be close to the semiconductor device region R. As shown in FIG.

此外，如圖2A至圖2D所示，嵌入式摻雜區106可位在整個浮體場環結構104的正下方，亦即嵌入式摻雜區106可位在 每個浮體場環104a的正下方，但本發明並不以此為限。在另一些實施例中，如圖2F所示，嵌入式摻雜區106可位在部分浮體場環結構104的正下方。 In addition, as shown in FIG. 2A to FIG. 2D , the embedded doped region 106 can be located directly under the entire floating body field ring structure 104, that is, the embedded doped region 106 can be located at directly below each floating body field ring 104a, but the present invention is not limited thereto. In other embodiments, as shown in FIG. 2F , the embedded doped region 106 may be located directly under a portion of the floating body field ring structure 104 .

另外，如圖2A至圖2F所示，嵌入式摻雜區106的數量是以一個為例，但本發明並不以此為限。在另一些實施例中，如圖2G所示，嵌入式摻雜區106可為多個。在圖2G中，雖然多個嵌入式摻雜區106分別位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方，但本發明並不以此為限。在一些實施例中，多個嵌入式摻雜區106可分別不位在浮體場環結構104的正下方、摻雜區110的正下方、井區114的正下方、摻雜區118的正下方及/或摻雜區116的正下方。 In addition, as shown in FIGS. 2A to 2F , the number of embedded doped regions 106 is taken as an example, but the present invention is not limited thereto. In other embodiments, as shown in FIG. 2G , there may be multiple embedded doped regions 106 . In FIG. 2G, although a plurality of embedded doped regions 106 are located directly below the floating body field ring structure 104, directly below the doped region 110, directly below the well region 114, directly below the doped region 118 and /or directly below the doped region 116, but the invention is not limited thereto. In some embodiments, the plurality of embedded doped regions 106 may not be located directly below the floating body field ring structure 104, directly below the doped region 110, directly below the well region 114, or directly below the doped region 118. below and/or directly below the doped region 116 .

基於上述實施例可知，在半導體結構10中，由於嵌入式摻雜區106位在浮體場環結構104下方的半導體層102中，且連接於浮體場環結構104，因此可擴大空乏區的範圍，進而提升半導體元件108的崩潰電壓。另一方面，由於半導體結構10可提升半導體元件108的崩潰電壓，因此即使縮小浮體場環結構104的面積，也可以維持與現有技術相同的崩潰電壓，且可具有更小的元件尺寸。此外，當嵌入式摻雜區106的面積越大時(如，圖2A所示)，提升半導體元件108的崩潰電壓的效果越好。 Based on the foregoing embodiments, it can be known that in the semiconductor structure 10, since the embedded doped region 106 is located in the semiconductor layer 102 below the floating body field ring structure 104 and is connected to the floating body field ring structure 104, the depletion region can be enlarged. range, thereby increasing the breakdown voltage of the semiconductor device 108 . On the other hand, since the semiconductor structure 10 can increase the breakdown voltage of the semiconductor device 108 , even if the area of the floating body field ring structure 104 is reduced, the same breakdown voltage as the prior art can be maintained, and the device size can be smaller. In addition, when the area of the embedded doped region 106 is larger (eg, as shown in FIG. 2A ), the effect of increasing the breakdown voltage of the semiconductor device 108 is better.

綜上所述，在上述實施例的半導體結構中，可藉由位在浮體場環結構下方且連接於浮體場環結構的嵌入式摻雜區來擴大 空乏區的範圍，因此可提升半導體元件的崩潰電壓。 To sum up, in the semiconductor structure of the above-mentioned embodiment, the embedded doped region located under the floating body field ring structure and connected to the floating body field ring structure can enlarge the The scope of the depletion region, so the breakdown voltage of the semiconductor device can be increased.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

10:半導體結構 10:Semiconductor structure

100:基底 100: base

102:半導體層 102: Semiconductor layer

104:浮體場環結構 104: Floating body field ring structure

104a:浮體場環 104a: Floating body field ring

106:嵌入式摻雜區 106: Embedded doping area

108:半導體元件 108: Semiconductor components

110,112,116,118:摻雜區 110, 112, 116, 118: doped regions

114:井區 114: well area

R:半導體元件區 R: semiconductor element area

W:寬度 W: width

Claims (13)

一種半導體結構，包括：基底；半導體層，設置在所述基底上，且具有第一導電型；浮體場環結構，位在所述半導體層中，且包括至少一個浮體場環，其中所述浮體場環具有第二導電型；以及嵌入式摻雜區，位在所述浮體場環結構下方的所述半導體層中，且連接於所述浮體場環結構，其中所述嵌入式摻雜區具有所述第二導電型，且所述嵌入式摻雜區位在整個所述浮體場環結構的正下方。 A semiconductor structure, comprising: a substrate; a semiconductor layer disposed on the substrate and having a first conductivity type; a floating body field ring structure located in the semiconductor layer and including at least one floating body field ring, wherein the The floating body field ring has a second conductivity type; and an embedded doped region is located in the semiconductor layer below the floating body field ring structure and connected to the floating body field ring structure, wherein the embedded The type doped region has the second conductivity type, and the embedded doped region is directly below the entire floating body field ring structure. 如請求項1所述的半導體結構，其中所述嵌入式摻雜區僅位在整個所述浮體場環結構的一側。 The semiconductor structure according to claim 1, wherein the embedded doped region is only located on one side of the entire floating body field ring structure. 如請求項1所述的半導體結構，其中所述嵌入式摻雜區的數量為一個。 The semiconductor structure according to claim 1, wherein the number of the embedded doped region is one. 如請求項1所述的半導體結構，其中所述嵌入式摻雜區的數量為多個。 The semiconductor structure as claimed in claim 1, wherein the number of the embedded doped regions is multiple. 一種半導體結構，包括：基底；半導體層，設置在所述基底上，且具有第一導電型；浮體場環結構，位在所述半導體層中，且包括至少一個浮體場環，其中所述浮體場環具有第二導電型；以及嵌入式摻雜區，位在所述浮體場環結構下方的所述半導體層 中，且連接於所述浮體場環結構，其中所述嵌入式摻雜區具有所述第二導電型，且所述基底包括半導體元件區，所述浮體場環結構環繞所述半導體元件區，且所述半導體結構更包括：半導體元件，包括：第一摻雜區，位在所述半導體元件區的所述半導體層中，且具有所述第二導電型；以及第二摻雜區，位在所述基底中，且鄰近於所述半導體層，其中所述第二摻雜區具有所述第一導電型。 A semiconductor structure, comprising: a substrate; a semiconductor layer disposed on the substrate and having a first conductivity type; a floating body field ring structure located in the semiconductor layer and including at least one floating body field ring, wherein the The floating body field ring has a second conductivity type; and an embedded doping region, the semiconductor layer located under the floating body field ring structure and connected to the floating body field ring structure, wherein the embedded doped region has the second conductivity type, and the substrate includes a semiconductor element region, and the floating body field ring structure surrounds the semiconductor element region, and the semiconductor structure further includes: a semiconductor element, including: a first doped region, located in the semiconductor layer of the semiconductor element region, and having the second conductivity type; and a second doped region , located in the substrate and adjacent to the semiconductor layer, wherein the second doped region has the first conductivity type. 如請求項5所述的半導體結構，其中所述嵌入式摻雜區更位在所述第一摻雜區的正下方。 The semiconductor structure as claimed in claim 5, wherein the embedded doped region is located directly below the first doped region. 如請求項5所述的半導體結構，其中所述半導體元件更包括：井區，位在所述半導體元件區的所述半導體層中，且具有所述第二導電型，其中所述第一摻雜區位在所述井區中。 The semiconductor structure according to claim 5, wherein the semiconductor element further comprises: a well region located in the semiconductor layer of the semiconductor element region and having the second conductivity type, wherein the first doped A hetero site is located in the well region. 如請求項7所述的半導體結構，其中所述嵌入式摻雜區更位在所述井區的正下方。 The semiconductor structure as claimed in claim 7, wherein the embedded doped region is located directly below the well region. 如請求項5所述的半導體結構，其中所述半導體元件更包括：第三摻雜區，位在所述浮體場環結構的遠離所述半導體元件區的一側的所述半導體層中。 The semiconductor structure according to claim 5, wherein the semiconductor element further comprises: a third doped region located in the semiconductor layer on a side of the floating body field ring structure away from the semiconductor element region. 如請求項9所述的半導體結構，其中所述嵌入式摻雜區更位在所述第三摻雜區的正下方。 The semiconductor structure as claimed in claim 9, wherein the embedded doped region is located directly below the third doped region. 如請求項9所述的半導體結構，更包括：第四摻雜區，位在所述浮體場環結構與所述第三摻雜區之間的所述半導體層中，且具有所述第一導電型。 The semiconductor structure according to claim 9, further comprising: a fourth doped region, located in the semiconductor layer between the floating body field ring structure and the third doped region, and having the first A conductivity type. 如請求項11所述的半導體結構，其中所述嵌入式摻雜區更位在所述第四摻雜區的正下方。 The semiconductor structure as claimed in claim 11, wherein the embedded doped region is located directly below the fourth doped region. 一種半導體結構，包括：基底；半導體層，設置在所述基底上，且具有第一導電型；浮體場環結構，位在所述半導體層中，且包括至少一個浮體場環，其中所述浮體場環具有第二導電型；以及嵌入式摻雜區，位在所述浮體場環結構下方的所述半導體層中，且連接於所述浮體場環結構，其中所述嵌入式摻雜區具有所述第二導電型，且所述嵌入式摻雜區位在部分所述浮體場環結構的正下方。 A semiconductor structure, comprising: a substrate; a semiconductor layer disposed on the substrate and having a first conductivity type; a floating body field ring structure located in the semiconductor layer and including at least one floating body field ring, wherein the The floating body field ring has a second conductivity type; and an embedded doped region is located in the semiconductor layer below the floating body field ring structure and connected to the floating body field ring structure, wherein the embedded The type doped region has the second conductivity type, and the embedded doped region is directly under part of the floating body field ring structure.
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