JP7423853B2 - semiconductor equipment - Google Patents

Description

The present invention relates to a semiconductor device having a trench gate structure.

For example, Patent Document 1 describes an epitaxial layer in which an active cell array and a gate bus area are formed, a gate trench formed in the active cell array, a gate oxide film formed in the gate trench, and a polysilicon buried in the gate trench. a trench formed in the gate bus area and connected to the gate trench, and a gate bus (gate finger) made of polysilicon embedded in the trench so as to cover the surface of the epitaxial layer in the gate bus area. , discloses a trench gate vertical MOSFET.

Special Publication No. 2006-520091

In order to obtain high avalanche resistance in a transistor, it is necessary to cause avalanche breakdown in the pn junction of the active part. In other words, during avalanche breakdown (when high voltage is applied), if the electric field concentrates on the gate finger part, which has a lower dielectric breakdown strength than the active part, the gate finger part will break down first, so sufficient avalanche strength cannot be achieved. It is difficult to obtain.

One embodiment of the present invention provides a semiconductor device having a trench gate structure that can obtain high avalanche resistance.

One embodiment of the present invention includes an active part, a semiconductor layer made of SiC, and a plurality of MIS transistors formed in the active part, wherein the active part is divided into a plurality of unit cells by a plurality of gate trenches. each MIS transistor includes a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of a first conductivity type along the side surface of the gate trench; and a gate finger portion. a plurality of first gate finger trenches configured by extensions of the gate trench; a gate electrode embedded in the gate trench and the first gate finger trench via a gate insulating film; and the first gate finger trench. a first bottom impurity region of a second conductivity type formed at least at the bottom of the semiconductor layer, at least a part of the bottom of the first bottom impurity region forming a horizontal straight line along the surface of the semiconductor layer in cross-sectional view; a first bottom impurity region having the same depth, a gate conductive layer electrically connected to the plurality of first gate finger trenches and the gate electrode, and a source electrode formed on the semiconductor layer. and a first film containing a non-conductive material formed on the semiconductor layer between the adjacent gate trenches, and a first conductive film formed between the source electrode and the first film. , the source electrode has a protrusion that protrudes in the thickness direction of the semiconductor layer, and forms a boundary with the first conductive film in a direction intersecting the thickness direction of the semiconductor layer. , the gate conductive layer includes a gate finger formed in at least the gate finger portion and connected to the gate electrode, and the first gate finger trench extends below the gate finger and across the gate finger to the outside. A semiconductor device is provided which is formed into an extending line shape.

FIGS. 1A and 1B are schematic plan views of a semiconductor device according to an embodiment of the present invention. FIG. 1(a) shows an overall view, and FIG. 1(b) shows an enlarged internal view. FIG. 2A is a cross-sectional view (a cross-sectional view taken along the line IIA-IIA in FIG. 1(b)) of the semiconductor device. FIG. 2B is a cross-sectional view of the semiconductor device (cross-sectional view taken along the line IIB-IIB in FIG. 1(b)). FIG. 2C is a cross-sectional view of the semiconductor device (cross-sectional view taken along the line IIC-IIC in FIG. 1(b)). FIG. 2D is a cross-sectional view of the semiconductor device (cross-sectional view taken along the line IID-IID in FIG. 1(b)). FIG. 3 is an enlarged sectional view of the gate finger portion of the semiconductor device. FIG. 4 is a flow diagram for explaining the method for manufacturing the semiconductor device. FIG. 5 is a diagram for explaining the process of forming an inclined surface on the upper edge. FIG. 6 is a diagram for explaining the process of forming a circular surface on the upper edge. FIG. 7 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 8 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 9 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 10 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 11 is a plan view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 12 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 13 is a cross-sectional view for explaining one embodiment of the gate finger portion of the semiconductor device. FIG. 14 is a cross-sectional view for explaining one embodiment of the active portion of the semiconductor device. FIG. 15 is a diagram for explaining one embodiment of the active portion of the semiconductor device.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIGS. 1A and 1B are schematic plan views of a semiconductor device 1 according to an embodiment of the present invention. FIG. 1(a) shows an overall view, and FIG. 1(b) shows an enlarged internal view.

The semiconductor device 1 includes a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) element (individual element) using SiC (silicon carbide). For example, the vertical length of the semiconductor device 1 in the paper of FIG. 1 is about 1 mm.

As shown in FIG. 1(a), a semiconductor device 1 includes a SiC substrate 2 as an example of a semiconductor layer. SiC substrate 2 may be an SiC epitaxial substrate including a base substrate and an active layer epitaxially grown thereon. The SiC substrate 2 includes an active part 3 disposed at the center thereof and functioning as a field effect transistor, and a gate finger part 4 surrounding the active part 3.

The source pad 5 made of aluminum, for example, is formed to cover almost the entire area of the active part 3. The source pad 5 has a substantially square shape in plan view. A removal region 6 surrounding the center of the source pad 5 along the gate finger section 4 is formed at the peripheral edge of the source pad 5 . A portion of the removed region 6 is selectively depressed toward the center of the source pad 5 . A gate pad 7 is installed in this recess. A gate finger 8 made of aluminum, for example, extends from the gate pad 7 along the gate finger portion 4 over the entire removal region 6 . A pair of gate fingers 8 are formed symmetrically with respect to the gate pad 7.

As shown in FIG. 1B, a gate trench 9 and a gate finger trench 10 are formed in the SiC substrate 2 directly under the source pad 5 and the like. Gate trench 9 is formed in active section 3 . Gate trench 9 is formed in a lattice shape.

Gate finger trench 10 is formed in gate finger portion 4 . Gate finger trench 10 is integrally formed with gate trench 9. Further, the gate finger trench 10 is formed to have the same width as the gate trench 9. By making the widths the same, it is possible to prevent embedding defects when embedding the gate electrode 22, which will be described later.

Gate finger trench 10 includes a first gate finger trench 11 and a second gate finger trench 12. The first gate finger trench 11 is an extension of the gate trench 9 and is formed in a stripe shape extending from each end of the gate trench 9 to the gate finger section 4 . That is, the first gate finger trenches 11 are arranged at the same pitch as the lattice pitch _P1 of the gate trenches 9. A plurality of second gate finger trenches 12 are formed in a region between adjacent first gate finger trenches 11 . The second gate finger trench 12 is connected to a portion 14 between the ends of a lateral trench 13 that spans a plurality of ends of the gate trench 9 . In FIG. 1B, two second gate finger trenches 12 are provided in the portion 14 between each end, but this number is not particularly limited. Also, in this embodiment, each second gate finger trench 12 is parallel to the first gate finger trench 11. In the gate finger section 4, gate finger trenches 10 consisting of a first gate finger trench 11 and a second gate finger trench 12 are arranged at a pitch _P2 narrower than the lattice pitch _P1 .

Note that the patterns of the gate trenches 9 and gate finger trenches 10 are not limited to these shapes. For example, the gate trench 9 may have a stripe shape, a honeycomb shape, or the like. Further, the gate finger trench 10 may have a lattice shape, a honeycomb shape, or the like.

The active portion 3 is further divided into a large number of unit cells 15 by gate trenches 9 . In the active section 3, a large number of unit cells 15 are regularly arranged in a matrix. A source trench 47 is formed in the center of each unit cell 15 . A p ⁺ type channel contact region ¹⁶ (for example, a concentration of 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ ) is formed in the center region of the bottom surface of the source trench 47 . An n ⁺ -type source region 17 (for example, a concentration of 1×10 ¹⁸ cm ⁻³ to 5×10 ²¹ cm ⁻³ ) is formed to surround (source trench 47).
The n ⁺ -type source region 17 forms the side surface of each unit cell 15 (the side surface of the gate trench 9 ) and the side surface of the source trench 47 .

In the gate finger portion 4, the gate fingers 8 are laid along a direction that traverses a striped gate finger trench 10. In this embodiment, the gate finger 8 is laid in a region inside the longitudinal end of the gate finger trench 10 (the end opposite to the gate trench 9), and the end of the gate finger trench 10 is It protrudes outward from the gate finger 8. A low step portion 18 is formed in the SiC substrate 2 in a region further outside the terminal end portion, which is dug down over the entire circumference of the gate finger portion 4 . A p-type guard ring or the like (not shown) may be formed in the low step portion 18 .

Next, the basic cross-sectional structures of the active section 3 and gate finger section 4 of the semiconductor device 1 will be explained.

2A, 2B, 2C, and 2D are cross-sectional views of the semiconductor device 1 (IIA-IIA line cross-sectional view, IIB-IIB line cross-sectional view, IIC-IIC line cross-sectional view, and IID -IID line sectional view).

As described above, the semiconductor device 1 includes the SiC substrate 2. SiC substrate 2 is an n-type SiC substrate in this embodiment. A portion of the SiC substrate 2 below the surface portion functions as an n-type drain region 20 (for example, a concentration of 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ ) of a field effect transistor.

Further, a gate trench 9 and a gate finger trench 10 are formed on the front surface 21 side of the SiC substrate 2. As described above, the active section 3 is further divided into a large number of unit cells 15 by the gate trenches 9. An n ⁺ type source region 17 is formed on the upper surface of each unit cell 15, and a p type channel region 19 (for example, a concentration of 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ ) is formed below it. ing. That is, as shown in FIG. 2A, the gate trench 9 penetrates the n ⁺ type source region 17 and the p type channel region 19 and reaches the n type drain region 20.

A gate electrode 22 made of, for example, polysilicon is buried in the gate trench 9 and the gate finger trench 10 all together. A gate insulating film 23 is interposed between the gate electrode 22 and the SiC substrate 2.

In the active portion 3, the gate electrode 22 is embedded in the gate trench 9 up to the surface 21 of the SiC substrate 2, as shown by diagonal hatching in FIG. 1(b), for example. As a result, the gate electrode 22 is also formed in a grid shape, and the upper surface of each unit cell 15 is exposed without being covered with the gate electrode 22. On the other hand, the gate finger section 4 has an overlap section 24 formed so as to cover the surface 21 of the SiC substrate 2 from the open end of the gate finger trench 10 . The overlap portion 24 is formed along the gate finger 8 and across the striped gate finger trench 10 .

The gate insulating film 23 integrally includes a side surface portion 25 on the side surface of the gate trench 9, a bottom surface portion 26 on the bottom surface, and a surface portion 27 on the surface 21 of the SiC substrate 2. The surface portion 27 is interposed between at least the overlap portion 24 and the surface 21 of the SiC substrate 2 .

In the active part 3, the gate electrode 22 extends between the n ⁺ type source region 17 and the n type drain region 20, and forms an inversion layer (channel) on the surface of the p type channel region 19 (side surface of the gate trench 9). control the formation of That is, this semiconductor device 1 has a MOSFET with a so-called trench gate structure.

A source trench 47 is formed in the center of each unit cell 15 . Source trench 47 has the same depth as gate trench 9, but has a wider width than gate trench 9. Source trench 47 penetrates n ⁺ -type source region 17 and p-type channel region 19 . The source trench 47 may have a shape defined only by the outer periphery, as shown in FIG. 1(b) in plan view. In this case, in the cut surface that appears when the SiC substrate 2 is cut in the depth direction, one source trench 47 appears as shown in FIG. 2A (first pattern of source trenches). Specifically, as shown in FIG. 1(b), it may be a (regular) quadrilateral in plan view, a (regular) hexagon, a circle, or the like.

An insulating film residue 49 and an electrode film residue 50 remain below the source trench 47. The insulating film residue 49 is selectively present at the corner portion of the source trench 47 and its periphery so as to expose the center portion of the bottom surface of the source trench 47 . The electrode film residue 50 exists only on the insulating film residue 49. In other words, the planar patterns of the insulating film residue 49 and the electrode film residue 50 are aligned with each other.

Furthermore, in the active portion 3, a p-type region 28 (eg, concentration 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ ) is formed in the n-type drain region 20 . P-type region 28 is formed along the inner surface of source trench 47. P-type region 28 extends vertically from p-type channel region 19 along the side surfaces of source trench 47 and has an outer surface that extends laterally along the bottom surface of source trench 47 . The vertical outer surface of p-type region 28 is spaced inward from gate trench 9 . Therefore, in an intermediate region between the outer surface and the gate trench 9, an n-type drain region 20 and a p-type channel region 19 connected to a p-type region 28 are present. The p-type region 28 is formed so as to be continuous with the p-type channel region 19, and extends toward the back surface of the SiC substrate 2 to a position _d1 deeper than the p-type channel region 19 in the n-type drain region 20. .

P ⁺ type channel contact region 16 is selectively formed in the center of the bottom surface of source trench 47 . Furthermore, the p ⁺ type channel contact region 16 is formed to have a size that spans the inside and outside of the insulating film residue 49. The thickness of p ⁺ type channel contact region 16 (vertical depth from the bottom surface of source trench 47) is smaller than the thickness of p type region 28. Therefore, p ⁺ -type channel contact region 16 is formed in a floating state on the surface of p-type region 28 .

On the surface 21 of the SiC substrate 2, an interlayer film 29 made of silicon oxide, for example, is formed. A contact hole 30 is selectively formed in the interlayer film 29 in the central region of the p-type channel region 19 in the active portion 3 . This contact hole 30 selectively exposes the source trench 47. Further, in the interlayer film 29, a contact hole 31 is selectively formed directly under the gate finger 8 in the gate finger portion 4. The contact hole 31 is formed in a straight line at the center of the gate finger 8 in the width direction, surrounding the active part 3 along the gate finger part 4 .

A source pad 5 and a gate finger 8 (gate pad 7) are formed on the interlayer film 29. The source pad 5 enters all the contact holes 30 at once and is connected to the n ⁺ -type source region 17 and the p ⁺ -type channel contact region 16 in each unit cell 15 . Therefore, n ⁺ type source region 17 has the same potential as source pad 5. Further, since p type channel region 19 is connected to source pad 5 via p ⁺ type channel contact region 16, it has the same potential as source pad 5. The gate finger 8 enters the contact hole 31 and is connected to the overlap portion 24 of the gate electrode 22. Therefore, the gate electrode 22 embedded in the gate trench 9 is connected to the gate finger 8 via the overlap portion 24, and therefore has the same potential as the gate finger 8 (gate pad 7).

FIG. 3 is an enlarged cross-sectional view of the gate finger section 4 of the semiconductor device 1. In FIG. 3, parts corresponding to those shown in FIGS. 1 and 2 described above are given the same reference numerals. Further, in FIG. 3, the gate finger 8 and the interlayer film 29 are omitted.

The side surface portion 25 of the gate insulating film 23 has an overcoat that is selectively thicker than other portions of the side surface portion 25 so as to protrude inward from the gate finger trench 10 at the upper edge 32 of the gate finger trench 10. It includes a hang part 33. This overhang portion 33 may be employed at the upper edge (not shown) of the gate trench 9.

The upper edge 32 is a corner including a line of intersection formed by the side surface of the gate finger trench 10 and the surface 21 of the SiC substrate 2. In FIG. 3, the upper edge 32 is an inclined surface 34 that connects the surface 21 of the SiC substrate 2 and the side surface of the gate finger trench 10. That is, the upper edge 32 of the gate finger trench 10 has a chamfered shape. Note that instead of this inclined surface 34, a circular surface 39 (see FIG. 6) may be employed. The circular surface 39 causes the upper edge 32 of the gate finger trench 10 to be rounded rather than sharp.

In the semiconductor device 1, when an on-voltage is applied to the gate finger 8, an on-voltage is also applied to the overlap portion 24 of the gate electrode 22. Therefore, the electric field generated from the overlap portion 24 tends to concentrate on the upper edge 32 of the gate finger trench 10. As a result, there is a risk of dielectric breakdown of the gate insulating film 23 at the upper edge 32 of the gate finger trench 10. However, the overhang portion 33 can improve the breakdown voltage of the gate insulating film 23 at the upper edge 32. Therefore, even if an electric field concentrates on the upper edge 32 when the gate is turned on, dielectric breakdown of the gate insulating film 23 at the upper edge 32 can be prevented. As a result, reliability with respect to gate-on voltage can be improved.

Regarding the relationship between the thicknesses of each part of the gate insulating film 23, the thickness t ₂ of the bottom part 26 is greater than or equal to the thickness t ₁ of the surface part 27 (t ₂ ≧t ₁ ), and both the thicknesses t ₁ and t ₂ are It is preferable that the thickness is larger than the thickness _t3 of the side surface portion 25 (excluding the overhang portion 33). In other words, the relationship t ₂ ≧t ₁ >t ₃ is satisfied. With this configuration, the capacitance of the capacitor formed by the gate electrode 22 and the SiC substrate 2 facing each other with the bottom surface portion 26 interposed therebetween can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. Further, since the withstand voltage of the bottom portion 26 can be improved, dielectric breakdown of the bottom portion 26 when the gate is turned off can be prevented. Further, since the surface portion 27 is also thick, the capacitance of the capacitor formed by the gate electrode 22 (overlap portion 24) and the SiC substrate 2 facing each other via the surface portion 27 can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

A lower edge at the bottom of the gate finger trench 10 is a circular surface 35 that connects the side surface and the bottom surface of the gate finger trench 10. That is, the lower edge of the gate finger trench 10 is not sharp, but is rounded by the circular surface 35. With this configuration, the electric field applied to the lower edge when the gate is off can be dispersed within the circular surface 35, so that concentration of the electric field at the lower edge can be alleviated.

Further, on the front surface 21 side of the SiC substrate 2, a p-type region 36 (for example, a concentration of 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ ) is formed as an example of a surface impurity region. The p-type region 36 is formed over the entire region 37 between adjacent gate finger trenches 10 (a flat region where the surface 21 of the SiC substrate 2 is continuous from one gate finger trench 10 to the other gate finger trench 10). has been done. The p-type region 36 is formed shallower than the gate finger trench 10, and is formed, for example, at the same depth as the p-type channel region 19 of the active section 3 (see FIG. 2A).

Furthermore, a bottom p-type region 38 (eg, concentration 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ ) as an example of an electric field relaxation region is formed at the bottom of the gate finger trench 10 . Bottom p-type region 38 is continuous with p-type region 36. Specifically, the bottom p-type region 38 is formed on the bottom and side surfaces of the gate finger trench 10 so as to hide the n-type drain region 20 exposed in the gate finger trench 10 below the p-type region 36. It is connected to the p-type region 36 at its upper end. Therefore, in the width direction of gate finger trench 10, a plurality of bottom p-type regions 38 and p-type regions 36 are formed in succession alternately. On the other hand, in the longitudinal direction of the gate finger trench 10, the bottom p-type region 38 crosses the boundary between the gate finger trench 10 and the low step portion 18 on the tip side of the gate finger trench 10, as shown in FIG. 2D. , reaching the low step portion 18. On the other hand, on the base end side of the gate finger trench 10 (gate trench 9 side), it is also formed at the bottom of the horizontal trench 13, and is further integrated with the p-type channel region 19 at the side of the horizontal trench 13. Thereby, bottom p-type region 38 is electrically connected to p-type channel region 19. Of course, the p-type region 36 is also electrically connected to the p-type channel region 19 via the bottom p-type region 38. Further, the depth d ₂ of the bottom p-type region 38 is either the same as the depth d ₁ of the deepest part of the p-type impurity region in the active region 3 (the bottom of the p-type region 28 in this embodiment), or the depth d It is preferably smaller than ₁ (d ₁ ≧d ₂ ). By maintaining the size relationship between the depths d ₁ and d ₂ , it is possible to further enhance the effect of alleviating electric field concentration on the gate finger portion 4 when a high voltage is applied.

FIG. 4 is a flow diagram for explaining the method for manufacturing the semiconductor device 1. As shown in FIG.

To manufacture the semiconductor device 1, for example, impurities are selectively implanted into the surface 21 of the SiC substrate 2, and annealing treatment is performed (step S1). As a result, impurity regions such as the p type channel region 19, the n ⁺ type source region 17, the p ⁺ type channel contact region 16, etc. are formed. Next, gate trenches 9, gate finger trenches 10, and source trenches 47 are simultaneously formed in SiC substrate 2 by etching SiC substrate 2 in a predetermined pattern from surface 21 (step S2).

The next step is the formation of p-type region 28 and bottom p-type region 38. Formation of p-type region 28 and bottom p-type region 38 is performed by ion implantation and annealing treatment (step S3). For example, a mask is formed on the SiC substrate 2 to cover areas other than those where the p-type region 28 and the bottom p-type region 38 are to be formed, and p-type impurities (ions) are implanted through the mask. Bottom p-type region 38 is formed by p-type impurities implanted into the side and bottom surfaces of gate finger trench 10. After implantation, an annealing process is performed.

The next step is the formation of the gate insulating film 23 (step S4). The gate insulating film 23 is formed under predetermined conditions (gas flow rate, gas type, gas An insulating material is deposited in the gate trenches 9 and gate finger trenches 10 using a CVD method under the following conditions: ratio, gas supply time, etc.). As a result, a gate insulating film 23 having an overhang portion 33 is formed.

Here, when forming the inclined surface 34 on the upper edge 32 as shown in FIG. 3, the SiC substrate 2 is thermally oxidized after the gate trench 9 is formed and before the gate insulating film 23 is formed. Specifically, as shown in FIG. 5, a sacrificial oxide film 40 is formed by thermally oxidizing the SiC substrate 2. When forming the sacrificial oxide film 40, oxidation starts uniformly from both the surface 21 of the SiC substrate 2 and the side surfaces of the gate finger trench 10 in the vicinity of the gate finger trench 10. Therefore, in the upper edge 32, the oxide film that has progressed from the surface 21 of the SiC substrate 2 and the oxide film that has progressed from the side surface of the gate finger trench 10 are integrated earlier than in other regions. As a result, an inclined surface 34 is formed below the integrated oxide film. Thereafter, the sacrificial oxide film 40 may be removed and the gate insulating film 23 may be formed by CVD.

On the other hand, when forming the circular surface 39 on the upper edge 32, the SiC substrate 2 is subjected to H ₂ annealing after the gate finger trench 10 is formed and before the gate insulating film 23 is formed. Specifically, as shown in FIG. 6, a circular surface 39 is formed on the upper edge 32 by subjecting the SiC substrate 2 to H ₂ annealing (H ₂ etching) at 1400° C. or higher.

Returning to FIG. 4 again, after forming the gate insulating film 23, the gate trench 9 and the gate finger trench 10 are backfilled, and polysilicon is deposited until the gate trench 9 and the gate finger trench 10 are completely covered (step S5). Then, by patterning the deposited polysilicon, the polysilicon outside the gate trench 9 is removed in the active part 3, and at the same time, the polysilicon remains as an overlap part 24 in the gate finger part 4. At this time, an electrode film residue 50 made of the remaining polysilicon material is formed in the source trench 47.

Next, an interlayer film 29 is formed on the SiC substrate 2 by the CVD method (step S6). Next, contact holes 30 and contact holes 31 are simultaneously formed by patterning interlayer film 29 (step S7). At this time, part of the gate insulating film 23 remains in the source trench 47 as an insulating film residue 49 in a portion sandwiched between the electrode film residue 50 and the inner surface of the source trench 47 .

Next, a metal material such as aluminum is deposited on the interlayer film 29 by sputtering or vapor deposition (step S8). As a result, source pad 5, gate pad 7, and gate finger 8 are formed. Through the above steps, etc., the semiconductor device 1 is obtained.

According to the semiconductor device 1, since the bottom p-type region 38 is formed, a depletion layer generated by the junction (pn junction) between the bottom p-type region 38 and the n-type drain region 20 is generated near the gate finger trench 10. can be done. The presence of this depletion layer allows the equipotential surface to be moved away from the gate insulating film 23. As a result, the electric field applied to the gate insulating film 23 at the bottom of the gate finger trench 10 can be relaxed. Further, since the bottom p-type region 38 of the gate finger section 4 can be formed in the same process as the p-type region 28 of the active section 3, the manufacturing process of the semiconductor device 1 can also be simplified.

Furthermore, since the pitch _P2 of the gate finger trenches 10 is narrower than the lattice pitch _P1 of the gate trenches 9 (see FIG. 2B), the density of the bottom p-type region 38 in the gate finger portion 4 can be increased. Can be done. Therefore, when a high voltage is applied, electric field concentration on the gate finger portion 4 can be alleviated, and occurrence of avalanche breakdown in the gate finger portion 4 can be reduced. As a result, avalanche breakdown can occur preferentially in the active section 3, so that high avalanche tolerance can be achieved.

For example, according to the experimental results of the present inventor, in the semiconductor device 1 having the structure shown in FIGS. 1 to 3, if the pitch _P2 is narrowed from 6 μm to 2 μm, the It was found that the electric field could be relaxed to about 0.7 times. As a result, it was found that the avalanche current could be withstood approximately eight times as much as before the pitch was changed.

Moreover, since the structure for mitigating the electric field in the gate finger section 4 is the bottom p-type region 38 formed at the bottom of the gate finger trench 10, the p-type impurity region is formed relatively shallowly from the bottom of the gate finger trench 10. By doing so, it is possible to easily form an electric field relaxation region deeper than the bottom of the gate finger trench 10.

7 to 13 are diagrams for explaining one embodiment of the gate finger section 4 of the semiconductor device 1. FIG. Further, FIGS. 14 and 15 are diagrams for explaining one embodiment of the active section 3 of the semiconductor device 1.

As shown in FIG. 7, the semiconductor device 1 does not need to have the second gate finger trenches 12 between the first gate finger trenches 11. In this case, a region between adjacent first gate finger trenches 11 is formed as a flat region 37, and a p-type region 36 is formed over the entire flat region 37. In FIG. 7, the structure for mitigating the electric field in the gate finger portion 4 is formed as a p-type protruding region 41. In FIG. The p-type protruding region 41 is continuous with the p-type region 36 and selectively protrudes downward from the p-type region 36. The protruding position is, for example, the formation position of the second gate finger trench 12 described above. The p-type protruding region 41 may be formed to have the same depth d ₂ as the bottom p-type region 38 of the first gate finger trench 11 . Further, the p-type protruding region 41 may have a stripe shape parallel to the first gate finger trench 11 similarly to the second gate finger trench 12, or may have a stripe shape parallel to the first gate finger trench 11. It may also have a selectively protruding shape. Note that the p-type protruding region 41 may be formed by an ion implantation/annealing process for forming the p-type region 28.

According to this configuration, in the gate finger portion 4, the pitch _P2 of the p-type region deeper than the first gate finger trench 11 can be made narrower than the lattice pitch _P1 of the gate trench 9. Therefore, in the gate finger portion 4, the density of the bottom p-type region 38 and the p-type protrusion region 41 can be increased. Therefore, when a high voltage is applied, electric field concentration on the gate finger portion 4 can be alleviated, and occurrence of avalanche breakdown in the gate finger portion 4 can be reduced. As a result, avalanche breakdown can occur preferentially in the active section 3, so that high avalanche tolerance can be achieved.

Furthermore, since the p-type protrusion region 41 is formed in the flat region 37 of the SiC substrate 2, even if the mask position shifts during ion implantation, the depth aimed at the p-type protrusion region 41 can be achieved with high probability. can be formed in position.

For example, when a p-type impurity region is formed by ion implantation into the SiC substrate 2, its depth is controlled by the implantation energy. The greater the implantation energy, the deeper the p-type impurity region can be formed from the surface 21 of the SiC substrate 2. Since the implantation energy is determined depending on the target depth position, if a mask misalignment occurs before implantation, it may not be possible to form an impurity region at the target depth position. For example, as described above, the energy conditions when forming the bottom p-type region 38 of the gate finger trench 10 are determined based on the depth from the ion implantation surface (the bottom surface of the gate finger trench 10) as a reference plane. Determined by However, if the mask shifts laterally with respect to the gate finger trench 10, the depth reference plane will rise to the surface 21 of the SiC substrate 2 (the opening end of the gate finger trench 10), and the depth will be shallower than the intended position. There is a possibility that an impurity region will be formed only in this case. However, according to this configuration, since the p-type protruding region 41 is formed in the flat region 37, even if the mask is misaligned, the height position of the reference plane for ion implantation hardly changes. Therefore, the above effects can be obtained.

Further, in place of the p-type protruding region 41 in FIG. 7, the semiconductor device 1 has a p-type floating region 42 formed downwardly from the p-type region 36 at an interval, as shown in FIG. Good too. The formation position of the p-type floating region 42 is, for example, the formation position of the second gate finger trench 12 described above. Further, the p-type floating region 42 may have a stripe shape parallel to the first gate finger trench 11 similarly to the second gate finger trench 12, or may have a stripe shape parallel to the first gate finger trench 11. They may be selectively scattered.

As shown in FIG. 9, the semiconductor device 1 may have a p-type region 43 that extends over the entire lower part of the p-type region 36. The p-type region 43 is continuous and integrated with the bottom p-type region 38 of the first gate finger trench 11 in the lateral direction along the surface 21 of the SiC substrate 2 . Further, the p-type region 43 may be formed to have the same depth d ₂ as the bottom p-type region 38 of the first gate finger trench 11 . As a result, in the flat region 37, a p-type impurity region is continuously formed in a region deeper than the first gate finger trench 11 from one first gate finger trench 11 to the other first gate finger trench 11. There is. That is, the entire region between adjacent first gate finger trenches 11 is covered with a p-type region deeper than the first gate finger trenches 11. Therefore, the density of the p-type region in the gate finger portion 4 can be increased.

As shown in FIG. 10, the semiconductor device 1 may have an n ⁺ type region 44 within the p type region 36. The n ⁺ type region 44 may be formed at the same depth as the n ⁺ type source region 17 (see FIG. 2A) of the active part 3.

As shown in FIG. 11, the semiconductor device 1 includes a second gate finger trench extending in a direction crossing the first gate finger trench 11 instead of a second gate finger trench 12 parallel to the first gate finger trench 11. 45. A plurality of second gate finger trenches 45 may be formed at intervals in the longitudinal direction of the first gate finger trench 11. Thereby, the gate finger trench 10 as a whole may be formed in a lattice shape by the first gate finger trench 11 extending in one direction and the second gate finger trench 45 extending in the other direction crossing the first gate finger trench 11. Then, the bottom p-type region 38 may be formed in the second gate finger trench 45 as well as in the first gate fin trench 11 (see FIG. 3). As a result, in the region along the second gate finger trench 45, as shown in FIG. The type impurity regions can be formed continuously.

As shown in FIG. 13, the semiconductor device 1 does not need to have the sloped surface 34 or the circular surface 39 on the upper edge 32 of the gate finger trench 10. That is, the upper edge 32 may be sharp.

Further, the semiconductor device 1 may include a source trench 48 instead of the source trench 47, as shown in FIG. The source trench 48 has a shape defined by both sides of the outer periphery and the inner periphery in plan view (the left side diagram in FIG. 14). In this case, in the cut surface that appears when the SiC substrate 2 is cut in the depth direction, two source trenches 48 appear (second pattern of source trenches), as shown in the cross section taken along line AA. Specifically, as shown in the diagram on the left side of FIG. 14, it may have a (regular) square ring shape in plan view, a (regular) hexagonal ring shape, a circular ring shape, or the like. As a result, a convex portion 51 (mesa portion) defined by the inner periphery of the source trench 48 is formed in the inner region of the source trench 48 . Further, source trench 48 has the same depth and width as gate trench 9.

P-type region 28 is formed throughout the outer edge of source trench 48 and its inner region, similar to the structure of FIG. 2A. Therefore, p-type region 28 extends vertically from p-type channel region 19 along the side surfaces of source trench 48 and has an outer surface extending horizontally along the bottom surface of source trench 48 . At the bottom, it has an outer surface extending laterally along the surface of the SiC substrate 2 . As a result, in the configuration of FIG. 14, the p-type region 28 is formed deeper than the source trench 48 below the convex portion 51. In this embodiment, most of the convex portion 51 except for the surface portion is composed of the p-type region 28 . The p ⁺ type channel contact region 16 may be formed over the entire surface of the convex portion 51 .

Further, the semiconductor device 1 does not need to include source trenches 47 and 48, as shown in FIG. 15. The p ⁺ type channel contact region 16 is formed in the central region of each unit cell 15, and the n ⁺ type source region 17 may be formed to surround this p ⁺ type channel contact region 16. In this case, the semiconductor device 1 may include a p-type pillar layer 46 (for example, a concentration of 1×10 ¹⁶ cm ⁻³ to 1×10 ¹⁹ cm ⁻³ ) continuous to the p-type channel region 19 . The p-type pillar layer 46 is formed in the inner region of the p-type channel region 19 of each unit cell 15. More specifically, the p-type pillar layer 46 is formed, for example, in a similar shape to the p-type channel region 19 (rectangular in plan view in the layout of FIG. 1(b)) in a substantially central region of the p-type channel region 19. You can leave it there. That is, the p-type pillar layer 46 is formed in a substantially columnar shape (substantially square columnar in the layout of FIG. 1(b)). As a result, the SiC substrate 2 has p-type pillar layers 46 arranged at appropriate pitches and an n-type drain region 20 sandwiched between adjacent p-type pillar layers 46 in the direction along the surface 21. arranged alternately.

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other forms.

For example, a configuration may be adopted in which the conductivity type of each semiconductor portion of the semiconductor device 1 described above is reversed. For example, in the semiconductor device 1, the p-type portion may be n-type, and the n-type portion may be p-type.

Further, the semiconductor employed in the semiconductor device 1 is not limited to SiC, and may be, for example, Si, GaN, diamond, or the like.

Further, the overlap portion 24 may be formed not only in the gate finger portion 4 but also in the active portion 3. For example, the overlap portion 24 may also be formed in the active portion 3 by covering only the periphery of the open end of the gate trench 9 to such an extent that the upper surface of each unit cell 15 is not hidden. In this case, if the overhang portion 33 is also formed in the gate trench 9, the same effect of improving the breakdown voltage as described above can be obtained. That is, the structure directly below the gate finger 8 is only one example of the effect of improving the breakdown voltage by the overhang part 33 of the present invention, and the structure is not limited to the gate finger part as long as the structure can achieve the same effect. .

In addition, various design changes can be made within the scope of the claims.

Furthermore, the following features can be extracted from the above-described embodiments.

A semiconductor layer including an active part and a gate finger part, and a MIS transistor formed in the active part, comprising a gate trench, a source region of a first conductivity type, and a source region of a second conductivity type along the side surface of the gate trench in this order. a MIS transistor including a channel region and a drain region of a first conductivity type; a plurality of first gate finger trenches configured by extensions of the gate trench in the gate finger portion; the gate trench and the first gate finger trench. a gate electrode embedded through a gate insulating film, a first bottom impurity region of a second conductivity type formed at least at the bottom of the first gate finger trench, and crossing the plurality of first gate finger trenches; a second conductivity type electric field relaxation region formed deeper than a bottom of the first gate finger trench between the gate finger electrically connected to the gate electrode and the first gate finger trench adjacent to each other; Semiconductor devices including the above are extracted.

According to this configuration, due to the presence of the electric field relaxation region, the pitch of the second conductivity type impurity region (the region including both the first bottom impurity region and the electric field relaxation region) in the gate finger portion is set to be higher than the pitch of the gate trench. It can be made narrower. As a result, the density of the second conductivity type impurity region can be increased in the gate finger portion, so that when a high voltage is applied, electric field concentration on the gate finger portion can be alleviated, and the occurrence of avalanche breakdown in the gate finger portion can be reduced. . As a result, avalanche breakdown can occur preferentially in the active portion, so high avalanche tolerance can be achieved.

The semiconductor device further includes a second gate finger trench formed between adjacent first gate finger trenches and integral with the gate trench, and the electric field relaxation region covers at least a bottom portion of the second gate finger trench. The second bottom impurity region may be formed in the second bottom impurity region.

According to this configuration, the depth of the second gate finger trench can be included in the depth of the electric field relaxation region, so that the first impurity region can be formed relatively shallowly from the bottom of the second gate finger trench. An electric field relaxation region deeper than the bottom of the gate finger trench can be easily formed.

In the semiconductor device, the second gate finger trench may extend along the first gate finger trench, or may extend in a direction crossing the first gate finger trench.

In the semiconductor device, a region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one of the first gate finger trenches to the other first gate finger trench, The semiconductor device further includes a second conductivity type surface impurity region formed shallower than a bottom of the first gate finger trench in the flat region. In this case, the electric field relaxation region may include a region formed so as to be continuous with the surface impurity region, or may include a region formed at intervals below the surface impurity region. Good too.

For example, if the field relaxation region is formed by ion implantation, its depth is controlled by the implant energy. The greater the implantation energy, the deeper the electric field relaxation region can be formed from the semiconductor surface. Since the implantation energy is determined depending on the target depth position, if a mask misalignment occurs before implantation, it may not be possible to form an impurity region at the target depth position. For example, when an impurity region is formed at the bottom of a trench, the energy conditions are determined according to the depth from the ion implantation surface (trench bottom surface) as a reference plane. However, if the mask is shifted laterally with respect to the trench, the depth reference plane will rise to the surface of the semiconductor (the opening end of the trench), and there is a risk that the impurity region will be formed only at a shallower position than the targeted position. be.

According to this configuration, since the electric field relaxation region is formed in the flat region of the semiconductor layer, even if the mask is misaligned, the height position of the reference plane for ion implantation hardly changes. Therefore, the electric field relaxation region can be formed at a targeted depth position with high probability.

In the semiconductor device, the MIS transistor further includes a second conductivity type region that is continuous with the channel region and is formed deeper than the electric field relaxation region.

According to this configuration, the effect of alleviating electric field concentration on the gate finger portion when high voltage is applied can be further enhanced.

Further, a semiconductor layer including an active part and a gate finger part, a MIS transistor formed in the active part, a gate trench formed at a predetermined pitch _P1 , and a first semiconductor layer along the side surface of the gate trench in order. The MIS transistor includes a source region of a conductivity type, a channel region _of a second conductivity type, and a drain region of a first conductivity type, and the gate finger portion is formed with a pitch _P2 narrower than a pitch P1 of the gate trench, a plurality of gate finger trenches integral with the gate trench; a gate electrode embedded in the gate trench and the gate finger trench via a gate insulating film; and a second conductive layer formed at least at the bottom of the gate finger trench. A semiconductor device is extracted that includes a bottom impurity region of the mold and a gate finger across the plurality of gate finger trenches and electrically connected to the gate electrode.

According to this configuration, the density of the second conductivity type impurity region can be increased in the gate finger portion, so that when a high voltage is applied, electric field concentration on the gate finger portion is alleviated, and occurrence of avalanche breakdown in the gate finger portion is reduced. be able to. As a result, avalanche breakdown can occur preferentially in the active portion, so high avalanche tolerance can be achieved.

In the semiconductor device, the gate trenches are formed in a lattice shape, and the gate finger trenches are formed by extensions of the gate trenches, and a plurality of first gate finger trenches are arranged at a lattice pitch of the gate trenches. and a second gate finger trench formed between adjacent first gate finger trenches.

In the semiconductor device, the MIS transistor further includes a second conductivity type region continuous with the channel region and formed deeper than the bottom impurity region.

According to this configuration, the effect of alleviating electric field concentration on the gate finger portion when high voltage is applied can be further enhanced.

In the semiconductor device, the bottom impurity region is electrically connected to the channel region.

According to this configuration, the potential of the bottom impurity region can be maintained at the potential of the channel region.

In the semiconductor device, the gate electrode has an overlap portion that overlaps the surface of the semiconductor layer at the upper edge of the trench in which the gate electrode is embedded, and the gate insulating film overlaps the surface of the semiconductor layer at the upper edge. It includes an overhang portion that protrudes toward the front. The trench includes the gate trench, the gate finger trench, the first gate finger trench, and the second gate finger trench.

According to this configuration, since the overhang portion is formed at the upper edge of the trench, the withstand voltage of the gate insulating film at the upper edge can be improved. Therefore, even if an electric field concentrates on the upper edge when the gate is turned on, dielectric breakdown of the gate insulating film at the upper edge can be prevented. As a result, reliability with respect to gate-on voltage can be improved.

In the semiconductor device, the upper edge includes an inclined surface connecting the surface of the semiconductor layer and the inner surface of the trench.

According to this configuration, the electric field applied to the upper edge when the gate is turned on can be dispersed within the inclined plane, thereby making it possible to alleviate electric field concentration.

In the semiconductor device, the upper edge includes a circular surface that connects the surface of the semiconductor layer and the inner surface of the trench.

According to this configuration, the electric field applied to the upper edge when the gate is turned on can be dispersed within a circular plane, thereby making it possible to alleviate electric field concentration.

In the semiconductor device, the gate insulating film on the bottom surface of the trench is thicker than the gate insulating film on the side surfaces of the trench.

According to this configuration, the capacitance of the capacitor formed by the gate electrode and the semiconductor layer facing each other via the gate insulating film on the bottom surface of the trench can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced. Further, since the withstand voltage of the gate insulating film on the bottom surface of the trench can be improved, dielectric breakdown of the gate insulating film when the gate is turned off can be prevented.

In the semiconductor device, the gate insulating film further includes a thicker portion on the surface of the semiconductor layer than the gate insulating film on a side surface of the trench.

According to this configuration, the capacitance of the capacitor formed by the semiconductor layer and the gate electrode (overlap portion) facing each other via the gate insulating film on the surface of the semiconductor layer can be reduced. As a result, the capacitance of the entire gate (gate capacitance) can be reduced.

In the semiconductor device, a lower edge of the trench includes a circular surface connecting a side surface and a bottom surface of the trench.

According to this configuration, the electric field applied to the lower edge when the gate is turned off can be dispersed within the circular plane, thereby alleviating electric field concentration.

1 Semiconductor device 2 SiC substrate 3 Active part 4 Gate finger part 8 Gate finger 9 Gate trench 10 Gate finger trench 11 First gate finger trench 12 Second gate finger trench 17 N ⁺ type source region 19 P type channel region 20 N type drain Region 22 Gate electrode 23 Gate insulating film 24 Overlapping part 25 Side part (of the gate insulating film) 26 Bottom part (of the gate insulating film) 27 Surface part (of the gate insulating film) 28 P-type region 32 Upper edge 33 Overhang part 34 Inclined surface 35 Circular surface 36 P-type region 37 Flat region 38 Bottom p-type region 39 Circular surface 41 P-type protruding region 42 P-type floating region 43 P-type region 45 Second gate finger trench 46 P-type pillar layer

Claims (22)

a semiconductor layer including an active part and a gate finger part;
The MIS transistor is formed in the active part, and includes a gate trench, a first conductivity type source region, a second conductivity type channel region, and a first conductivity type drain region along side surfaces of the gate trench in this order. an MIS transistor including;
a first impurity region of a second conductivity type formed so as to be continuous with the channel region and extending in the drain region to a position deeper than the channel region and the gate trench toward the back surface side of the semiconductor layer;
a plurality of first gate finger trenches configured by extensions of the gate trench in the gate finger portion;
a gate electrode embedded in the gate trench and the first gate finger trench via a gate insulating film;
a first bottom impurity region of a second conductivity type formed at least at the bottom of the first gate finger trench;
a gate finger electrically connected to the gate electrode;
an electric field relaxation region of a second conductivity type formed deeper than the bottom of the first gate finger trench between the adjacent first gate finger trenches;
A semiconductor device, wherein a first depth, which is the depth of the deepest part of the electric field relaxation region, is equal to or smaller than a second depth, which is the depth of the first impurity region. further comprising a second gate finger trench formed between adjacent first gate finger trenches and integral with the gate trench;
2. The semiconductor device according to claim 1, wherein the electric field relaxation region further includes a second bottom impurity region of a second conductivity type formed at least at the bottom of the second gate finger trench. 3. The semiconductor device according to claim 2, wherein the second gate finger trench extends along the first gate finger trench. A region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench,
The region between adjacent first gate finger trenches further includes a surface impurity region of a second conductivity type formed shallower than a bottom of the first gate finger trench in the flat region,
2. The semiconductor device according to claim 1, wherein the electric field relaxation region includes a region formed so as to be continuous with the surface impurity region. A region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench,
The region between adjacent first gate finger trenches further includes a surface impurity region of a second conductivity type formed shallower than a bottom of the first gate finger trench in the flat region,
2. The semiconductor device according to claim 1, wherein the electric field relaxation region includes a region spaced apart below the surface impurity region. A region between adjacent first gate finger trenches includes a flat region where the surface of the semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench,
The region between the adjacent first gate finger trenches further includes a second impurity region of a second conductivity type formed at the same depth as the bottom of the first bottom impurity region in the flat region;
2. The semiconductor device according to claim 1, wherein the region between adjacent first gate finger trenches is completely covered by the second impurity region. The MIS transistor includes a channel contact region of a second conductivity type formed adjacent to the source region in a unit cell between adjacent gate trenches, and a region inside the channel region of the unit cell. further comprising a pillar layer of a second conductivity type,
7. The pillar layer is formed so as to be continuous with the channel region, and extends in the drain region toward a back surface side of the semiconductor layer to a deeper position than the channel region and the gate trench. The semiconductor device according to any one of the above. The gate finger part surrounds the active part,
The semiconductor device further includes a source metal covering the active portion and a gate pad,
A removal region surrounding the central portion of the source metal along the gate finger portion is formed in a peripheral portion of the source metal,
the gate pad is formed in the removed region,
8. The semiconductor device according to claim 1, wherein the gate finger extends from the gate pad to the entire removal region. 9. The semiconductor device according to claim 8, wherein the source metal, the gate pad, and the gate finger are made of aluminum. 10. The semiconductor device according to claim 8, wherein the pair of gate fingers are formed in a symmetrical shape with respect to the gate pad. The first gate finger trench includes an upper edge that is an intersection between a side surface of the first gate finger trench and a surface of the semiconductor layer,
11. The semiconductor device according to claim 1, wherein the upper edge includes an inclined surface connecting a surface of the semiconductor layer and an inner surface of the first gate finger trench. The first gate finger trench includes an upper edge that is an intersection between a side surface of the first gate finger trench and a surface of the semiconductor layer,
11. The semiconductor device according to claim 1, wherein the upper edge includes a circular surface connecting the surface of the semiconductor layer and the inner surface of the first gate finger trench. 11. The semiconductor device according to claim 1, wherein the gate insulating film on the bottom of the first gate finger trench is thicker than the gate insulating film on the side surface of the first gate finger trench. 11. The gate insulating film of the first gate finger trench further includes a portion on the surface of the semiconductor layer that is thicker than the gate insulating film on the side surface of the first gate finger trench. The semiconductor device according to item 1. the first gate finger trench includes a lower edge at the bottom of the first gate finger trench;
11. The lower edge of the first gate finger trench includes a circular surface connecting a side surface of the first gate finger trench and a bottom of the first gate finger trench. The semiconductor device described. 13. The semiconductor device according to claim 1, wherein the semiconductor layer includes a wide bandgap semiconductor. 17. The semiconductor device according to claim 16, wherein the semiconductor layer is a SiC semiconductor layer. 18. The semiconductor device according to claim 1, wherein avalanche breakdown occurs preferentially in the active portion than in the gate finger portion. a SiC semiconductor layer including an active part and a gate finger part;
The MIS transistor is formed in the active part, and includes a gate trench, a first conductivity type source region, a second conductivity type channel region, and a first conductivity type drain region along side surfaces of the gate trench in this order. an MIS transistor including;
a first impurity region of a second conductivity type formed so as to be continuous with the channel region and extending in the drain region to a position deeper than the channel region and the gate trench toward the back surface side of the SiC semiconductor layer;
a plurality of first gate finger trenches configured by extensions of the gate trench in the gate finger portion;
a gate electrode embedded in the gate trench and the first gate finger trench via a gate insulating film;
a first bottom impurity region of a second conductivity type formed at least at the bottom of the first gate finger trench;
a gate finger electrically connected to the gate electrode;
an electric field relaxation region of a second conductivity type formed deeper than the bottom of the first gate finger trench between the adjacent first gate finger trenches;
The first depth, which is the depth of the deepest part of the electric field relaxation region, is the same as or smaller than the second depth, which is the depth of the first impurity region,
A region between adjacent first gate finger trenches includes a flat region where the surface of the SiC semiconductor layer is continuous from one first gate finger trench to the other first gate finger trench,
The region between the adjacent first gate finger trenches further includes a second impurity region of a second conductivity type formed at the same depth as the bottom of the first bottom impurity region in the flat region;
the region between adjacent first gate finger trenches is completely covered by the second impurity region;
The MIS transistor includes a channel contact region of a second conductivity type formed adjacent to the source region in a unit cell between adjacent gate trenches, and a region inside the channel region of the unit cell. further comprising a pillar layer of a second conductivity type,
The pillar layer is formed so as to be continuous with the channel region, and extends in the drain region toward a back surface side of the SiC semiconductor layer to a position deeper than the channel region and the gate trench. The gate finger part surrounds the active part,
The semiconductor device further includes a source metal covering the active portion and a gate pad,
A removal region surrounding the central portion of the source metal along the gate finger portion is formed in a peripheral portion of the source metal,
the gate pad is formed in the removed region,
20. The semiconductor device according to claim 19, wherein the gate finger extends from the gate pad to the entire removal region. 21. The semiconductor device according to claim 20 , wherein the gate pad and the gate finger are made of aluminum. 22. The semiconductor device according to claim 20 , wherein the pair of gate fingers are formed in a symmetrical shape with respect to the gate pad.

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