JP2018056380A - Switching element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for relaxing an electric field concentration in the circumference of a bottom region.SOLUTION: A switching element comprises: a semiconductor substrate; a trench provided on an upper surface of the semiconductor substrate; a gate insulation film covering an inner surface of the trench; and a gate electrode that is arranged in the trench, and is insulated from the semiconductor substrate by the gate insulation film. The semiconductor substrate comprises: an n-type source region contacted to the gate insulation film; a p-type body region contacted to the gate insulation film in a lower side of the source region; an n-type drift region that is contacted to the gate insulation film on the lower side of the body region, and is separated from the source region by the body region; a p-type bottom region contacted to the gate insulation film in a bottom surface of the trench; and a p-type connection region that is contacted to the gate insulation film on a side surface of the trench, and connects with the body region and the bottom region. The thickness of a connection region becomes thinner toward a body region side end part from the bottom region side end part.SELECTED DRAWING: Figure 2

Description

  The present specification discloses a switching element.

  Patent Document 1 discloses a switching element having a semiconductor substrate in which a trench is provided on an upper surface. A gate insulating film that covers the inner surface of the trench and a gate electrode that is insulated from the semiconductor substrate by the gate insulating film are disposed in the trench. The semiconductor substrate has an n-type source region, a p-type body region, and an n-type drift region. The source region is in contact with the gate insulating film. The body region is in contact with the gate insulating film below the source region. The drift region is in contact with the gate insulating film below the body region. The semiconductor substrate also has a p-type bottom region extending along the bottom surface of the trench and a p-type connection region extending along the side surface of the trench. The connection region connects the body region and the bottom region. The drift region described above is in contact with the gate insulating film in a range where no connection region exists.

  When the switching element is turned off, a depletion layer extends from the body region and the bottom region into the drift region. The depletion layer extending from the bottom region suppresses concentration of the electric field on the gate insulating film. In addition, the connection region is depleted in the process of turning off the switching element, so that the bottom region is electrically isolated from the body region. As a result, the potential of the bottom region becomes floating. This suppresses a high potential difference between the bottom region and the back surface of the semiconductor substrate.

  When this switching element is turned on, a channel is formed in the body region, and the depletion layer extending in the drift region contracts to turn on the switching element. In the process, the depletion layer in the connection region also contracts, and the bottom region is electrically connected to the body region through the connection region. Then, holes are supplied from the body region to the bottom region through the connection region. As a result, the depletion layer that has spread from the bottom region to the drift region contracts toward the bottom region. For this reason, the resistance of the drift region decreases in a short time when the switching element is turned on. Therefore, in this switching element, it is difficult for loss to occur.

JP 2007-242852 A

  In the switching element of Patent Document 1, electric field concentration occurs around the bottom region when turned off. The present specification discloses a technique for mitigating electric field concentration around a bottom region in a switching element having a connection region and a bottom region.

  In the simulation performed by the present inventors, in the structure of the switching element of Patent Document 1, an electric field distribution result was obtained as shown in FIG. FIG. 7 shows a cross section of a range including the gate electrode 126, the gate insulating film 124, the source region 130, the body region 132, the bottom region 136, the connection region 138, and the drift region 134. FIG. 7 shows a state when the switching element is off. In FIG. 7, the broken lines indicate equipotential lines. In FIG. 7, the semiconductor region in which equipotential lines are distributed is depleted. In FIG. 7, a hatched area with dots indicates a semiconductor area that is not depleted (hereinafter referred to as a non-depleted area). As shown in FIG. 7, when the connection region 138 is depleted, the lower portion of the connection region 138 (the portion on the bottom region 136 side) is located above the connection region 138 due to a potential difference generated in the semiconductor substrate. Compared with the portion (the portion on the body region 132 side), it is easily depleted. Therefore, in the switching element of Patent Document 1, as shown in FIG. 7, a depleted region 138 a and a non-depleted region 138 b exist in the connection region 138. The non-depleted region 138b in the connection region 138 suppresses electric field concentration in the upper portion of the connection region 138 (portion near the lower end of the gate electrode 126). On the other hand, in the structure of the switching element of Patent Document 1, electric field concentration occurs in the bottom region 136 (region 210 in FIG. 7).

  A switching element disclosed in this specification includes a semiconductor substrate, a trench provided on an upper surface of the semiconductor substrate, a gate insulating film covering an inner surface of the trench, and the gate insulating film disposed in the trench. And a gate electrode insulated from the semiconductor substrate. The semiconductor substrate includes an n-type source region in contact with the gate insulating film, a p-type body region in contact with the gate insulating film below the source region, and the lower side of the body region. An n-type drift region in contact with the gate insulating film and separated from the source region by the body region; a p-type bottom region in contact with the gate insulating film at a bottom surface of the trench; A p-type connection region that is in contact with the gate insulating film on a side surface and connects the body region and the bottom region is provided. The thickness of the connection region decreases as it goes from the bottom region side end to the body region side end.

  Note that the thickness of the connection region means the dimension of the connection region in a direction perpendicular to the side surface of the trench.

  In the switching element described above, the thickness of the connection region decreases from the bottom region side end toward the body region side end. Thus, if the thickness of the connection region on the body region side is thin, the portion of the connection region on the body region side is likely to be depleted. For this reason, the entire connection region 38 is depleted. FIG. 6 shows a simulation result performed in the structure of the switching element disclosed in this specification. Note that FIG. 6 illustrates an example of the structure of the switching element disclosed in this specification for the sake of explanation, and the structure of the switching element disclosed in this specification is not limited to the structure of FIG. . 6 shows a cross section of a range including the gate electrode 26, the gate insulating film 24, the source region 30, the body region 32, the bottom region 36, the connection region 38, and the drift region 34. As illustrated in FIG. 6, electric field concentration occurs in the region 100 near the lower end of the gate electrode 26. As a result, electric field concentration occurs in the region 100 near the lower end of the gate electrode 26 and the bottom region 36 (region 110 in FIG. 6). As described above, according to the switching element disclosed in the present specification, electric field concentration can be distributed and generated. Thereby, compared with the case where an electric field concentrates on one place, the electric field in each electric field concentration part can be suppressed.

The top view of MOSFET10. Sectional drawing of MOSFET10 in the II-II line | wire of FIG. Sectional drawing of MOSFET10 in the III-III line of FIG. Sectional drawing of MOSFET10 in the IV-IV line | wire of FIG. The graph which shows the proof pressure of MOSFET10. Sectional drawing which shows the state (electric field distribution) of the trench vicinity when MOSFET10 is OFF. Sectional drawing which shows the state (electric field distribution) of the trench vicinity when the conventional MOSFET is OFF.

  1 to 4 show a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 10 of the embodiment. The MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, illustration of electrodes and insulating layers on the upper surface 12 a of the semiconductor substrate is omitted for easy viewing. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as an x direction, a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as a y direction, and a thickness direction of the semiconductor substrate 12 is referred to as a z direction. The semiconductor substrate 12 is made of SiC (silicon carbide).

  As shown in FIGS. 2 to 4, a plurality of trenches 22 are provided on the upper surface 12 a of the semiconductor substrate 12. As shown in FIG. 1, each trench 22 extends linearly in the y direction. The plurality of trenches 22 are arranged at intervals in the x direction. As shown in FIGS. 2 to 4, the inner surface of each trench 22 is covered with a gate insulating film 24. The gate insulating film 24 includes a bottom insulating film 24a and a side insulating film 24b. The bottom insulating film 24 a is provided on the bottom of the trench 22. The bottom insulating film 24a covers the bottom surface of the trench 22 and the side surface near the bottom surface. The side surface insulating film 24b covers the side surface of the trench 22 above the bottom insulating film 24a. The thickness of the bottom insulating film 24a (that is, the width between the upper surface and the lower surface of the bottom insulating film 24a (in other words, the distance between the lower end of the gate electrode 26 and the bottom surface of the trench 22)) is the thickness of the side insulating film 24b. (That is, the distance between the side surface of the trench 22 and the side surface of the gate electrode 26). A gate electrode 26 is disposed in each trench 22. Each gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24. The upper surface of each gate electrode 26 is covered with an interlayer insulating film 28.

  An upper electrode 70 is disposed on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 70 is in contact with the upper surface 12 a of the semiconductor substrate 12 at a portion where the interlayer insulating film 28 is not provided. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A lower electrode 72 is disposed on the lower surface 12 b of the semiconductor substrate 12. The lower electrode 72 is in contact with the lower surface 12 b of the semiconductor substrate 12.

  As shown in FIGS. 2 to 4, a plurality of source regions 30, a body region 32, a drift region 34, a drain region 35, a plurality of bottom regions 36, and a plurality of connection regions 38 are provided inside the semiconductor substrate 12. Yes.

  Each source region 30 is an n-type region. Each source region 30 is disposed at a position exposed on the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 70. Each source region 30 is in contact with the side surface insulating film 24b on the side surface in the short direction of the trench 22 (the side surface located at the end portion in the short direction and extending along the y direction). Each source region 30 is in contact with the side insulating film 24 b at the upper end of the trench 22.

  Body region 32 is a p-type region. The body region 32 is in contact with each source region 30. The body region 32 extends from a range between the two source regions 30 to the lower side of each source region 30. The body region 32 has a high concentration region 32a and a low concentration region 32b. The high concentration region 32a has a higher p-type impurity concentration than the low concentration region 32b. The high concentration region 32 a is disposed in a range sandwiched between the two source regions 30. The high concentration region 32 a is in ohmic contact with the upper electrode 70. The low concentration region 32 b is in contact with the side insulating film 24 b on the side surface in the short direction of the trench 22. That is, the low concentration region 32 b is in contact with the side insulating film 24 b below the source region 30. As shown in FIGS. 1 and 4, the low concentration region 32 b is in a range adjacent to the side surface in the longitudinal direction of the trench 22 (the side surface located at the end in the longitudinal direction and extending along the x direction). Also arranged. The low concentration region 32 b is in contact with the side insulating film 24 b on the side surface in the longitudinal direction of the trench 22. The lower end of the body region 32 (that is, the lower end of the low concentration region 32b) is disposed above the lower end of the gate electrode 26 (that is, the upper surface of the bottom insulating film 24a).

  The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32 and is separated from the source region 30 by the body region 32. As shown in FIG. 3, the drift region 34 is in contact with the side insulating film 24 b and the bottom insulating film 24 a on the lateral side surface of the trench 22. That is, the drift region 34 is in contact with the side surface insulating film 24 b and the bottom insulating film 24 a below the body region 32.

  The drain region 35 is an n-type region. The drain region 35 has a higher n-type impurity concentration than the drift region 34. The drain region 35 is disposed below the drift region 34. The drain region 35 is exposed on the lower surface 12 b of the semiconductor substrate 12. The drain region 35 is in ohmic contact with the lower electrode 72.

  Each bottom region 36 is a p-type region. Each bottom region 36 is arranged in a range exposed on the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with the bottom insulating film 24 a at the bottom surface of the corresponding trench 22. As shown in FIG. 4, each bottom region 36 extends long in the y direction along the bottom surface of the corresponding trench 22. Each bottom region 36 is in contact with the bottom insulating film 24 a over the entire bottom surface of the corresponding trench 22. As shown in FIGS. 2 and 3, the periphery of each bottom region 36 is surrounded by a drift region 34. Each bottom region 36 is separated from the body region 32 by a drift region 34 except for a portion where a connection region 38 described later is formed.

  Connection region 38 is a p-type region. As shown in FIG. 1, the connection region 38 is provided along the lateral side surface of the trench 22. As shown in FIG. 2, the connection region 38 extends downward from the body region 32 along the lateral side surface of the trench 22. A plurality of connection regions 38 are disposed on the lateral side surface of the trench 22. The lower end of the connection region 38 is connected to the bottom region 36. That is, the body region 32 and the bottom region 36 are connected by the connection region 38. The thickness of the connection region 38 (the dimension of the connection region 38 in the direction perpendicular to the side surface of the trench 22) decreases from the bottom region 36 side toward the body region 32 side. The connection region 38 has a p-type impurity concentration lower than that of the body region 32 and the bottom region 36.

  Next, the operation of the MOSFET 10 will be described. When the MOSFET 10 is used, the MOSFET 10, a load (for example, a motor), and a power source are connected in series. A power supply voltage (about 800 V in this embodiment) is applied to the series circuit of the MOSFET 10 and the load. The power supply voltage is applied in such a direction that the drain side (lower electrode 72) of the MOSFET 10 has a higher potential than the source side (upper electrode 70). When a gate-on potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel (inversion layer) is formed in the body region 32 (low concentration region 32b) in the range in contact with the side surface insulating film 24b, and the MOSFET 10 is turned on. When a gate-off potential (potential below the gate threshold) is applied to the gate electrode 26, the channel disappears and the MOSFET 10 is turned off. Hereinafter, the operation of the MOSFET 10 when it is turned off and when it is turned on will be described in detail.

  When the MOSFET 10 is turned off, the potential of the gate electrode 26 is lowered from the gate-on potential to the gate-off potential. Then, the channel disappears and the potential of the lower electrode 72 increases. The potential of the lower electrode 72 rises to a potential that is higher than the upper electrode 70 by a power supply voltage (ie, about 800 V). In the process of increasing the potential of the lower electrode 72, the potential of the bottom region 36 slightly increases due to capacitive coupling between the bottom region 36 and the lower electrode 72. Then, holes flow from the bottom region 36 to the upper electrode 70 through the connection region 38 and the body region 32. While the holes are flowing in this way, the increase in the potential of the bottom region 36 is suppressed, and the potential of the bottom region 36 is maintained at a potential slightly higher than the potential of the upper electrode 70.

  As the potential of the lower electrode 72 increases, the potentials of the drain region 35 and the drift region 34 also increase. When the potential of the drift region 34 increases, a potential difference is generated between the body region 32 and the drift region 34. For this reason, a reverse voltage is applied to the pn junction at the interface between the body region 32 and the drift region 34. Therefore, a depletion layer extends from the body region 32 to the drift region 34. Further, when the potential of the drift region 34 increases, a potential difference is generated between the bottom region 36 and the drift region 34. For this reason, a reverse voltage is applied to the pn junction at the interface between the bottom region 36 and the drift region 34. Therefore, a depletion layer extends from the bottom region 36 to the drift region 34.

  Further, when the potential of the drift region 34 increases, a reverse voltage is also applied to the pn junction at the interface between the connection region 38 and the drift region 34. Since the p-type impurity concentration in the connection region 38 is low, a depletion layer spreads from the pn junction into the connection region 38. Here, in the drift region 34, the potential is distributed so that the potential becomes higher toward the lower side. For this reason, the voltage applied to the upper part of the pn junction at the boundary between the connection region 38 and the drift region 34 is lower than that of the lower part. For this reason, the depletion layer is less likely to spread in the upper part of the connection region 38 than in the lower part of the connection region 38. On the other hand, as described above, the thickness of the connection region 38 becomes thinner from the bottom region 36 side (lower side) toward the body region 32 side (upper side). Therefore, as shown in FIG. 6, the upper portion of the connection region 38 where the depletion layer is difficult to spread is also completely depleted. As a result, almost the entire connection region 38 is depleted. As the connection region 38 is depleted, the bottom region 36 is electrically isolated from the upper electrode 70.

  When the bottom region 36 is electrically separated from the body region 32, the flow of holes from the bottom region 36 toward the upper electrode 70 stops, and the potential of the bottom region 36 becomes floating. For this reason, the potential of the bottom region 36 increases as the potential of the lower electrode 72 increases. Thus, the potential difference between the bottom region 36 and the lower electrode 72 is prevented from being excessively increased by increasing the potential of the bottom region 36. As described above, in the MOSFET 10, almost the entire region in the connection region 38 is depleted, so that electric field concentration occurs in the vicinity of the lower end of the gate electrode 26 as shown in FIG. That is, the electric field can be dispersed in the vicinity of the lower end of the gate electrode 26 and the bottom region 36. In other words, electric field peaks can be formed at two locations, the vicinity of the lower end of the gate electrode 26 and the bottom region 36. For this reason, compared with the case where an electric field concentrates on one place, the electric field in each electric field concentration part can be suppressed. Therefore, the MOSFET 10 has a high breakdown voltage. FIG. 5 shows the result of a withstand voltage simulation performed on the MOSFET 10 of this embodiment and the MOSFET of the conventional structure (structure of FIG. 7). It has been found that the breakdown voltage of the MOSFET 10 of this embodiment (shown by a solid line in the graph of FIG. 5) is higher than that of the conventional MOSFET shown in FIG. When the potential of the lower electrode 72 rises to a potential higher than the upper electrode 70 by the power supply voltage, the turn-off of the MOSFET 10 is completed.

  When the MOSFET 10 is turned on, the potential of the gate electrode 26 is raised from the gate-off potential to the gate-on potential. Then, electrons are attracted to the body region 32 in a range in contact with the gate insulating film 24 on the lateral side surface of the trench 22. As a result, the body region 32 in this range is inverted from p-type to n-type, and a channel is formed. The source region 30 and the drift region 34 are connected by the channel. As a result, the potentials of the drift region 34, the drain region 35, and the lower electrode 72 are lowered. When the potential of the drift region 34 decreases, the reverse voltage applied to the pn junction at the interface between the body region 32 and the drift region 34 decreases. For this reason, the depletion layer extending from the body region 32 to the drift region 34 contracts toward the body region 32 and disappears. As a result, electrons flow from the upper electrode 70 to the lower electrode 72 via the source region 30, the channel, the drift region 34, and the drain region 35. That is, the MOSFET 10 is turned on.

  Further, in the process in which the potential of the drift region 34 decreases, the depletion layer spreading in the connection region 38 contracts toward the drift region 34 and disappears. As a result, the bottom region 36 is electrically connected to the body region 32 via the connection region 38. Then, holes flow from the upper electrode 70 to the bottom region 36 through the body region 32 and the connection region 38. When holes are supplied to the bottom region 36, the depletion layer extending from the bottom region 36 to the drift region 34 contracts toward the bottom region 36 and disappears. For this reason, the resistance of the drift region 34 decreases, and electrons easily flow from the upper electrode 70 toward the lower electrode 72. For this reason, it is difficult for loss to occur in the drift region 34.

  As described above, in the MOSFET 10 of this embodiment, almost the entire connection region 38 is depleted at the time of turn-off. That is, the non-depleted region does not remain in the connection region 38 when the MOSFET 10 is turned off. Therefore, as shown in FIG. 6, an electric field concentration portion can be formed even in the vicinity of the lower end of the gate electrode 26. The electric field can be distributed in the vicinity of the lower end of the gate electrode 26 and in the vicinity of the bottom region 36. For this reason, the MOSFET 10 has a high breakdown voltage.

  In the present embodiment, the connection region 38 extends downward from the body region 32 along the lateral side surface of the trench 22, but extends downward from the body region along the longitudinal side surface of the trench. It may extend and be connected to the bottom region. Even in this case, the electric field concentration around the bottom region can be reduced by reducing the thickness of the connection region from the bottom region side toward the body region side.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: MOSFET
12: Semiconductor substrate 22: Trench 24: Gate insulating film 26: Gate electrode 28: Interlayer insulating film 30: Source region 32: Body region 34: Drift region 35: Drain region 36: Bottom region 38: Connection region 70: Upper electrode 72 : Lower electrode

Claims (1)

A switching element,
A semiconductor substrate;
A trench provided on an upper surface of the semiconductor substrate;
A gate insulating film covering the inner surface of the trench;
A gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film;
With
The semiconductor substrate is
An n-type source region in contact with the gate insulating film;
A p-type body region in contact with the gate insulating film under the source region;
An n-type drift region that is in contact with the gate insulating film under the body region and is separated from the source region by the body region;
A p-type bottom region in contact with the gate insulating film at the bottom of the trench;
A p-type connection region that is in contact with the gate insulating film on the side surface of the trench and connects the body region and the bottom region;
With
The thickness of the connection region becomes thinner from the bottom region side end toward the body region side end,
Switching element.