CN205428920U - 一种存储盘芯片阶梯式多叠层封装结构 - Google Patents

一种存储盘芯片阶梯式多叠层封装结构 Download PDF

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CN205428920U
CN205428920U CN201620182580.5U CN201620182580U CN205428920U CN 205428920 U CN205428920 U CN 205428920U CN 201620182580 U CN201620182580 U CN 201620182580U CN 205428920 U CN205428920 U CN 205428920U
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倪黄忠
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Shenzhen Shi Creative Electronics Co.,Ltd.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

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Abstract

本实用新型公开了一种存储盘芯片阶梯式多叠层封装结构，该封装结构包括：置于最底层的PCB基板层、存储盘芯片晶元层、假片，所述存储盘芯片晶元层设置在PCB基板层表面，它分为两部分，每个部分都是由多个晶元层呈阶梯式层叠在一起，其中下部分晶元层与PCB基板层接触，上部分晶元层置于下部分晶元层上表面右侧区域，上部分晶元层与下部分晶元层呈反向放置，其右侧部分与所述PCB基板层之间形成间隙；所述假片置于所述上部分晶元层与所述PCB基板层之间的间隙处。本实用新型将晶元层设置成阶梯式层叠在一起，使金手指之间的连接距离变短，减少信号损耗，同时也可以节约成本。

Description

一种存储盘芯片阶梯式多叠层封装结构
技术领域
本实用新型涉及芯片封装，具体的说是涉及一种存储盘芯片阶梯式多叠层封装结构。
背景技术
芯片堆叠技术可让两芯片更为靠近，由此实现两芯片间更快数据传输及消耗较少的能量。存储芯片可堆叠一起，以获得具有更大储存空间的存储盘模块。传统上，施加在存储盘芯片堆叠中的信号是流经导线(wires)，长导线会造成信号延迟，且会占据较多的空间，导致制作出大的存储盘芯片堆叠。
实用新型内容
针对现有技术中的不足，本实用新型要解决的技术问题在于提供了一种存储盘芯片阶梯式多叠层封装结构。
为解决上述技术问题，本实用新型通过以下方案来实现：一种存储盘芯片阶梯式多叠层封装结构，该封装结构包括：
置于最底层的PCB基板层；
其特征在于，封装结构还包括：
存储盘芯片晶元层，所述存储盘芯片晶元层设置在PCB基板层表面，它分为两部分，每个部分都是由多个晶元层呈阶梯式层叠在一起，其中下部分晶元层与PCB基板层接触，上部分晶元层置于下部分晶元层上表面右侧区域，上部分晶元层与下部分晶元层呈反向放置，其右侧部分与所述PCB基板层之间形成间隙；
假片，所述假片置于所述上部分晶元层与所述PCB基板层之间的间隙处。
进一步的，所述假片的上下表面分别与所述上部分晶元层下表面、所述PCB基板层上表面接触。
进一步的，所述PCB基板层上表面设置有基板层金手指，基板层金手指设置有两处，分居于存储盘芯片晶元层两边。
进一步的，存储盘芯片晶元层的每个晶元层设置有晶元层金手指，晶元层金手指设置在晶元层的阶梯处，每个相邻的晶元层金手指通过金线连接。
进一步的，基板层金手指通过金线连接晶元层金手指，其中，左侧的基板层金手指连接在最底部的下部分晶元层上的晶元层金手指，右侧的基板层金手指连接在最底部的上部分晶元层上的晶元层金手指。
相对于现有技术，本实用新型的有益效果是：本实用新型将晶元层设置成阶梯式层叠在一起，使金手指之间的连接距离变短，减少信号损耗，同时也可以节约成本。
附图说明
图1为本实用新型多叠层封装结构侧边截面图。
图2为图1右侧的放大图。
图3为图1左侧的放大图。
附图中标记：PCB基板层1、存储盘芯片晶元层2、假片3、基板层金手指4、金线5、晶元层金手指6。
具体实施方式
下面结合附图对本实用新型的优选实施例进行详细阐述，以使本实用新型的优点和特征能更易于被本领域技术人员理解，从而对本实用新型的保护范围做出更为清楚明确的界定。
请参照附图1~3，本实用新型的一种存储盘芯片阶梯式多叠层封装结构，该封装结构包括：
置于最底层的PCB基板层1，PCB基板层1为现有技术中的PCB基板。
封装结构还包括：存储盘芯片晶元层2、假片3。所述存储盘芯片晶元层2设置在PCB基板层1表面，它分为两部分，每个部分都是由多个晶元层呈阶梯式层叠在一起，其中下部分晶元层与PCB基板层1接触，上部分晶元层置于下部分晶元层上表面右侧区域，上部分晶元层与下部分晶元层呈反向放置，其右侧部分与所述PCB基板层1之间形成间隙，所述假片3置于所述上部分晶元层与所述PCB基板层1之间的间隙处，所述假片2的上下表面分别与所述上部分晶元层下表面、所述PCB基板层1上表面接触。所述PCB基板层1上表面设置有基板层金手指4，基板层金手指4设置有两处，分居于存储盘芯片晶元层2两边。存储盘芯片晶元层2的每个晶元层设置有晶元层金手指6，晶元层金手指6设置在晶元层的阶梯处，每个相邻的晶元层金手指6通过金线5连接。基板层金手指4通过金线连接晶元层金手指6，其中，左侧的基板层金手指4连接在最底部的下部分晶元层上的晶元层金手指6，右侧的基板层金手指4连接在最底部的上部分晶元层上的晶元层金手指6。
按照上述结构所设计的存储盘芯片封装结构制作成本低，本实用新型封装结构将晶元层设置成阶梯式层叠在一起，使金手指之间的连接距离变短，减少信号损耗，同时也可以节约成本。
以上所述仅为本实用新型的优选实施方式，并非因此限制本实用新型的专利范围，凡是利用本实用新型说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本实用新型的专利保护范围内。

Claims (5)

1.一种存储盘芯片阶梯式多叠层封装结构，该封装结构包括：
置于最底层的PCB基板层（1）；
其特征在于，封装结构还包括：
存储盘芯片晶元层（2），所述存储盘芯片晶元层（2）设置在PCB基板层（1）表面，它分为两部分，每个部分都是由多个晶元层呈阶梯式层叠在一起，其中下部分晶元层与PCB基板层（1）接触，上部分晶元层置于下部分晶元层上表面右侧区域，上部分晶元层与下部分晶元层呈反向放置，其右侧部分与所述PCB基板层（1）之间形成间隙；
假片（3），所述假片（3）置于所述上部分晶元层与所述PCB基板层（1）之间的间隙处。
2.根据权利要求1所述的一种存储盘芯片阶梯式多叠层封装结构，其特征在于：所述假片（2）的上下表面分别与所述上部分晶元层下表面、所述PCB基板层（1）上表面接触。
3.根据权利要求1所述的一种存储盘芯片阶梯式多叠层封装结构，其特征在于：所述PCB基板层（1）上表面设置有基板层金手指（4），基板层金手指（4）设置有两处，分居于存储盘芯片晶元层（2）两边。
4.根据权利要求3所述的一种存储盘芯片阶梯式多叠层封装结构，其特征在于：存储盘芯片晶元层（2）的每个晶元层设置有晶元层金手指（6），晶元层金手指（6）设置在晶元层的阶梯处，每个相邻的晶元层金手指（6）通过金线（5）连接。
5.根据权利要求4所述的一种存储盘芯片阶梯式多叠层封装结构，其特征在于：基板层金手指（4）通过金线连接晶元层金手指（6），其中，左侧的基板层金手指（4）连接在最底部的下部分晶元层上的晶元层金手指（6），右侧的基板层金手指（4）连接在最底部的上部分晶元层上的晶元层金手指（6）。
CN201620182580.5U 2016-03-10 2016-03-10 一种存储盘芯片阶梯式多叠层封装结构 Active CN205428920U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252344A (zh) * 2016-09-12 2016-12-21 深圳市时创意电子有限公司 一种同基板兼容多种接口的多层叠加存储盘及其封装工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252344A (zh) * 2016-09-12 2016-12-21 深圳市时创意电子有限公司 一种同基板兼容多种接口的多层叠加存储盘及其封装工艺
CN106252344B (zh) * 2016-09-12 2019-01-04 深圳市时创意电子有限公司 一种同基板兼容多种接口的多层叠加存储盘及其封装工艺

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