CN205050830U - 半导体器件和封装体 - Google Patents

半导体器件和封装体 Download PDF

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Publication number
CN205050830U
CN205050830U CN201520748454.7U CN201520748454U CN205050830U CN 205050830 U CN205050830 U CN 205050830U CN 201520748454 U CN201520748454 U CN 201520748454U CN 205050830 U CN205050830 U CN 205050830U
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lead
wire
nude film
packaging
lead frame
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L·切里亚尼
P·克雷马
A·米诺蒂
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STMicroelectronics SRL
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STMicroelectronics SRL
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • CCHEMISTRY; METALLURGY
    • C22METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22CALLOYS
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Abstract

本申请涉及半导体器件和封装体。公开了一种半导体器件,包括:半导体材料的裸片;引线框,限定被设计用于承载裸片的支撑板以及被设计为电耦合到所述裸片的引线;以及封装件,具有被设计用于对所述裸片进行密封的密封材料,并且部分的引线从封装件中伸出。所述引线框具有包括百分比在1%和1.5%之间的硅的铝合金作为构成材料。根据本实用新型的方案,可以避免中间层的存在,降低了制造工艺和相对应半导体器件的复杂度以及相应的成本;另外可以降低在所生成的半导体器件中发生故障或本征缺陷的可能性。

Description

半导体器件和封装体
技术领域
本公开内容涉及一种用于特别是功率半导体器件的半导体器件的铝合金引线框。
背景技术
本领域内已知半导体器件,尤其是功率类型的半导体器件,例如功率MOSFET,其包括塑料封装件,该塑料封装件被设计为密封包括半导体材料并且集成相对应的集成电子组件的裸片,其中塑料封装件通常通过模塑(molding)来获得。
例如,图1示出了密封在例如环氧树脂的塑料材料的封装件2中的半导体器件1(特别地,功率器件)。
半导体器件1包括裸片3以及引线框4,裸片3包括半导体材料,特别地为硅,引线框架4布置为至少部分地位于封装件2之内并且设计为在封装件2之内支撑裸片3且提供朝向裸片3中出现的集成组件的外部的电连接。
引线框4包括:金属材料的支撑板(通常称为“裸片焊垫”或“裸片焊盘”)5,布置在封装件2之内并且具有顶部表面5a,裸片3例如经由粘合材料层6的插入耦合到该顶部表面5a;以及多个引线7,例如数目上为三个,其从封装件2出来。
按照这里未图示的方式,裸片焊盘5可以由采用引线7中的一个引线的单一件制成(特别地采用布置在中间位置的引线),由此构成了半导体器件1的电极(例如,功率MOSFET的漏极电极)。进一步,裸片3由电键合接线8电连接到剩余的引线7,所述电键合接线8从各自的接触焊垫开始延伸,由裸片3的顶部表面相承载且不与裸片焊盘5相接触,朝向各自的引线7(剩余的引线被设计为例如限定功率MOSFET的源极电极和栅极电极)。
引线框4的引线7接着例如通过焊接而电耦合到由印刷电路板(PCB)10的顶部表面所承载的相对应的电焊垫9,该电焊垫9具有已知的类型并且在此不再详细描述。
与图1中所图示的不同,裸片焊盘5可以用作封装件2的基础,在这种情况下布置为在与裸片3耦合到的顶部表面5a相对的其底部表面5b处与外部环境相接触,或者如相同的图1中所图示的,裸片焊盘5还可以在下方由封装件2的密封材料的部分进行涂敷。
在任何情况下,裸片焊盘5还可以用作热传送元件,用于将在集成在裸片3中的组件的使用中生成的热朝向外部散热器(未示出)传送。
半导体器件1以及相对应的引线框4和例如朝向印刷电路板10的朝向外部的电连接的制造于是利用了关于引线框4而提供的多个分立的电连接接口,即为:
用于封装件2内部的引线7的第一端7a和电键合接线8之间的连接的接口,其例如提供在铜(作为构成引线7的材料)和铝、铜或金(作为构成电键合接线8的材料)之间的耦合;
用于封装件2外部的引线7的第二端7b和在印刷电路板10上的各自的电焊垫9之间的连接的接口,其例如可以提供在铜(作为构成引线7的材料)和金(作为构成电焊垫9的材料)之间的耦合;以及
用于通过粘合材料层6的在裸片焊盘5和裸片3之间的连接的接口,其可以例如提供在铜(作为构成裸片焊盘5的材料)和例如SAC或SnPb的锡合金之间的耦合。
如果前述的材料组合中的一些彼此不相容,或者在任何情况下可能不能实现达到电耦合的期望质量,则使用一个或多个中间层,例如金属耦合层,其通常通过在待耦合的材料中的一个或多个上并且特别地是在引线框4上进行电沉积来形成。这个中间耦合金属层可以例如包括锌、镍、铜、银、锡、或者这些或其他材料的适当组合。
例如,US2013/0221507A1公开了铝合金引线框的制造,其在相对应的封装件和相对应的半导体器件的制造工艺期间利用了通过电沉积在构成引线框的金属层上方形成多个金属层。
然而,前述中间耦合金属层的存在引起了制造工艺和相对应半导体器件的复杂度的增加,以及相应的成本的增加;进一步,很显然地,在所生成的半导体器件中发生故障或本征缺陷的可能性也增加。
实用新型内容
本公开内容的一个或多个实施例提供一种用于半导体器件的铝合金引线框,其使得前述的与现有解决方案相关联的问题和劣势得以全部或者部分克服。
根据本公开内容,接下来提供半导体器件。
一个实施例涉及一种半导体器件,其特征在于,包括:裸片,包括半导体材料;引线框,包括支撑所述裸片的支撑板和电耦合到所述裸片的引线,其中所述引线框为铝合金,所述铝合金包括百分比在1%和1.5%之间的硅;以及封装件,包括对所述裸片进行密封的密封材料,其中部分的所述引线从所述封装件中伸出。
在一个实施例中,该半导体器件包括:在所述封装件内的至少一个电键合接线,被直接耦合到所述引线的至少一个引线的第一端并且第二端耦合到所述裸片的接触焊垫。
在一个实施例中,从所述封装件中伸出的所述部分的引线被配置为直接与另一器件或板的接触焊垫耦合。
在一个实施例中,所述裸片被直接耦合到所述引线框的支撑板的表面。
在一个实施例中,所述裸片通过粘合剂被耦合到所述引线框的支撑板的表面。
在一个实施例中,所述铝合金进一步包括百分比在0.25%和0.6%之间的镁。
在一个实施例中,所述半导体器件为功率器件。
另一实施例涉及一种封装体,其特征在于,包括:包括裸片焊垫和引线的引线框,所述引线框为铝合金,所述铝合金包含在1%到1.5%之间的硅;半导体裸片,被耦合到所述裸片焊垫的表面;导电接线,将所述半导体裸片的键合焊垫电耦合到所述引线的第一部分;以及封装件,将所述裸片和所述导电接线进行密封,所述引线的第二部分从所述封装件中延伸出。
在一个实施例中,所述铝合金的剩余部分为铝。
在一个实施例中,所述铝合金包含百分比在0.25%到0.6%之间的镁。
在一个实施例中,所述引线为第一引线,所述封装体进一步包括第二引线,所述第二引线具有在所述封装件中的第一部分以及从所述裸片焊垫延伸出的第二部分。
在一个实施例中,所述引线的第二部分被配置为直接耦合到另一器件或衬底的接触焊垫。
在一个实施例中,所述封装体为功率器件。
根据本实用新型的方案,可以避免中间层的存在,降低了制造工艺和相对应半导体器件的复杂度以及相应的成本;另外可以降低在所生成的半导体器件中发生故障或本征缺陷的可能性。
附图说明
为了更好地理解本公开内容,现在纯粹通过非限定的例子并且参照附图描述其优选实施例,其中:
图1示出了耦合到印刷电路板的半导体器件和相对应的封装体的示意性横截面图;
图2A-图2C示出根据本实用新型一个实施例的半导体器件和相对应的封装体的制造工艺的连续步骤的示意性平面视图;以及
图2D示出了在制造工艺的结束时半导体器件和相对应的封装体的透视图。
具体实施方式
通过广泛的测试和实验性的评估,本申请人已经意识到,将特定的铝合金用作用于提供集成半导体器件的封装体的引线框的基础构成材料提供了通常使用的材料所无法获得的特定的优势。
特别地,这种铝合金包含了在1%到1.5%的范围中的硅含量。
本申请人进一步意识到,可以具有优势地用于提供引线框的铝合金公开在WO2013/037918A1中,将该申请在此通过参考整体并入,然而该申请描述了将这种材料用于与集成半导体器件的制造领域毫无关联或联系的领域,特别地是在用于形成构成汽车的面板的汽车行业。那里所公开的使用针对宏观应用,即,完全与集成的解决方案不同的应用,例如生产车辆的主体的面板(例如,用于阀盖或门)。
在这篇文献中描述的铝合金,由制造商HydroAluminiumRolledProductsGmbH的编码AA6016来标识,其为铝和硅的合金并且进一步包括百分比在0.25%和0.6%之间的镁。
本解决方案的一个方面接着构思了利用具有在1%和1.5%之间的硅含量的铝合金,例如在前述文献WO2013/037918A1中所描述的合金,用于制造半导体器件特别是功率半导体器件的引线框(即,用于在微观尺度上的应用)。半导体器件例如如参照图1所描述地那样制造。
根据特定的应用,可以向上述合金中添加较低百分比(例如,0.1%-0.2%)的其他金属,例如铁、锰、铬、锡或锌,或其他掺杂元素,例如磷或铍;同样,有可能存在残余杂质。
本申请人已经发现这种类型的引线框具有优化的机械特性,例如在强度和硬度方面,以及电特性,例如避免了使用用于与不同材料电耦合的中间金属层,不同材料例如为封装体中的电接线、由外部印刷电路板承载的电焊垫以及/或者在封装体内的硅裸片。
本解决方案的又一个方面构思了用于制造半导体器件的封装体的合适的制造工艺。
通过最初参照图2A,制造工艺构思了利用已知类型并且在此没有详细描述的技术对前述包含了在1%到1.5%的范围内的硅含量的铝合金的板20进行模塑,用于限定在板20本身的耦合区域20’处耦合在一起的多个引线框24(例如,各种引线框24可以布置为行或条)。
正如之前所提及的,每个引线框24包括:支撑板(以下为裸片焊盘)25,具有限定设计用来接收半导体材料的裸片的区域的顶部表面25a;以及多个引线27,在例子中其数目为三,其中中间引线27a整体地连接到裸片焊盘25,并且两个侧引线27b、27c布置为横向地沿着中间引线27a,通过相应的耦合区域20’连接到中间引线27a。
在图2A中所图示的例子中,引线框24进一步包括带孔的外部部分24’,该带孔的外部分别24’整体地连接到裸片焊盘25并且以已知且不在此进行详细描述的方式被设计为耦合到散热器。
特别地,每个引线27在裸片焊盘25附近、在被设计用于由相对应的封装件所闭合的区域处具有电连接区域27’,该电连接区域27’被设计用于与相对应的电键合接线的电连接。
制造工艺接着进行到(图2B)将裸片23耦合到裸片焊盘25的顶表面25a上。裸片23包括半导体材料例如硅,并且集成一个或多个电子组件,例如一个或多个功率MOSFET元件。
特别地,前述的耦合可以通过利用布置在裸片焊盘25的顶表面25a和裸片23的底表面之间的粘合材料层的键合来获得(以类似于在图1中所图示的方式)。在这种情况下,没有构思对裸片焊盘25的预备表面处理。
可代替地,可以通过焊接(所谓的“软焊”),优选地为无铅焊接,来获得该耦合。
在这种情况下,本解决方案的一个方面构思了局部化清洁的预备步骤(所谓“原位清洁”),从而预备好裸片焊盘25的顶表面25a用于焊接到裸片23。这个清洁可以例如去除形成在顶表面25a上的杂质或氧化物,或者一般来说不规则物。
本申请人发现,清洁操作进一步改善了顶表面25a的润湿性,由此有助于接下来的耦合到裸片23的操作。
例如,可以以本身已知的方式,利用诸如局部化激光或等离子体处理的物理(非化学)类型的处理来执行对顶表面25a的清洁,如例如在US2008/0009129A1中所描述的,将该申请在此通过参考整体并入。
接着,制造工艺构思(图2C)在裸片23和引线27之间通过接线键合技术(即,通过利用电接线的连接)的电连接。
电键合接线28于是连接在引线27(特别地侧引线27b、27c)的电连接区域27’和由裸片23的顶表面23a所承载的接触焊垫30之间,而未与裸片焊盘25相接触。
特别地,在使用了铝电键合接线28的情况下,可以通过超声键合技术(是已知类型并且在此不再详细描述)来获得电连接。在这种情况下,没有构思对引线27的预备表面处理。
可代替地,在使用了铜、金或银的电键合接线28的情况下,可以使用热超声键合技术(是已知类型,在此不再详细描述)。
在这种情况下,本解决方案的一个方面构思了在引线27的电连接区域27’和接触焊垫30的区域处原位清洁的预备步骤以便预备好裸片23的顶表面23a。
清洁可以例如去除杂质或氧化物,或者一般来说不规则物,并且可以通过局部化激光或等离子体处理来执行。
制造工艺接着进行到(参照图2D)采用诸如注塑成型的模塑技术(是已知类型并且在此不再详细描述)形成例如环氧树脂的塑料材料的封装件32。封装件32的材料特别是覆盖了裸片23以及裸片焊盘25、电键合接线28和引线27的电连接区域27’。这个步骤没有构思任何对于引线框24的处理或加工的操作。
此外,在耦合区域20’处执行所谓的“裁切”操作,从而将各个引线框24彼此分离以及进一步将每个引线框24的引线27相分离,从而获得个体的半导体器件40,例如功率晶体管器件(如在前面的图2D中所图示的)。同样这个步骤没有构思任何对于引线框24的处理或加工的操作。
制造工艺以封装件32外部的引线27的端接部分的表面修整操作而终止(所谓的“焊料浸渍”操作)。
特别地,前述的引线27的外部端接部分涂覆有含铅或无铅的焊料涂层,该焊料涂层被设计用于帮助例如焊接到印刷电路板的进一步的操作(在此未示出)。
焊料涂层可以例如通过如下连续步骤来涂覆:将引线27的外部端接浸渍在焊剂中,该焊剂也实现对可能的表面氧化物的去除;将相同的端接浸渍在熔化的焊料材料中,在例如250℃和300℃之间的温度处;并且最终例如利用水进行清洗。
所提出的解决方案的优势从前述中清楚地凸显。
在任何情况下,需要强调的是这种解决方案允许了避免在引线框上使用例如金属层的中间层的需要,该中间层一般由电沉积形成以便实现其电耦合。
事实上,制造工艺在这种情况下构思了原位清洁的最多的预备操作,目的在于改善引线框的电耦合的特性(特别地,相对应的裸片焊盘和相对应的引线的特性)。
此外,用于提供引线框的铝合金允许达到希望的机械特性,例如就强度而言,由此允许了所得到的引线框的机械加工性的希望特性。本申请人于是例如发现了在60布氏硬度和80布氏硬度之间的引线框的硬度,即相较于利用传统材料所得到的结果而言高得多。
上述的优势,尤其在强度和省略中间耦合层的电沉积步骤方面而言特别地明显,例如当与上面引用的US2013/0221507A1的解决方案相比较时。
此外,本解决方案中指出的材料通过模塑易于处理并且因而不需要对现有的机器的修改。
最终,很清楚的是,可以对在此所描述和图示的内容做出修改和变形,而不会因此背离本公开内容的范围。
特别地,很明显的是,所描述的解决方案寻找到了针对任何包括具有引线框的封装体的半导体器件(即便不是功率类型的)的具有优势的应用。
进一步,很明显的是,引线框和封装体的特定构造可以与参照图2A-图2D所描述的不同。例如,所得到的半导体器件40可以包括不同数目的引线27,或者没有引线框24的用于耦合到散热器的外部部分24’。
此外,正如之前所着重强调的,包括所指出的百分比的硅的铝合金,可以可能地包括进一步的构成元素,例如低百分比(例如,0.2%-0.3%)的掺杂元素。
上面描述的各种实施例可以组合以提供进一步的实施例。可以在上面详细的描述的启发下做出这些以及其他的对于实施例的改变。一般地,在下面的权利要求中,所使用的术语不应当被解释为将权利要求限制在说明书和权利要求所公开的特定实施例,而是应当被解释为包括所有的可能实施例,连同这些权利要求所被赋予的全面等效范围。相应地,权利要求不受本公开内容的限制。

Claims (13)

1.一种半导体器件,其特征在于,包括:
裸片,包括半导体材料;
引线框,包括支撑所述裸片的支撑板和电耦合到所述裸片的引线,其中所述引线框为铝合金,所述铝合金包括百分比在1%和1.5%之间的硅;以及
封装件,包括对所述裸片进行密封的密封材料,其中部分的所述引线从所述封装件中伸出。
2.根据权利要求1所述的器件,其特征在于,包括:在所述封装件内的至少一个电键合接线,被直接耦合到所述引线的至少一个引线的第一端并且第二端耦合到所述裸片的接触焊垫。
3.根据权利要求1所述的器件,其特征在于,
从所述封装件中伸出的所述部分的引线被配置为直接与另一器件或板的接触焊垫耦合。
4.根据权利要求1所述的器件,其特征在于,所述裸片被直接耦合到所述引线框的支撑板的表面。
5.根据权利要求1所述的器件,其特征在于,所述裸片通过粘合剂被耦合到所述引线框的支撑板的表面。
6.根据权利要求1所述的器件,其特征在于,所述铝合金进一步包括百分比在0.25%和0.6%之间的镁。
7.根据权利要求1所述的器件,其特征在于,所述半导体器件为功率器件。
8.一种封装体,其特征在于,包括:
包括裸片焊垫和引线的引线框,所述引线框为铝合金,所述铝合金包含在1%到1.5%之间的硅;
半导体裸片,被耦合到所述裸片焊垫的表面;
导电接线,将所述半导体裸片的键合焊垫电耦合到所述引线的第一部分;以及
封装件,将所述裸片和所述导电接线进行密封,所述引线的第二部分从所述封装件中延伸出。
9.根据权利要求8所述的封装体,其特征在于,所述铝合金的剩余部分为铝。
10.根据权利要求8所述的封装体,其特征在于,所述铝合金包含百分比在0.25%到0.6%之间的镁。
11.根据权利要求8所述的封装体,其特征在于,所述引线为第一引线,所述封装体进一步包括第二引线,所述第二引线具有在所述封装件中的第一部分以及从所述裸片焊垫延伸出的第二部分。
12.根据权利要求8所述的封装体,其特征在于,所述引线的第二部分被配置为直接耦合到另一器件或衬底的接触焊垫。
13.根据权利要求8所述的封装体,其特征在于,所述封装体为功率器件。
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US8709874B2 (en) * 2010-08-31 2014-04-29 Advanpack Solutions Pte Ltd. Manufacturing method for semiconductor device carrier and semiconductor package using the same
JP5758676B2 (ja) * 2011-03-31 2015-08-05 株式会社神戸製鋼所 成形加工用アルミニウム合金板およびその製造方法
CN103187382B (zh) * 2011-12-27 2015-12-16 万国半导体(开曼)股份有限公司 应用在功率半导体元器件中的铝合金引线框架
US8716069B2 (en) * 2012-09-28 2014-05-06 Alpha & Omega Semiconductor, Inc. Semiconductor device employing aluminum alloy lead-frame with anodized aluminum
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