CN203085521U - Lead frame for packaging three chips - Google Patents
Lead frame for packaging three chips Download PDFInfo
- Publication number
- CN203085521U CN203085521U CN2013200787304U CN201320078730U CN203085521U CN 203085521 U CN203085521 U CN 203085521U CN 2013200787304 U CN2013200787304 U CN 2013200787304U CN 201320078730 U CN201320078730 U CN 201320078730U CN 203085521 U CN203085521 U CN 203085521U
- Authority
- CN
- China
- Prior art keywords
- chip
- chip carrier
- lead frame
- lead
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to a lead frame for packaging three chips. The lead frame comprises at least one lead support group, wherein the lead support group is formed by joining a plurality of lead supports in the longitudinal direction in parallel, each lead support comprises a first ship seat, a second ship seat and a third chip seat, which are arranged at intervals, and the first chip seat, the second chip seat and the third chip seat are respectively used for installing a first chip, a second chip and a third chip. By designing the first chip seat and the second chip seat in different sizes, so that a first chip and a second chip in different sizes can be installed, and the practicable requirement can be met; the structure is optimized, and the lead quantity is reduced, the rejection rate caused by the packaging can be reduced, and the product yield can be improved; and the lead frame has the advantages of simplicity and reasonability in structure and stable performance.
Description
Technical field
The utility model relates to a kind of lead frame, relates in particular to a kind of lead frame of three Chip Packaging of the 16NSOP of being used for product.
Background technology
About the lead frame of semiconductor packages, it mainly is used as chip and a Support Position is provided and chip is fixed, and makes between chip and the lead frame output with gold thread simultaneously to connect into circuit.At present, the project that lead frame almost reduces as each company cost, wish to carry product as much as possible on a lead frame, reaching the purpose of saving, but the technology difficulty in the bonding gold wire technology of existing 16NSOP product is big, causes the complex structure of lead frame, gold thread quantity many, cause the fraction defective height after the encapsulation, product yield is low, and unstable properties has been wasted a large amount of production costs.
The utility model content
The utility model has overcome the deficiencies in the prior art, and a kind of simple in structure, lead frame that is used for three Chip Packaging that product yield is high is provided.
For achieving the above object, the technical solution adopted in the utility model is: a kind of lead frame that is used for three Chip Packaging, comprise at least one wire support group, described wire support group vertically is formed by connecting side by side by a plurality of wire supports, described wire support comprises three spaced first chip carriers, second chip carrier, the 3rd chip carrier, and described first chip carrier, second chip carrier, the 3rd chip carrier are respectively applied for installs first chip, second chip, the 3rd chip.
In preferred embodiment of the utility model, the lead frame that is used for three Chip Packaging comprises that further described first chip carrier, described second chip carrier, the 3rd chip carrier are that arrange the lateral separation.
In preferred embodiment of the utility model, the lead frame that is used for three Chip Packaging further comprise described first chip carrier, second chip carrier and the 3rd chip carrier around be arranged with 15 pins altogether.
In preferred embodiment of the utility model, the lead frame that is used for three Chip Packaging comprises that further a side of described first chip carrier, second chip carrier and the 3rd chip carrier is provided with eight pins, and opposite side is provided with seven pins.
In preferred embodiment of the utility model, the lead frame that is used for three Chip Packaging comprises that further described first chip, second chip and the 3rd chip are electrically connected to described pin by lead-in wire, does not have between the adjacent described lead-in wire and intersects.
The utility model has solved the defective that exists in the background technology, the utility model has designed first chip carrier and second chip carrier of two different sizes, be suitable for first chip of different size size, the installation of second chip, satisfied practical demand, structurally be optimized again, reduce its number of leads, can reduce the fraction defective that encapsulation causes, improve product yield, have advantage simple and reasonable for structure, stable performance.
Description of drawings
Below in conjunction with drawings and Examples the utility model is further specified.
Fig. 1 is the structural representation of the wire support of preferred embodiment of the present utility model;
Fig. 2 is the structural representation of preferred embodiment of the present utility model;
Among the figure: 1, wire support group, 2, wire support, 3, first chip carrier, 4, second chip carrier, the 5, the 3rd chip carrier, 6, first chip, 7, second chip, the 8, the 3rd chip, 9, pin, 10, lead-in wire.
Embodiment
In conjunction with the accompanying drawings and embodiments the utility model is described in further detail now, these accompanying drawings are the schematic diagram of simplification, basic structure of the present utility model only is described in a schematic way, so it only show the formation relevant with the utility model.
As shown in Figure 1, a kind of lead frame that is used for three Chip Packaging, comprise at least one wire support group 1, described wire support group 1 vertically is formed by connecting side by side by a plurality of wire supports 2, described wire support 2 comprises three spaced first chip carriers 3, second chip carrier 4, the 3rd chip carrier 5, described first chip carrier 3, second chip carrier 4, the 3rd chip carrier 5 are respectively applied for installs first chip 6, second chip 7, the 3rd chip 8, avoid the generation of short circuit phenomenon, reduced the usage quantity of materials such as gold thread simultaneously.
Preferred described first chip carrier 3 of the utility model, described second chip carrier 4, the 3rd chip carrier 5 are arranged for the lateral separation.
Further, described first chip carrier 3, second chip carrier 4 and the 3rd chip carrier 5 around be arranged with 15 pins altogether.First chip carrier 3, second chip carrier 4, the 3rd chip carrier 5 are done as a whole, preferably the side in integral body is provided with eight pins 9, and opposite side is provided with seven pins 9.
Preferred described first chip 6 of the utility model, second chip 7 and the 3rd chip 8 10 are electrically connected to described pin 9 by going between, and do not have intersection between the adjacent described lead-in wire 10.
As shown in Figure 2, in order to make lead frame can carry more chip, reduce the production cost of enterprise greatly, 14 wire support groups 1 are combined, each wire support group 1 has five wire supports 2 that vertically connect side by side, and first chip 6, second chip 7, the 3rd chip 8 of different sizes can be installed respectively on each wire support 2.
Above foundation desirable embodiment of the present utility model is enlightenment, and by above-mentioned description, the related personnel can carry out various change and modification fully in the scope that does not depart from this utility model technological thought.The technical scope of this utility model is not limited to the content on the specification, must determine technical scope according to the claim scope.
Claims (5)
1. lead frame that is used for three Chip Packaging, it is characterized in that: comprise at least one wire support group, described wire support group vertically is formed by connecting side by side by a plurality of wire supports, described wire support comprises three spaced first chip carriers, second chip carrier, the 3rd chip carrier, and described first chip carrier, second chip carrier, the 3rd chip carrier are respectively applied for installs first chip, second chip, the 3rd chip.
2. the lead frame that is used for three Chip Packaging according to claim 1 is characterized in that: described first chip carrier, described second chip carrier, the 3rd chip carrier are that arrange the lateral separation.
3. the lead frame that is used for three Chip Packaging according to claim 2 is characterized in that: be arranged with 15 pins around described first chip carrier, second chip carrier and the 3rd chip carrier altogether.
4. the lead frame that is used for three Chip Packaging according to claim 3 is characterized in that: a side of described first chip carrier, second chip carrier and the 3rd chip carrier is provided with eight pins, and opposite side is provided with seven pins.
5. the lead frame that is used for three Chip Packaging according to claim 4 is characterized in that: described first chip, second chip and the 3rd chip are electrically connected to described pin by lead-in wire, do not have between the adjacent described lead-in wire and intersect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200787304U CN203085521U (en) | 2013-02-21 | 2013-02-21 | Lead frame for packaging three chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200787304U CN203085521U (en) | 2013-02-21 | 2013-02-21 | Lead frame for packaging three chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203085521U true CN203085521U (en) | 2013-07-24 |
Family
ID=48831334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013200787304U Expired - Fee Related CN203085521U (en) | 2013-02-21 | 2013-02-21 | Lead frame for packaging three chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203085521U (en) |
-
2013
- 2013-02-21 CN CN2013200787304U patent/CN203085521U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130724 Termination date: 20140221 |