CN202585395U - DIP (Dual inline-pin Package) lead frame structure - Google Patents
DIP (Dual inline-pin Package) lead frame structure Download PDFInfo
- Publication number
- CN202585395U CN202585395U CN 201220194878 CN201220194878U CN202585395U CN 202585395 U CN202585395 U CN 202585395U CN 201220194878 CN201220194878 CN 201220194878 CN 201220194878 U CN201220194878 U CN 201220194878U CN 202585395 U CN202585395 U CN 202585395U
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- China
- Prior art keywords
- pin
- lead frame
- chip
- frame structure
- dip
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- Expired - Lifetime
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- 230000009977 dual effect Effects 0.000 title abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000012536 packaging technology Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a DIP (Dual inline-pin Package) lead frame structure, comprising a lead frame, two base islands, pins and frame connecting pins, wherein each of the two base islands is provided with a chip and the base islands are fixed on the lead frame through the pins and the frame connecting pins. The DIP lead frame structure is characterized in that one pin of one of the two chips has high voltage and a pin of the other chip, adjacent to the high-voltage pin, is not led out. Compared with the prior art, the DIP lead frame structure has the following advantages and beneficial effects that a fixed pin of a chip B base is designed to be adjacent to the high-voltage pin of the chip A, so a function which can be achieved in the traditional twin-island lead frame by virtue of two pins can be achieved in the DIP lead frame structure by only one pin; and compared with the traditional twin-island lead frame structure, the DIP lead frame structure disclosed by the utility model is completely compatible with a packaging technology flow.
Description
Technical field
The utility model relates to a kind of integrated circuit encapsulation technology field that belongs to, and is specifically related to a kind of DIP twin islet lead frame structure.
Background technology
The frequent existence of power integrated circuit need be encapsulated in same DIP (Dual Inline-pin Package with chip A and chip B; The encapsulation of twin islet straight cutting) situation in.Because chip A is different with the current potential of chip B substrate, must be installed on the different Ji Dao, so lead frame comprises two Ji Dao, each Ji Dao need be connected to a fixed with at least 1 connecting pin and 1 pin, and is stable to guarantee Ji Dao's.The lead frame that comprises two Ji Dao is called the twin islet lead frame.
There is not the pin of other current potentials to draw this demand in order to satisfy on the adjacent pin of the chip A high pressure pin position; If adopt traditional twin islet lead frame structure; Can only the fixedly pin of chip B Ji Dao be linked to each other with the substrate of chip B; For preventing high-voltage breakdown, this pin can not but still need take a pin position as the function pin; Perhaps that the pin of high presser feet adjacent locations is vacant, cause the waste of pin.
Summary of the invention
The utility model purpose is to the defective of prior art a kind of DIP twin islet lead frame structure with high pressure pin to be provided.
The utility model adopts following technical scheme for realizing above-mentioned purpose:
A kind of DIP twin islet lead frame structure; It comprises lead frame, two Ji Dao, pin and framework connecting pins; Be respectively arranged with a chip on said two Ji Dao; Said Ji Dao is fixed on the said lead frame through pin and framework connecting pin, it is characterized in that: said one of them chip pin has high pressure, and its another adjacent pin of chip is not drawn.
Compared with prior art, the utlity model has following advantage and beneficial effect:
(1) the DIP twin islet lead frame structure of the utility model, on chip A high pressure pin adjacent position, it realizes the function that 2 pins of traditional double island lead frame could be realized through 1 pin with the design of the fixedly pin of chip B pedestal;
(2) the DIP twin islet lead frame structure of the utility model is compared with the traditional double island lead frame structure, and its packaging technology flow process is compatible fully.
Description of drawings
Fig. 1 is the DIP twin islet lead frame structure sketch map of utility model;
Fig. 2 is the external form schematic top plan view that adopts the utility model DIP twin islet lead frame structure packaged chip.
Embodiment
A kind of DIP twin islet lead frame structure as shown in Figure 1; It comprises lead frame 1; 2, the second basic island 13, the first basic island; First pin 3, second pin 4, the 3rd pin 5, the 4th pin 6, the 5th pin 7, the 6th pin 8, the 7th pin 9, the 8th pin 10, A chip 11, B chip 12 and the first framework connecting pin 14, the second framework connecting pin 15; Basic island, the said first basic island 2, second 13, the first pins 3, second pin 4, the 3rd pin 5, the 4th pin 6, the 5th pin 7, the 6th pin 8, the 7th pin 9, the 8th pin 10 are arranged on the lead frame 1; Said A chip 11 is arranged on the first basic island 2, and B chip 12 is arranged on the second basic island 13; The said first basic island 2 fixes through said first pin 3, second pin 4 and the said first framework connecting pin 14, and wherein said first pin 3, second pin 4 are the pin of said A chip 11; The said second basic island 13 fixes through said the 3rd pin 5 and the second framework connecting pin 15, and said the 3rd pin 5 is adjacent with second pin 4 of said A chip 11, and does not draw.Voltage among the figure on second pin 4 of A chip is the 400-1000V high pressure.
Fig. 2 is for adopting the external form vertical view of the said utility model DIP twin islet of Fig. 1 leadframe package chip.Compare with adopting traditional double island lead frame structure packaged chip, the 3rd pin 5 is not drawn, and has therefore lacked a leading foot.
Claims (2)
1. DIP twin islet lead frame structure; It comprises lead frame, two Ji Dao, pin and framework connecting pins; Be respectively arranged with a chip on said two Ji Dao; Said Ji Dao is fixed on the said lead frame through pin and framework connecting pin, it is characterized in that: said one of them chip pin has high pressure, and its another adjacent pin of chip is not drawn.
2. according to the said a kind of DIP twin islet lead frame structure of claim 1; It is characterized in that: it comprises lead frame (1); First Ji Dao (2), second Ji Dao (13); First pin (3), second pin (4), the 3rd pin (5), the 4th pin (6), the 5th pin (7), the 6th pin (8), the 7th pin (9), the 8th pin (10), A chip (11), B chip (12) and the first framework connecting pin (14), the second framework connecting pin (15); Said first Ji Dao (2), second Ji Dao (13), first pin (3), second pin (4), the 3rd pin (5), the 4th pin (6), the 5th pin (7), the 6th pin (8), the 7th pin (9), the 8th pin (10) are arranged on the lead frame (1); Said A chip (11) is arranged on first Ji Dao (2), and B chip (12) is arranged on second Ji Dao (13); Said first Ji Dao (2) fixes through said first pin (3), second pin (4) and the said first framework connecting pin (14), and wherein said first pin (3), second pin (4) are the pin of said A chip (11); Said second Ji Dao (13) fixes through said the 3rd pin (5) and the second framework connecting pin (15), and said the 3rd pin (5) is adjacent with second pin (4) of said A chip (11), and does not draw.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220194878 CN202585395U (en) | 2012-05-03 | 2012-05-03 | DIP (Dual inline-pin Package) lead frame structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220194878 CN202585395U (en) | 2012-05-03 | 2012-05-03 | DIP (Dual inline-pin Package) lead frame structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202585395U true CN202585395U (en) | 2012-12-05 |
Family
ID=47254777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220194878 Expired - Lifetime CN202585395U (en) | 2012-05-03 | 2012-05-03 | DIP (Dual inline-pin Package) lead frame structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202585395U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811456A (en) * | 2014-02-18 | 2014-05-21 | 江阴苏阳电子股份有限公司 | Multi-chip DIP (Dual In-line Package) structure |
| CN103871995A (en) * | 2014-03-07 | 2014-06-18 | 气派科技股份有限公司 | Double-base-island seven-pin structure of integrated circuit (IC) and rib cutting die |
| CN105470189A (en) * | 2014-09-05 | 2016-04-06 | 无锡华润安盛科技有限公司 | Double-pad frame bonding heating block and fixture |
| CN113597057A (en) * | 2019-11-13 | 2021-11-02 | 上海路傲电子科技有限公司 | Chip frame, packaged chip, driving system and lighting device |
-
2012
- 2012-05-03 CN CN 201220194878 patent/CN202585395U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811456A (en) * | 2014-02-18 | 2014-05-21 | 江阴苏阳电子股份有限公司 | Multi-chip DIP (Dual In-line Package) structure |
| CN103871995A (en) * | 2014-03-07 | 2014-06-18 | 气派科技股份有限公司 | Double-base-island seven-pin structure of integrated circuit (IC) and rib cutting die |
| CN105470189A (en) * | 2014-09-05 | 2016-04-06 | 无锡华润安盛科技有限公司 | Double-pad frame bonding heating block and fixture |
| CN113597057A (en) * | 2019-11-13 | 2021-11-02 | 上海路傲电子科技有限公司 | Chip frame, packaged chip, driving system and lighting device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121205 |