CN203085519U - A chip leading wire frame - Google Patents
A chip leading wire frame Download PDFInfo
- Publication number
- CN203085519U CN203085519U CN2013200180522U CN201320018052U CN203085519U CN 203085519 U CN203085519 U CN 203085519U CN 2013200180522 U CN2013200180522 U CN 2013200180522U CN 201320018052 U CN201320018052 U CN 201320018052U CN 203085519 U CN203085519 U CN 203085519U
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- Prior art keywords
- pins
- chip
- frame
- pin
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The utility model discloses a chip leading wire frame which is suitable for TO-220/5L and TO-263/5L chip packaging technology. The chip leading wire frame comprises a frame pedestal. An installing hole, a chip carrying zone, and five pins are disposed on the frame pedestal. The five pins comprise a middle pin electrically connected with the frame pedestal. Two side pins are disposed in parallel at one side of the middle pin while the other two side pins are disposed in parallel at the other side of the middle pin. Bonding portions are disposed on the tops of the side pins. A bonding portion is disposed on the top of the middle pin. The position where the bonding portion of the middle pin is arranged is in a same horizontal line with the positions where the bonding portions of the side pins are arranged. In the chip leading wire frame, leading wires bonded on the pedestal previously are bonded on the pins. Therefore, the performance of the product is enhanced and the binding force between a plastic-sealed body and the frame is enhanced while the yield rate of the complete products is increased. In addition, the large chip IC packaging capability of the frame is enhanced so that purposes of reducing cost and increasing benefits are achieved.
Description
Technical field
The utility model relates to the semiconductor packaging field, especially relates to the lead frame of five pins of a kind of TO-220/5L of being applicable to and TO-263/5L Chip Packaging.
Background technology
Lead frame is as the chip carrier of integrated circuit, be a kind of being electrically connected by means of bonding material (spun gold, aluminium wire, copper wire) realization chip internal circuit exit and outer lead, form the key structure spare of electric loop, it has played the function served as bridge that is connected with outer lead, all needing to use lead frame in the semiconductor integrated package of the overwhelming majority, is basic material important in the electronics and information industry.
Along with the demand to power device of consumption market in recent years constantly enlarges, to improving constantly that product reliability requires; Give power device Packaging Industry has been brought development opportunity, and Tong Shi also Give power device Packaging Industry has proposed new challenge.So whether the design of lead frame that power device uses has rationally played critical effect to the power device Packaging Industry.
See also shown in Figure 1, Fig. 1 is the structural representation of traditional lead frame, the middle pin of the lead frame of five traditional pins just plays the electric connection effect, need on middle pin, go between for some chips, can only be bonded on the frame base that is connected with middle pin, and five pin routings are at pedestal, often can not draw high and cause when being subjected to plastic packaging punching press to make the bank distortion run into chip to cause short circuit or line to disconnect causing to open circuit because of the bank of bonding, thereby influence properties of product, cause encapsulating yield and reduce.
The utility model content
The purpose of this utility model is to provide a kind of chip lead framework, and it has enhancing product performance, strengthens the adhesion of plastic-sealed body and framework and the characteristics that promote the finished product yield, to solve the problem that prior art chips lead frame exists.
The purpose of this utility model is to be achieved through the following technical solutions:
A kind of chip lead framework, it comprises frame base, described frame base is provided with installing hole, slide glass district and five pins, described five pins comprise the middle pin that is electrically connected with frame base, the both sides of pin all are set side by side with two side pins in the middle of described, and wherein, the top of described side pin is provided with bonding part, and the top of pin also is provided with bonding part in the middle of described, and the bonding part that position and side pin are set of the bonding part of described middle pin is on the same horizontal line.
Especially, the width of the bonding part of described middle pin is 1 ㎜.
The beneficial effects of the utility model are, described chip lead framework is compared with prior art by increasing bonding part at middle pin, change into and being bonded on the pin being bonded in lead-in wire on the pedestal, draw high the lead-in wire arc and avoid influenced by punching press and make the lead-in wire arc blow to run into chip when plastic packaging causing short circuit, line disconnects causing and opens circuit.Not only improve the performance of product, strengthened the adhesion of plastic-sealed body and framework, promoted the yield of finished product.And the ability that promotes this framework encapsulation large chip IC reaches the purpose that reduces cost and increase the benefit.
Description of drawings
Fig. 1 is the structural representation of traditional lead frame
Fig. 2 is the front view of the chip lead framework that provides of the utility model embodiment 1;
Fig. 3 is the end view of the chip lead framework that provides of the utility model embodiment 1.
Embodiment
Further specify the technical solution of the utility model below in conjunction with accompanying drawing and by embodiment.
See also shown in Fig. 2 and 3, Fig. 2 is the front view of the chip lead framework that provides of the utility model embodiment 1; Fig. 3 is the end view of the chip lead framework that provides of the utility model embodiment 1.
In the present embodiment, a kind of chip lead framework comprises frame base 1, described frame base 1 is provided with installing hole 2, slide glass district 3 and five pins, described five pins comprise the middle pin 4 that is electrically connected with frame base 1, the both sides of pin 4 all are set side by side with two side pins 5 in the middle of described, the top of described side pin 5 is provided with bonding part 6a, and the top of pin 4 also is provided with bonding part 6b in the middle of described, the bonding part 6a that position and side pin 5 are set of the bonding part 6b of pin 4 is on the same horizontal line in the middle of described, and the width of described bonding part 6b is 1 ㎜.
The lead frame profile of said frame construction packages profile and standard is identical, can extensive use.Pin 4 increases bonding part 6b in the middle of the lead frame, change into and being bonded on the pin being bonded in lead-in wire on the pedestal, avoid when plastic packaging, influenced by punching press and make the lead-in wire arc blow to run into chip and cause short circuit, line disconnects causing and opens circuit, can improve the performance of product, strengthen the adhesion of plastic-sealed body and framework, promote the yield of finished product.The ability that can promote this framework encapsulation large chip IC reaches the purpose that reduces cost and increase the benefit.
Above embodiment has just set forth basic principle of the present utility model and characteristic; the utility model is not limited by above-mentioned example; under the prerequisite that does not break away from the utility model spirit and scope; the utility model also has various variations and change, and these variations and change all fall in claimed the utility model scope.The claimed scope of the utility model is defined by appending claims and equivalent thereof.
Claims (2)
1. chip lead framework, it comprises frame base, described frame base is provided with installing hole, slide glass district and five pins, described five pins comprise the middle pin that is electrically connected with frame base, the both sides of pin all are set side by side with two side pins in the middle of described, it is characterized in that: the top of described side pin is provided with bonding part, and the top of pin also is provided with bonding part in the middle of described, and the bonding part that position and side pin are set of the bonding part of described middle pin is on the same horizontal line.
2. chip lead framework according to claim 1; It is characterized in that: the width of the bonding part of pin is 1 ㎜ in the middle of described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200180522U CN203085519U (en) | 2013-01-14 | 2013-01-14 | A chip leading wire frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013200180522U CN203085519U (en) | 2013-01-14 | 2013-01-14 | A chip leading wire frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203085519U true CN203085519U (en) | 2013-07-24 |
Family
ID=48831332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013200180522U Expired - Fee Related CN203085519U (en) | 2013-01-14 | 2013-01-14 | A chip leading wire frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203085519U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039367A (en) * | 2016-01-08 | 2017-08-11 | 新光电气工业株式会社 | Optical-semiconductor element packaging body |
| CN112289765A (en) * | 2020-12-24 | 2021-01-29 | 瑞能半导体科技股份有限公司 | Semiconductor package device |
-
2013
- 2013-01-14 CN CN2013200180522U patent/CN203085519U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107039367A (en) * | 2016-01-08 | 2017-08-11 | 新光电气工业株式会社 | Optical-semiconductor element packaging body |
| CN107039367B (en) * | 2016-01-08 | 2021-05-28 | 新光电气工业株式会社 | Optical semiconductor element package |
| CN112289765A (en) * | 2020-12-24 | 2021-01-29 | 瑞能半导体科技股份有限公司 | Semiconductor package device |
| CN112289765B (en) * | 2020-12-24 | 2021-04-20 | 瑞能半导体科技股份有限公司 | Semiconductor package device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130724 Termination date: 20170114 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |