CN203026499U - Chip double-sided packaging structure - Google Patents

Chip double-sided packaging structure Download PDF

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Publication number
CN203026499U
CN203026499U CN2012206343590U CN201220634359U CN203026499U CN 203026499 U CN203026499 U CN 203026499U CN 2012206343590 U CN2012206343590 U CN 2012206343590U CN 201220634359 U CN201220634359 U CN 201220634359U CN 203026499 U CN203026499 U CN 203026499U
Authority
CN
China
Prior art keywords
chip
substrate
bonded
double
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2012206343590U
Other languages
Chinese (zh)
Inventor
李佳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XI'AN WEIZHENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
Original Assignee
XI'AN WEIZHENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XI'AN WEIZHENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd filed Critical XI'AN WEIZHENG ELECTRONIC SCIENCE AND TECHNOLOGY Co Ltd
Priority to CN2012206343590U priority Critical patent/CN203026499U/en
Application granted granted Critical
Publication of CN203026499U publication Critical patent/CN203026499U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a chip double-sided packaging structure which comprises a first chip as well as a second chip, wherein the first chip is bonded on the frontage side of a substrate through electric conducting glue or insulation glue; the second chip is bonded on the reverse side of the substrate through electric conducting glue or insulation glue; the first chip, the second chip and the substrate are all packaged to a packaged outer shell; the first chip and the second chip are both bonded to corresponding conducting bands of the substrate through golden wires, and are leaded out of the packaging outer shell through pins. Chips are both assembled to double sides of the substrate provided by the utility model, the system integration degree is improved greatly, and production miniaturization and reliability are improved; the scheme can effectively improve the functions of a packaging body; and double-sided assembling enables component assembling amount to be doubled.

Description

A kind of chip double-side envelope rotation structure
Technical field
The utility model relates to the die package technical field, particularly a kind of chip double-side envelope rotation structure.
Background technology
Traditional chip package is the encapsulation of single-chip single face, and the shortcoming of this mode is to only have 1 chip in each shell, has limited on the one hand the finished product circuit function of encapsulation, has also caused on the other hand very large waste.
Summary of the invention
In order to overcome above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide a kind of chip double-side envelope rotation structure, has characteristics easy to use simple in structure.
To achieve these goals, the technical solution adopted in the utility model is:
A kind of chip double-side envelope rotation structure, comprise the first chip 2 that is bonded in substrate 6 fronts with conducting resinl or insulating cement, and the second chip 5 that is bonded in substrate 6 reverse side with conducting resinl or insulating cement, the first chip 2, the second chip 5 and substrate 6 all are packaged in package casing 1, the first chip 2 and the second chip 5 all are bonded on the corresponding conduction band of substrate 6 by spun gold 3, and draw outside package casing 1 by pin 4.
Described package casing 1 comprises top cover, sidewall and bottom.
Compared with prior art, the two-sided equal assembling chip of the utility model substrate has improved level of integrated system greatly, is beneficial to the miniaturization of product and the raising of reliability, this scheme can effectively improve the packaging body function, and two-sided assembling makes components and parts assembling amount improve 2 times.
Description of drawings
Accompanying drawing is structural representation of the present utility model.
Embodiment
Below in conjunction with drawings and Examples, the utility model is carried out more detailed explanation.
As shown in the figure, the utility model is a kind of chip double-side envelope rotation structure, comprise the first chip 2 that is bonded in substrate 6 fronts with conducting resinl or insulating cement, and the second chip 5 that is bonded in substrate 6 reverse side with conducting resinl or insulating cement, the first chip 2, the second chip 5 and substrate 6 all are packaged in package casing 1, the first chip 2 and the second chip 5 all are bonded on the corresponding conduction band of substrate 6 by spun gold 3, and draw outside package casing 1 by pin 4, glass insulator is set therebetween guarantees sealing and reliability.
Utilize the two-sided assembling bare chip of substrate 6 in this programme, substrate 6 selects ltcc substrate or HTCC substrate all can, after assembling is completed, the surrounding of substrate up and down is all used the encapsulating shell good seal, package casing 1 comprises top cover, sidewall and bottom, the first chip 2 is positioned at the chamber that top cover, sidewall and substrate 6 surround, and the second chip 5 is positioned at the chamber that bottom, sidewall and substrate 6 surround.
The utility model has realized that dual chip is integrated in an encapsulating housing, can make the single system miniaturization, improves the competitiveness of product.

Claims (2)

1. a chip double-side seals rotation structure, it is characterized in that, comprise with conducting resinl or insulating cement and be bonded in positive the first chip (2) of substrate (6), and the second chip (5) that is bonded in substrate (6) reverse side with conducting resinl or insulating cement, the first chip (2), the second chip (5) and substrate (6) all are packaged in package casing (1), the first chip (2) and the second chip (5) all are bonded on the corresponding conduction band of substrate (6) by spun gold (3), and draw outside package casing (1) by pin (4).
2. chip double-side seals rotation structure according to claim 1, it is characterized in that, described package casing (1) comprises top cover, sidewall and bottom.
CN2012206343590U 2012-11-26 2012-11-26 Chip double-sided packaging structure Expired - Fee Related CN203026499U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012206343590U CN203026499U (en) 2012-11-26 2012-11-26 Chip double-sided packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012206343590U CN203026499U (en) 2012-11-26 2012-11-26 Chip double-sided packaging structure

Publications (1)

Publication Number Publication Date
CN203026499U true CN203026499U (en) 2013-06-26

Family

ID=48650460

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012206343590U Expired - Fee Related CN203026499U (en) 2012-11-26 2012-11-26 Chip double-sided packaging structure

Country Status (1)

Country Link
CN (1) CN203026499U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112289755A (en) * 2019-07-23 2021-01-29 珠海格力电器股份有限公司 TO packaging structure and packaging method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112289755A (en) * 2019-07-23 2021-01-29 珠海格力电器股份有限公司 TO packaging structure and packaging method

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130626

Termination date: 20131126