CN202384327U - 小体积芯片封装结构 - Google Patents

小体积芯片封装结构 Download PDF

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Publication number
CN202384327U
CN202384327U CN 201120486639 CN201120486639U CN202384327U CN 202384327 U CN202384327 U CN 202384327U CN 201120486639 CN201120486639 CN 201120486639 CN 201120486639 U CN201120486639 U CN 201120486639U CN 202384327 U CN202384327 U CN 202384327U
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chip
lead frame
utility
model
chip package
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Expired - Fee Related
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CN 201120486639
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English (en)
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彭兰兰
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Individual
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

本实用新型公开了一种小体积芯片封装结构，包括半导体芯片、导线架和包覆上述两者的封胶体，所述的芯片通过其下表面设置的数个电极电性连接导线架，该导线架设有数个对应各个电极的引脚延伸至该封胶体的侧边，使芯片的上表面裸露在该封胶体顶端表面上。由于采用上述结构，本实用新型可增强芯片的散热效果；可使芯片封装体积减少。

Description

小体积芯片封装结构
技术领域
本实用新型涉及封装技术领域，尤其是一种小体积的芯片封装结构。
背景技术
一般半导体芯片需要透过封装制作过程，由此保护芯片，并同时提供电性连接的接脚。
现有的封装制作过程中，大多是将整个芯片包覆于封装体内，再通过导线架连接芯片中所对应的电极，并分别延伸数个接脚至封装体外部，以提供封装后的芯片安装至电路板以达到电性连接。
因此，现有技术有待于提高和改善。
发明内容
为解决现有技术中的不足之处，本实用新型的目的是提供一种将芯片的顶端面裸露于封装体上部，以大幅度缩小封装体的提及，近而提升芯片的散热效果的小体积芯片封装结构。
本实用新型是通过以下技术手段来实现上述目的的：一种小体积芯片封装结构，包括半导体芯片、导线架和包覆上述两者的封胶体，所述的芯片通过其下表面设置的数个电极电性连接导线架，该导线架设有数个对应各个电极的引脚延伸至该封胶体的侧边，使芯片的上表面裸露在该封胶体顶端表面上。
由于采用上述结构，本实用新型可增强芯片的散热效果；可使芯片封装体积减少。
附图说明
附图1为本实用新型小体积芯片封装结构结构示意图。
图中各标号分别是：（1）芯片，（2）电极，（3）导线架，（4）引脚，（5）封胶体。
具体实施方式
下面结合附图对本实用新型作进一步的详细说明：
参看图1，本实用新型一种小体积芯片封装结构，包括半导体芯片1、导线架3和包覆上述两者的封胶体5， 所述的芯片1通过其下表面设置的数个电极2电性连接导线架3，该导线架3设有数个对应各个电极2的引脚4延伸至该封胶体5的侧边，使芯片1的上表面裸露在该封胶体5顶端表面上。
以上所述，仅是本实用新型的较佳实施例而已，并非对本实用新型作任何形式上的限制，任何熟悉本专业的技术人员可能利用上述揭示的技术内容加以变更或修饰为等同变化的等效实施例，但是凡未脱离本实用新型技术方案内容，依据本实用新型的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本实用新型技术方案的范围内。

Claims (1)

1.一种小体积芯片封装结构，包括半导体芯片、导线架和包覆上述两者的封胶体，其特征在于：所述的芯片通过其下表面设置的数个电极电性连接导线架，该导线架设有数个对应各个电极的引脚延伸至该封胶体的侧边，使芯片的上表面裸露在该封胶体顶端表面上。
CN 201120486639 2011-11-30 2011-11-30 小体积芯片封装结构 Expired - Fee Related CN202384327U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120486639 CN202384327U (zh) 2011-11-30 2011-11-30 小体积芯片封装结构

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Application Number Priority Date Filing Date Title
CN 201120486639 CN202384327U (zh) 2011-11-30 2011-11-30 小体积芯片封装结构

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CN202384327U true CN202384327U (zh) 2012-08-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105227129A (zh) * 2015-09-22 2016-01-06 常州星海电子有限公司 高导热贴片旁路二极管

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105227129A (zh) * 2015-09-22 2016-01-06 常州星海电子有限公司 高导热贴片旁路二极管
CN105227129B (zh) * 2015-09-22 2017-11-28 常州星海电子股份有限公司 高导热贴片旁路二极管

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C17 Cessation of patent right
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Granted publication date: 20120815

Termination date: 20121130