CN207834269U - 一种ic芯片的封装结构 - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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Abstract
本实用新型涉及IC芯片技术领域，具体涉及一种IC芯片的封装结构，其结构包括框槽、设于所述框槽上的与外部电连接的金属引体、固定于所述框槽内的IC芯片，所述IC芯片的电路管脚通过键合线与所述金属引体键合连接从而与外部电路进行电气连接，所述框槽内填充有封装胶，所述封装胶密封所述键合线和所述IC芯片的上表面和侧面，IC芯片的封装结构能够缩小体积的IC芯片封装结构，该IC芯片封装结构具有容易封装、散热效果好和生产成本低的优点。
Description
技术领域
本实用新型涉及IC芯片技术领域，具体涉及一种IC芯片的封装结构。
背景技术
IC芯片是现今高科技的核心部件之一，其广泛应用于各个领域，小至简单的指示电路，大至航天设备，均要采用大批量的IC封装器件。因此，提升IC封装器件的产品性能及降低生产成本是大力发展IC芯片的关键。
然而，传统的IC结构是将IC芯片用银胶固定在支架焊盘上，用金线或铜线键合到芯片的电极和支架焊盘的相应引脚上以形成电气连接，然后在IC芯片的外周面(包括背面)注入封装胶烘烤固化成形。由于上述IC封装结构可知，现有的IC芯片封装体使用的材料较多，物料成本较大；而且，焊盘所涉及的体积较大，不利于简化IC芯片封装体的结构。同时，IC芯片封装体的散热需求更高，但现有技术采用上下注封装胶的方式，导致IC芯片难以散热，以致降低IC芯片的使用寿命和稳定性。
发明内容
针对现有技术存在上述技术问题，本实用新型提供一种能够缩小体积的IC芯片封装结构，该IC芯片封装结构具有容易封装、散热效果好和生产成本低的优点。
为实现上述目的，本实用新型提供以下技术方案：
提供一种IC芯片的封装结构，包括框槽、设于所述框槽上的与外部电连接的金属引体、固定于所述框槽内的IC芯片，所述IC芯片的电路管脚通过键合线与所述金属引体键合连接从而与外部电路进行电气连接，所述框槽内填充有封装胶，所述封装胶密封所述键合线和所述IC芯片的上表面和侧面。
其中，所述框槽包括槽壁和槽底，所述槽壁为由绝缘体形成的槽壁，所述槽底由绝缘体与所述金属引体构成。
其中，所述金属引体延伸至所述框槽的框内槽底。
其中，所述IC芯片通过粘合剂固定于所述框槽内。
其中，所述金属引体中的金属为铜、黄铜、白铜、铁、铝中的任意一种。
其中，所述绝缘体为PPA、PCT、陶瓷、玻璃、环氧树脂、硅树脂、硅胶中的任意一种。
其中，所述粘合剂为硅胶、硅树脂、环氧树脂、导电银胶中的任意一种。
其中，所述键合线为金线、银线、铜线、铝线、合金线中的任意一种。
其中，所述封装胶为环氧树脂、硅胶、硅树脂中的任意一种。
本实用新型的有益效果：
本实用新型的一种IC芯片的封装结构，将IC芯片固定在框槽内，然后使用封装胶进行封装，封装胶只需封装在IC芯片的上表面和侧面，克服了现有技术在IC芯片背面涂覆封装胶的问题，这样的好处是：其一、节约一半的封装胶从而节省成本；其二、使得IC芯片能较好地从背面散热以提高IC芯片的散热效果；其三、IC芯片背面无需涂覆封装胶，使生产工艺难度变小、生产周期缩短，还使得IC芯片在较小的框槽内即可放置好，框槽体积可设计得更小，从而利于节约电子器件的内部使用空间。
附图说明
图1为本实用新型一种IC芯片的封装结构的主视结构示意图；
图2为本实用新型一种IC芯片的封装结构的俯视结构示意图；
图3为本实用新型一种IC芯片的封装结构的侧视结构示意图。
附图标记：
框槽——1、金属引体——2、IC芯片——3、键合线——4、封装胶——5。
具体实施方式
以下结合具体实施例及附图对本实用新型进行详细说明。
本实施例中的一种IC芯片的封装结构，如图1至图3所示，设有框槽1，框槽1的槽壁是绝缘体，框槽1的槽底是由绝缘体和金属引体2构成，金属引体2延伸至框槽1的槽底。框槽1内放置了IC芯片3，金属引体2能够与外部电路电连接，金属引体2又通过键合线4与IC芯片3的电路管脚键合，从而使IC芯片3与外部电路进行电气连接。框槽1内填充有封装胶5，该封装胶5密封在IC芯片3的上面和侧面，同时也密封键合线4。其中，IC芯片3通过粘合剂固定于框槽1内。从整个结构看，框槽1形成一槽状，IC芯片直接放入即可，大大简化了加工的工序。
本实施例中，金属引体2中的金属为铜、黄铜、白铜、铁、铝中的任意一种，只要起到导电效果即可。
本实施例中，所述绝缘体为PPA、PCT、陶瓷、玻璃、环氧树脂、硅树脂、硅胶中的任意一种。
本实施例中，粘合剂为硅胶、硅树脂、环氧树脂、导电银胶中的任意一种。
本实施例中，键合线4为金线、银线、铜线、铝线、合金线中的任意一种。
本实施例中，封装胶5为环氧树脂、硅胶、硅树脂中的任意一种。
最后应当说明的是，以上实施例仅用以说明本实用新型的技术方案，而非对本实用新型保护范围的限制，尽管参照较佳实施例对本实用新型作了详细地说明，本领域的普通技术人员应当理解，可以对本实用新型的技术方案进行修改或者等同替换，而不脱离本实用新型技术方案的实质和范围。
Claims (9)
1.一种IC芯片的封装结构，其特征是：包括框槽、设于所述框槽上的与外部电连接的金属引体、固定于所述框槽内的IC芯片，所述IC芯片的电路管脚通过键合线与所述金属引体键合连接从而与外部电路进行电气连接，所述框槽内填充有封装胶，所述封装胶密封所述键合线和所述IC芯片的上表面和侧面。
2.根据权利要求1所述的一种IC芯片的封装结构，其特征是：所述框槽包括槽壁和槽底，所述槽壁为由绝缘体形成的槽壁，所述槽底由绝缘体与所述金属引体构成。
3.根据权利要求2所述的一种IC芯片的封装结构，其特征是：所述金属引体延伸至所述框槽的框内槽底。
4.根据权利要求1所述的一种IC芯片的封装结构，其特征是：所述IC芯片通过粘合剂固定于所述框槽内。
5.根据权利要求1所述的一种IC芯片的封装结构，其特征是：所述金属引体中的金属为铜、黄铜、白铜、铁、铝中的任意一种。
6.根据权利要求2所述的一种IC芯片的封装结构，其特征是：所述绝缘体为PPA、PCT、陶瓷、玻璃、环氧树脂、硅树脂、硅胶中的任意一种。
7.根据权利要求4所述的一种IC芯片的封装结构，其特征是：所述粘合剂为硅胶、硅树脂、环氧树脂、导电银胶中的任意一种。
8.根据权利要求1所述的一种IC芯片的封装结构，其特征是：所述键合线为金线、银线、铜线、铝线、合金线中的任意一种。
9.根据权利要求1所述的一种IC芯片的封装结构，其特征是：所述封装胶为环氧树脂、硅胶、硅树脂中的任意一种。
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Address after: 528400 1st floor, building 6, No.1 MuLinSen Avenue, Xiaolan Town, Zhongshan City, Guangdong Province Patentee after: Zhongshan Zhuoman Microelectronics Co.,Ltd. Address before: 528400 1st floor, building 6, No.1 MuLinSen Avenue, Xiaolan Town, Zhongshan City, Guangdong Province Patentee before: Zhongshan MuLinSen Microelectronics Co.,Ltd. |