CN202384315U - 晶体封装结构 - Google Patents

晶体封装结构 Download PDF

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Publication number
CN202384315U
CN202384315U CN 201120486653 CN201120486653U CN202384315U CN 202384315 U CN202384315 U CN 202384315U CN 201120486653 CN201120486653 CN 201120486653 CN 201120486653 U CN201120486653 U CN 201120486653U CN 202384315 U CN202384315 U CN 202384315U
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wafer
parallel
segment
adhesive body
utility
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彭兰兰
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body

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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

本实用新型公开了一种晶体封装结构，包括晶片，多个接脚和包覆在晶片四周的封胶体，所述的封胶体裸露出晶片的上表面；所述的接脚通过黏着材料固定于晶片的下表面两端，所述的接脚由上平行段、下平行段及一连接该两平行段的垂直段所构成，上平行段面积大于下平行段；所述的导线电性连接晶片的下表面与上平行段的下表面；所述的下平行段的外端和下表面裸露出封胶体外。本实用新型结构简单，有利于制造上的方便及节省制造成本，具有广阔的市场前景。

Description

晶体封装结构
技术领域
本实用新型涉及封装技术领域，尤其是一种晶体封装结构。
背景技术
一般集成电路的晶片较为脆弱，因此其外部必须进行适当的封装才能确保在使用时不易受外力的污染或破坏，而且必须将该晶片的电性适度低导接于一电路板或一导线架上，才能有效地使的电性透过该电路板或导线架传导给外部使用。
现有的改善晶片封装机构的常用的结构，仅是改变在于导线接脚的块状接脚下表面，并无法使封装结构缩小体积及无法有效散热且节省物料，也无法具有良好和稳定的电性导通。
因此，现有技术有待于改进和提高。
发明内容
本实用新型的目的在解决上述现有技术中存在的上述问题，提供一种可达到缩小晶体体积并易于散热且节省封胶体物料，以及具有良好且稳定的电性导通的晶体封装结构。
为达到上述目的，本实用新型所采用的技术方案是：一种晶体封装结构，包括晶片，多个接脚和包覆在晶片四周的封胶体，所述的封胶体裸露出晶片的上表面；所述的接脚通过黏着材料固定于晶片的下表面两端，所述的接脚由上平行段、下平行段及一连接该两平行段的垂直段所构成，上平行段面积大于下平行段；所述的导线电性连接晶片的下表面与上平行段的下表面；所述的下平行段的外端和下表面裸露出封胶体外。
与现有技术相比，本实用新型的有益效果是：由于采用上述结构，将晶片、接脚及导线包覆于封胶体内，接脚的外端和接脚下表面露出封胶体外，可以避免溢锡而达到较易聚锡且节省封胶体物料及便于目视定位与重工的目的，本实用新型将晶片电性连接于电路板上后，可达到缩小晶体体积并易于散热且节省封胶体无聊，以及具有良好且稳定的电性导通的功效。本实用新型结构简单，有利于制造上的方便及节省制造成本，具有广阔的市场前景。
附图说明
附图1为本实用新型晶体封装结构的结构示意图。
图中各标号分别是：（1）晶片，（2）封胶体，（3）接脚，（4）上平行段，（5）下平行段，（6）垂直段，（7）导线。
具体实施方式
下面结合附图对本实用新型作进一步的详细说明：
参看图1，本实用新型一种晶体封装结构，包括晶片1，多个接脚3和包覆在晶片1四周的封胶体2，所述的封胶体2裸露出晶片1的上表面；所述的接脚3通过黏着材料固定于晶片1的下表面两端，所述的接脚3由上平行段4、下平行段5及一连接该两平行段的垂直段6所构成，上平行段4面积大于下平行段5；所述的导线7电性连接晶片1的下表面与上平行段4的下表面；所述的下平行段5的外端和下表面裸露出封胶体2外。
以上所述，仅是本实用新型的较佳实施例而已，并非对本实用新型作任何形式上的限制，任何熟悉本专业的技术人员可能利用上述揭示的技术内容加以变更或修饰为等同变化的等效实施例，但是凡未脱离本实用新型技术方案内容，依据本实用新型的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本实用新型技术方案的范围内。

Claims (1)

1.一种晶体封装结构，包括晶片，多个接脚和包覆在晶片四周的封胶体，其特征是：所述的封胶体裸露出晶片的上表面；所述的接脚通过黏着材料固定于晶片的下表面两端，所述的接脚由上平行段、下平行段及一连接该两平行段的垂直段所构成，上平行段面积大于下平行段；所述的导线电性连接晶片的下表面与上平行段的下表面；所述的下平行段的外端和下表面裸露出封胶体外。
CN 201120486653 2011-11-30 2011-11-30 晶体封装结构 Expired - Fee Related CN202384315U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201120486653 CN202384315U (zh) 2011-11-30 2011-11-30 晶体封装结构

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CN 201120486653 CN202384315U (zh) 2011-11-30 2011-11-30 晶体封装结构

Publications (1)

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CN202384315U true CN202384315U (zh) 2012-08-15

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Granted publication date: 20120815

Termination date: 20121130