CN202018955U - 半导体封装模具 - Google Patents

半导体封装模具 Download PDF

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CN202018955U
CN202018955U CN2011200821221U CN201120082122U CN202018955U CN 202018955 U CN202018955 U CN 202018955U CN 2011200821221 U CN2011200821221 U CN 2011200821221U CN 201120082122 U CN201120082122 U CN 201120082122U CN 202018955 U CN202018955 U CN 202018955U
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frame body
cave
semiconductor packaging
packaging mold
air
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钟旭光
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SINGLE WELL PRECISION INDUSTRY (KUNSHAN) Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

本实用新型公开了一种半导体封装模具，它包括上模板、凹设于上模板一表面的上模穴，下模板、凹设于下模板一表面的且与上模穴形状相匹配的下模穴，上模穴与下模穴围绕成一封装腔，沿上模穴的边缘围设有一上框体，沿下模穴的边缘围设有一下框体，上框体与下框体相对应的端面均设有多个导气槽，导气槽与封装腔及外界均导通。本实用新型半导体封装模具通过改变传统的半导体封装模原来设置在角落的可让气体排除的导气槽的方位及数量来将多余的气体导出，避免气洞的产生，且能将溢出的塑料由导气槽导出。

Description

半导体封装模具
技术领域
本实用新型涉及一种封装模具，尤其是涉及一种半导体封装模具。
背景技术
目前，在半导体的封装领域中，通常以灌注塑料的方式将晶片及导线架封装于塑料固化形成的壳体内，借此防止受到外力伤害及方便运送，在封装前，需先将多组晶片及导线架放置在封装模具的上、下模板的模穴内，然后将预热的塑料注入塑料流道内，之后会启动具有主料功能的油压机，将塑料推进上、下模板的上、下模穴中，将晶片完全包覆，由于塑料的特性不同，在固话后经过烘烤、开模可取得半成品。在半导体封装成半成品时还需要经过去胶、去纬步骤，也就是利用冲压刀具去除溢出塑料，以及割除彼此相连的合模线，使得引脚各自独立，为了防止注胶时因为气体无法排除而导致制造出有气洞的不良品，目前在半导体封装模具的角落设有可让气体排除的气槽，但是仍无法完全避免漏洞的产生，此外，由于封装模具是在大面积的施加压力，因此会无法集中施加压力而导致塑料外溢。
发明内容
为克服上述缺点，本实用新型的目的在于提供一种可避免漏洞且在施压过程中塑料不外溢的半导体封装模具。
为了达到以上目的，本实用新型采用的技术方案是：一种半导体封装模具，它包括上模板、凹设于所述上模板一表面的上模穴，下模板、凹设于所述下模板一表面的且与所述上模穴形状相匹配的下模穴，所述上模穴与所述下模穴围绕成一封装腔，沿所述上模穴的边缘围设有一上框体，沿所述下模穴的边缘围设有一下框体，所述上框体与所述下框体相对应的端面均设有多个导气槽，所述导气槽与封装腔及外界均导通。
优选地，所述下框体与所述上框体相对应的端面上还设有多个仅与外界相导通的让位槽，用以减少接触面积来集中合模力，达到防止塑料外溢的效果。
优选地，每两个所述让位槽之间设有至少一个所述导气槽。
优选地，所述上、下框体相对应的一角缘处分别设有浇口，所述浇口与所述封装腔相导通。
优选地，所述浇口处连通有一塑料流道，用以供塑料流入所述封装腔内。
由于采用了上述技术方案，不难看出本实用新型通过改变传统的半导体封装模原来设置在角落的可让气体排除的导气槽的方位及数量来将多余的气体导出，避免气洞的产生，且能将溢出的塑料由导气槽导出，此外，增加了让位槽的设置可以用以减少接触面积来集中合模力，达到防止塑料外溢的效果。
附图说明
图1本实用新型半导体封装模具的上模板与下模板合模时内部装有晶片及导线架及注入塑料时的剖视图；
图2为本实用新型半导体封装模具的上模板以及下模板的立体结构示意图；
图3为图2中A处的局部放大图。
图中：
10-上模板；11-上模穴；12-上框体；121-导气槽；
20-下模板；21-下模穴；22-下框体；221-导气槽；222-让位槽；
30-封装腔；31-导线架；311-引脚；32-浇口；33-塑料流道；34-晶片；35-塑料。
具体实施方式
下面结合附图对本实用新型的较佳实施例进行详细阐述，以使本实用新型的优点和特征能更易于被本领域技术人员理解，从而对本实用新型的保护范围做出更为清楚明确的界定。
参见图1、图2所示，一种半导体封装模具，它包括上模板10、凹设于上模板10一表面的上模穴11，下模板20、凹设于下模板20一表面的且与上模穴11形状相匹配的下模穴21，上模穴11与下模穴21围绕成一封装腔30，相较于传统的封装模具，本实施例的半导体封装模具沿上模穴11的边缘还围设有一上框体12，且沿下模穴21的边缘围设有一下框体22，由于增加了上框体12及下框体22，则两个框体的端面具有一定的宽度，本实用新型则于上框体12与下框体22相对应的端面均设有多个导气槽121、221，导气槽121、221与封装腔30及外界均导通，原来设于封装模具角落的导气槽改设于上框体12及下框体22的相对应的端面，通过增加导气槽的数量来将多余的气体导出，从而避免气洞的产生。
参见图3所示的A处的局部放大图，为了能减少接触面积来集中合模力，达到防止塑料外溢的效果，则下框体22与上框体12相对应的端面上还设有多个仅与外界相导通的让位槽222，这里的让位槽222不与上模穴11及下模穴21导通，且每两个让位槽222之间设有至少一个导气槽221。
此外，上框体12与下框体22相对应的一角缘处分别设有浇口32，浇口32与封装腔30相导通，浇口32处连通有一塑料流道33，可将塑料从塑料流道33中引入浇口32从而流入封装腔30内。
在使用本实用新型的半导体封装模具时，如图1、图2所示，需预先放置晶片34及承载晶片34的导线架31，导线架具有多个引脚311，本实施例中的引脚311与让位槽222相互对应，最后在封装腔30内通过塑料流道33导入塑料35即可。
以上实施方式只为说明本实用新型的技术构思及特点，其目的在于让熟悉此项技术的人了解本实用新型的内容并加以实施，并不能以此限制本实用新型的保护范围，凡根据本实用新型精神实质所做的等效变化或修饰，都应涵盖在本实用新型的保护范围内。

Claims (5)

1.一种半导体封装模具，它包括上模板(10)、凹设于所述上模板(10)一表面的上模穴(11)，下模板(20)、凹设于所述下模板(20)一表面的且与所述上模穴(11)形状相匹配的下模穴(21)，所述上模穴(11)与所述下模穴(21)围绕成一封装腔(30)，其特征在于：沿所述上模穴(11)的边缘围设有一上框体(12)，沿所述下模穴(21)的边缘围设有一下框体(22)，所述上框体(12)与所述下框体(22)相对应的端面均设有多个导气槽(121、221)，所述导气槽(121、221)与封装腔(30)及外界均导通。
2.根据权利要求1所述的半导体封装模具，其特征在于：所述下框体(22)与上框体(12)相对应的端面上还设有多个仅与外界相导通的让位槽(222)。
3.根据权利要求1或2所述的半导体封装模具，其特征在于：每两个所述让位槽(222)之间设有至少一个所述导气槽(221)。
4.根据权利要求1所述的半导体封装模具，其特征在于：所述上、下框体(12、22)相对应的一角缘处分别设有浇口(32)，所述浇口(32)与所述封装腔(30)相导通。
5.根据权利要求4所述的半导体封装模具，其特征在于：所述浇口(32)处连通有一塑料流道(33)。
CN2011200821221U 2011-03-25 2011-03-25 半导体封装模具 Expired - Fee Related CN202018955U (zh)

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Address after: 215314, No. 266 East Changxin Road, Zhou Town, Jiangsu, Kunshan

Patentee after: Single Well Precision Industry (Kunshan) Co., Ltd.

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