CN201994295U - 一种高抗静电的led - Google Patents

一种高抗静电的led Download PDF

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CN201994295U
CN201994295U CN 201120037263 CN201120037263U CN201994295U CN 201994295 U CN201994295 U CN 201994295U CN 201120037263 CN201120037263 CN 201120037263 CN 201120037263 U CN201120037263 U CN 201120037263U CN 201994295 U CN201994295 U CN 201994295U
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led
solder joint
negative pole
led chip
pin
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林新忠
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Xiamen Xiarom Electronics Co Ltd
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Xiamen Xiarom Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

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Abstract

本实用新型涉及电子元器件，尤其涉及发光二极管。本实用新型的高抗静电的LED，是由负极引脚、正极引脚和LED芯片构成，其中LED芯片置于一绝缘基台上，并通过细导线分别焊接至上述的负极引脚和正极引脚的顶端的第一焊点和第二焊点上，再通过透光材料层封装成一体的结构。改进的，所述的透光材料层内还设有一齐纳管，并电性并联于上述的第一焊点和第二焊点上。本实用新型采用如上技术方案，通过在第一焊点和第二焊点之间电性并联于一齐纳管，即在LED芯片两端并联齐纳管，通过齐纳管吸收静电高压的冲击，从而实现保护LED芯片的目的。因此，本实用新型是一种高抗静电的LED元件。

Description

一种高抗静电的LED
技术领域
本实用新型涉及电子元器件，尤其涉及发光二极管（Light Emitting Diode ,LED）。
背景技术
LED(Light-Emitting-Diode) ，发光二极管，是一种能够将电能转化为可见光的固态的半导体器件，它可以直接把电转化为光。因其发光效率高、使用寿命长、环保、体积小等优势，被大量应用。已有的LED最常见的封装方式是：在一基座上固定LED芯片，并通过2根细导线（一般为金线）焊接至引脚末端的2个焊点上，再用透光的材料封装而成，或者有的为了产生一定颜色还在封装前加入荧光胶等物质。
已有的LED器件存在的不足之处在于：在安装或者运输过程中，可能受静电影响。静电的电压一般较高，而LED芯片无法承受高电压冲击，容易损坏LED器件的PN结。
实用新型内容
因此，本实用新型针对这个不足，提出一种高抗静电的LED器件。
本实用新型所采用的技术方案是：
一种高抗静电的LED，是由负极引脚、正极引脚和LED芯片、齐纳管构成，其中LED芯片置于一绝缘基台上，并通过细导线分别焊接至上述的负极引脚和正极引脚的顶端的第一焊点和第二焊点上，再通过透光材料层封装成一体的结构。改进的，所述的透光材料层内还设有一齐纳管，并且电性并联于上述的第一焊点和第二焊点上。
进一步的，所述的齐纳管一端固定于负极引脚的顶端的一处，另一端通过细导线焊接至第二焊点上，从而实现电性并联于上述的第一焊点和第二焊点的目的。由于齐纳管一端固定负极引脚上，就可以直接实现齐纳管一端与第一焊点的电性连接，另一端再通过细导线焊接至第二焊点上。可以节约一根细导线即可实现电性并联于上述的第一焊点和第二焊点的目的。
进一步的，和已有LED器件相同的，所述的负极引脚的顶端是设有第一焊点和一内凹的圆弧杯体的结构，所述的绝缘基台设置于该内凹的圆弧杯体。
因此，适于已有LED器件封装结构的，所述的齐纳管一端固定于负极引脚的内凹的圆弧杯体的边缘，另一端通过细导线焊接至第二焊点上。
进一步的，所述的细导线是金丝线。金属单质金的导电性能佳且耐腐蚀性高，因此细导线采用金丝线效果更佳。
本实用新型采用如上技术方案，通过在第一焊点和第二焊点之间电性并联于一齐纳管，即在LED芯片两端并联齐纳管，通过齐纳管吸收静电高压的冲击，从而实现保护LED芯片的目的。因此，本实用新型是一种高抗静电的LED器件。
附图说明
图1是已有的LED结构图。
图2是已有的LED的封装步骤一的示意图。
图3是已有的LED的封装步骤二的示意图。
图4是已有的LED的电气原理图。
图5是本实用新型的LED结构图。
图6是本实用新型的LED的封装步骤一的示意图。
图7是本实用新型的LED的封装步骤二的示意图。
图8是本实用新型的LED的电气原理图。
具体实施方式
现结合附图和具体实施方式对本实用新型进一步说明。
参阅图1、图2和图3所示，已有的LED器件是由负极引脚1、正极引脚2和LED芯片3构成。所述的负极引脚1的顶端是设有第一焊点102和一内凹的圆弧杯体101的结构。其中LED芯片3置于一绝缘基台6上，所述的绝缘基台6设置于该内凹的圆弧杯体101。LED芯片3的负极方电极301和正极圆电极302通过细导线4分别焊接至上述的负极引脚1和正极引脚2的顶端的第一焊点102和第二焊点201上，再通过透光材料层5封装成圆柱型灯帽的一体的结构。由于负极引脚1、正极引脚2是金属材料制成，通过细导线4的连接，可以实现LED芯片3的负极方电极301和正极圆电极302电性连接于LED器件的负极引脚1、正极引脚2。参阅图4所示，即为已有的LED的电气原理图。
参阅图5、图6和图7所示，本实用新型的LED同样的是由负极引脚1、正极引脚2和LED芯片3构成。所述的负极引脚1的顶端是设有第一焊点102和一内凹的圆弧杯体101的结构。其中LED芯片3置于一绝缘基台6上，所述的绝缘基台6设置于该内凹的圆弧杯体101。LED芯片3的负极方电极301和正极圆电极302通过细导线4分别焊接至上述的负极引脚1和正极引脚2的顶端的第一焊点102和第二焊点201上。不同的是，还设有一齐纳管7，并电性并联于上述的第一焊点102和第二焊点201上。所述的齐纳管7一端固定于负极引脚1的内凹的圆弧杯体101的边缘103，另一端通过细导线4焊接至第二焊点201上，从而实现电性并联于上述的第一焊点102和第二焊点201的目的。最后，再通过透光材料层5封装成圆柱型灯帽的一体的结构。参阅图8所示，即为本实用新型的LED的电气原理图。
优选的，所述的细导线4是金丝线。金属单质金的导电性能佳且耐腐蚀性高，因此细导线采用金丝线效果更佳。
本实用新型的生产工艺是： LED芯片镜检->LED扩片->自动点胶->LED自动固晶->LED固晶烘烤->LED压焊->LED封胶->LED固化与后固化->LED切筋->LED测试->LED包装。
经测试，原LED抗静电在1000V以下，本实用新型在现有工艺上加齐纳管使现有的LED抗静电可以达到5000V以上。
尽管结合优选实施方案具体展示和介绍了本实用新型，但所属领域的技术人员应该明白，在不脱离所附权利要求书所限定的本实用新型的精神和范围内，在形式上和细节上可以对本实用新型做出各种变化，均为本实用新型的保护范围。

Claims (6)

1.一种高抗静电的LED，是由负极引脚（1）、正极引脚（2）和LED芯片（3）构成，其中LED芯片（3）置于一绝缘基台（6）上，并通过细导线（4）分别焊接至上述的负极引脚（1）和正极引脚（2）的顶端的第一焊点（102）和第二焊点（201）上，再通过透光材料层（5）封装成一体的结构，其特征在于：所述的透光材料层（5）内还设有一齐纳管（7），并电性并联于上述的第一焊点（102）和第二焊点（201）上。
2.根据权利要求1所述的高抗静电的LED，其特征在于：所述的齐纳管（7）一端固定于负极引脚（1）的顶端的一处，另一端通过细导线（4）焊接至第二焊点（201）上，从而实现电性并联于上述的第一焊点（102）和第二焊点（201）的目的。
3.根据权利要求1所述的高抗静电的LED，其特征在于：所述的负极引脚（1）的顶端是设有第一焊点（102）和一内凹的圆弧杯体（101）的结构，所述的绝缘基台（6）设置于该内凹的圆弧杯体（101）。
4.根据权利要求2或3所述的高抗静电的LED，其特征在于：所述的齐纳管（7）一端固定于负极引脚（1）的内凹的圆弧杯体（101）的边缘，另一端通过细导线（4）焊接至第二焊点（201）上。
5.根据权利要求1或2所述的高抗静电的LED，其特征在于：所述的细导线（4）是金丝线。
6.根据权利要求4所述的高抗静电的LED，其特征在于：所述的细导线（4）是金丝线。
CN 201120037263 2011-02-12 2011-02-12 一种高抗静电的led Expired - Fee Related CN201994295U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104426050A (zh) * 2013-09-03 2015-03-18 中国科学院苏州纳米技术与纳米仿生研究所 半导体激光二极管及其封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104426050A (zh) * 2013-09-03 2015-03-18 中国科学院苏州纳米技术与纳米仿生研究所 半导体激光二极管及其封装方法
CN104426050B (zh) * 2013-09-03 2018-07-06 中国科学院苏州纳米技术与纳米仿生研究所 半导体激光二极管及其封装方法

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