CN200965882Y - 多芯片封装发光二极管 - Google Patents

多芯片封装发光二极管 Download PDF

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CN200965882Y
CN200965882Y CNU2006201482267U CN200620148226U CN200965882Y CN 200965882 Y CN200965882 Y CN 200965882Y CN U2006201482267 U CNU2006201482267 U CN U2006201482267U CN 200620148226 U CN200620148226 U CN 200620148226U CN 200965882 Y CN200965882 Y CN 200965882Y
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吴继德
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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Abstract

一种多芯片封装发光二极管，包括包括LED芯片1、基座10、发射碗2、封装树脂4、电极板12及组件，基座10上均匀布置有不少于三个LED芯片1，再用封装树脂4封装在一个器件内。本实用新型的优点是：在相同功率下，大大减少了器件个数；增大了单个器件的功率；单个器件可以适应几种工作电压；使用方便，有利于普及推广、节能、环保的第三代光源。

Description

多芯片封装发光二极管
所属技术领域
本实用新型涉及一种多芯片封装发光二极管。
背景技术
通常我们所见的发光二极管(简称LED)，一个器件内只封装了一个发光芯片，最多的(特殊用途)一个器件内封装3个发光芯片(红、绿、蓝三色发光芯片)，其外引线为4根，常见的LED的功率单器件大都在0.1瓦左右，即使是功率型LED单器件也只有1-2瓦，由于单个器件功率小，光通量也小，用于照明必须多个同时使用，常常需要几十个甚至几百个LED串联或并联，以增大功率，才能满足不同场合的照明要求。由于所用LED器件太多，使用很不方便。
发明内容
针对现有发光二极管的上述不足，本实用新型提供一种多芯片封装发光二极管。
本实用新型解决其技术问题所采用的技术方案是：本实用新型包括包括LED芯片1、基座10、发射碗2、封装树脂4、电极板12及组件，基座10上均匀布置有不少于三个LED芯片1，再用封装树脂4封装在一个器件内。基座10上设置有一个电极板12，电极板12上均匀布置有不少于三个LED芯片1，LED芯片1之间并联，再用封装树脂4封装在一个器件内。基座10上同时均匀布置有阳电极板6和阴电极板8，阳电极板6和阴电极板8上均布置有不少于二个LED芯片1，阳电极板6与阴电极板8上的LED芯片1用内连接线7连接，中间串接电阻11，每一个阳电极板6和阴电极板8连成一个组，组与组之间并联，再用封装树脂4封装在一个器件内。电极板12为矩形，在矩形电极板上均布置有不少于二个LED芯片1。
本实用新型的有益效果是：1、在相同功率下，大大减少了器件个数。2、增大了单个器件的功率。3、单个器件可以适应几种工作电压。4、使用方便，有利于普及推广、节能、环保的第三代光源。
附图说明
下面结合附图和实施例对本实用新型进一步说明。
图1为本实用新型实施例1 LED芯片在电极板上的布置示意图；
图2为本实用新型实施例1立体示意图；
图3为本实用新型实施例2 LED芯片在电极板上的布置示意图；
图4为本实用新型实施例2电路图；
图5为本实用新型实施例3 LED芯片在电极板上的布置示意图；
图6为本实用新型实施例3一组电极板放大示意图；
图7为本实用新型实施例4 LED芯片在电极板上的布置示意图。
图中，1.LED芯片，2.发射碗，3.外引线，4.封装树脂，5.阳极引出线，6.阳电极板，7.内连接线，8.阴电极板，9.阴极引出线，10.基座，11.电阻，12.电极板。
具体实施方式
实施例1：并联封装法。在一个公共电极板12(它可以是凹型、凸型、锥型、平面)上放置多个LED芯片1，均匀布置，封装在一个器件内，可大幅提高单个器件的功率，具体布置(见图1)。单个器件的LED引出线3最多为(封装发光芯片数+1)根，最少为2根引线，与普通LED的引线一样。
实施例2：串联、并联混合法。阳电极板6和阴电极板8组成一个组，在一个器件内封装几组或几十组LED芯片1，每组2根引线，均采用共阴极、共阳极，每个阴极板8、阳极板6上均布的LED芯片1可以是1个、2个、3个或者更多，阴极板8、阳极板6上LED芯片1的内连接线7通过限流电阻11连接，组与组之间并联，这种单器件有多组引出线，使用起来更具灵活性，可在器件的引出线之间，采用串联或并联的接线方式，以适应几种不同的电压，可以很方便实行功率控制。
实施例3：为蛛网型布置的72引线，36组LED芯片1，每组2根引线，均采用共阴极、共阳极，阳电极板6和阴电极板8上LED芯片1的内连接线7通过限流电阻11连接，组与组之间并联，这种单器件可以适应5种电压。
实施例4：外形为扁圆形封装的LED芯片1器件。这种器件的阳电极板6和阴电极板8组采用矩形，在矩形上均布多个LED芯片1，这种器件适合组成荧光灯之类的长条形LED灯具，可按需要组成不同功率的灯具，每个器件设计有连接固定孔，可用螺栓将其固定。还可将器件底座设计成燕尾槽型，也可以很方便实行多个组装。

Claims (4)

1.一种多芯片封装发光二极管，包括LED芯片(1)、基座(10)、发射碗(2)、封装树脂(4)、电极板(12)及组件，其特征在于：基座(10)上均匀布置有不少于二个LED芯片(1)，再用封装树脂(4)封装在一个器件内。
2.根据权利要求1所述的多芯片封装发光二极管，其特征在于：基座(10)上设置有一个电极板(12)，电极板(12)上均匀布置有不少于三个LED芯片(1)，LED芯片(1)之间串联，再用封装树脂(4)封装在一个器件内。
3.根据权利要求1所述的多芯片封装发光二极管，其特征在于：基座(10)上同时均匀布置有阳电极板(6)和阴电极板(8)，阳电极板(6)和阴电极板(8)上均布置有不少于一个LED芯片(1)，阳电极板(6)与阴电极板(8)上的LED芯片(1)用内连接线(7)连接，中间串接电阻(11)，再用封装树脂(4)封装在一个器件内。
4.根据权利要求1所述的多芯片封装发光二极管，其特征在于：电极板(12)为矩形，在矩形电极板上均布置有不少于二个LED芯片(1)。
CNU2006201482267U 2006-10-31 2006-10-31 多芯片封装发光二极管 Expired - Fee Related CN200965882Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102454878A (zh) * 2010-10-19 2012-05-16 展晶科技(深圳)有限公司 发光二极管模组

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102454878A (zh) * 2010-10-19 2012-05-16 展晶科技(深圳)有限公司 发光二极管模组
CN102454878B (zh) * 2010-10-19 2014-07-02 展晶科技(深圳)有限公司 发光二极管模组

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