CN1979834A - 半导体封装直接电性连接的基板结构 - Google Patents
半导体封装直接电性连接的基板结构 Download PDFInfo
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Abstract
本发明的半导体封装直接电性连接的基板结构包括:一具有至少一贯穿开孔的承载结构;至少一收纳于该承载结构开孔中的半导体芯片,其表面具有电性连接垫;至少一形成于该半导体芯片及承载结构上的线路增层结构,该线路增层结构中形成有导电结构以电性连接至该半导体芯片的电性连接垫;以及一局部设置于该承载结构下且封闭其开孔的散热片,使该散热片相接于半导体芯片;本发明的一种半导体封装直接电性连接的基板结构同时整合了半导体芯片及其承载件,通过该承载结构可提高其上电子元件的散热能力,通过控制接置面的平整性,提升了后续进行线路增层结构的制程与电性连接的可靠性,并增加了结构空间利用灵活性,提升电子装置电性质量。
Description
技术领域
本发明是关于一种半导体封装直接电性连接的基板结构,特别是有关于一种整合半导体芯片及其承载件的半导体构装结构。
背景技术
随着电子产业的蓬勃发展,电子产品在形态上趋于轻薄短小,在功能上则逐渐进入高性能、高功能、高速化的研发方向。为满足半导体封装件高集成度(Integration)以及微型化(Miniaturization)的封装需求,提供多个主、被动元件及线路载接的电路板(Circuit board)也逐渐由双层板演变成多层板(Multi-layer board),在有限空间下,借由层间连接技术(Interlayer connection)扩大电路板上可利用的电路面积,进一步配合高密度的集成电路(Integrated circuit)需求。
因电路板的导电迹线层数以及元件密度提高,配合高度集成化(Integration)半导体芯片运行产生的热量也会大幅增加,这些热量若不及时排除,会导致半导体封装件过热而严重威胁芯片寿命。目前,一般球栅阵列式(BGA)结构在更多脚数(1500pin)以上及高频5GHz以上已无法符合电性及散热性的需求。覆晶的球栅阵列式(FCBGA)结构则可以使用于更多脚数及更高频的产品,但整体的封装成本高,且在技术上仍有许多限制,尤其在电性连接部分,因为环保需求,使得电性连接材料,例如焊锡材料的铅(Pb)等将禁用,使用其它替代材料,其电性、机械及物性的质量不稳定。
为此,新的解决方法是将半导体直接埋入基板。如图1所示,它是美国第6,709,898号专利案提出的散热型半导体封装件。如图所示,该半导体封装件包括一散热板102,该散热板102具有凹部104;一半导体芯片114,该半导体芯片114的非主动面118是借由一热传导粘着材料120接置于该凹部104中;一线路增层结构122是借由增层技术形成于该散热板102及该半导体芯片114上。
请参阅图2,它是该散热板102的剖面视图,如图所示,该散热板102的凹部104从该散热板102的上表面延伸到该散热板102内部一定开孔深处。
请参阅图3,用于支撑该半导体芯片114元件的散热板102的金属材质呈单一金属材质,虽然可由半蚀刻(half etching)方式先完成形成接置半导体芯片114的凹部104,但因蚀刻的均匀性不易控制,使得该散热板102整版面的每一凹部104深度不一,且无法形成平整面,不利于半导体元件的植入及接点连接,其高度及均匀性更是难以控制,甚至会影响后续进行线路增层结构的制程质量与电性连接可靠性。
再者,电子产品缩小化已成为今后的发展趋势,并且以往单一功能形态的电子产品已无法再满足消费者的需求,如移动电话结合数字照相机的多功能(multiple function)电子产品等,使得随身型的电子产品不再仅有单一使用功能。为此电子产业的集成电路(integrated circuit,IC)向多功能、高性能的方向发展。如具有多种功能的集成电路,由于其能够提供多种不同的功能,以IC为主体架构,并在其输入/输出接点上连接不同的被动元件,如电阻、电容或电感等,即可组合成该IC所提供的功能。上述美国专利的散热型半导体封装件另外面临的问题即是,在该封装件结构中并无多余的空间可配置被动元件,因此无法做到完全的模块化,且缺乏配置空间用于连接其它电子元件,导致未能有效发挥集成电路的多功能变化的效能。
发明内容
为克服上述现有技术的问题,本发明的主要目的在于提供一种半导体封装直接电性连接的基板结构,可同时整合半导体芯片及其承载件并提升其散热能力。
本发明的次一目的在于提供一种可均匀控制承载件与半导体芯片接置面平整性的半导体封装直接电性连接的基板结构。
本发明的另一目的在于提供一种可提升后续进行线路增层结构的制程质量与电性连接可靠性的半导体封装直接电性连接的基板结构。
本发明的又一目的在于提供一种可增加结构空间利用灵活性的半导体封装直接电性连接的基板结构。
本发明的再一目的在于提供一种可有效整合主动及被动元件,提升电子装置电性质量的半导体封装直接电性连接的基板结构。
为达上述及其它目的,本发明提供一种半导体封装直接电性连接的基板结构,该半导体封装直接电性连接的基板结构包括:一承载结构,具有至少一贯穿开孔;至少一半导体芯片,收纳于该承载结构的贯穿开孔中,且该半导体芯片表面形成有电性连接垫;至少一线路增层结构,形成于该半导体芯片及承载结构上,且该线路增层结构中形成有多个导电结构,电性连接到该半导体芯片上的电性连接垫;以及一散热片,局部接置于该承载结构,以封闭其开孔的一侧,并与该半导体芯片相接合。另外,在该线路增层结构的表面线路上可设置多个导电元件,提供该结构与外界电子装置作电性连接。
本发明还涉及一种该半导体封装直接电性连接的基板结构,该该半导体封装直接电性连接的基板结构包括:一承载结构,具有至少一贯穿开孔且具有至少一线路层的电路板;至少一半导体芯片,收纳于该承载结构的贯穿开孔中,且该半导体芯片表面形成有电性连接垫;至少一线路增层结构,形成于该半导体芯片及承载结构上,且该线路增层结构中形成有多个导电结构,电性连接到该半导体芯片上的电性连接垫;以及一散热片,局部接置于该承载结构,以封闭其开孔的一侧,并与该半导体芯片相接合。
在本发明中,该承载结构可以是一电路板,其具有多个层间导电结构与线路结构,并可在该承载结构下表面未供设置有散热片的位置处接置有各种电子元件(如主动或被动元件等),且该电子元件可以借由电路板的线路结构、层间导电结构以及形成于该半导体芯片与电路板(承载结构)上的线路,进而与该半导体芯片电性连接,实现结构空间灵活应用与提升电性质量的目的。
在本发明的中,该承载结构也可以是多层结构,其各层中形成有至少一对应的开孔,愈往上层的开孔尺寸愈大,形成有容置区域,在该容置区域可设置各式电子元件,实现结构空间灵活应用的目的,且该承载结构可采用金属等高导热性材质,供接置于该多层承载结构的容置区域上的电子元件有效逸散热量;此外,该多层承载结构可采用电路板形式,在该电路板(承载结构)下表面未供设置有散热片的位置处另外接置有各种电子元件(如主动或被动元件等),且该电子元件可以借由电路板的线路结构、层间导电结构以及形成于该半导体芯片与电路板(承载结构)上的线路增层结构,与收纳于该承载结构中的半导体芯片及电子元件电性连接,借以提升电性质量。
综上所述,本发明的一种半导体封装直接电性连接的基板结构同时整合了半导体芯片及其承载件,通过该承载结构可提高其上电子元件的散热能力,该基板结构可均匀控制承载件与半导体芯片接置面平整性,提升了后续进行线路增层结构的制程质量与电性连接可靠性,由于该承载结构可以是多层结构,因此增加了结构空间利用灵活性,提升电子装置电性质量。
附图说明
图1是美国第6,709,898号专利案的半导体构装结构剖面示意图;
图2是美国第6,709,898号专利案的散热板的剖面示意图;
图3是图2所示的散热板在容置半导体芯片时产生缺失的局部剖面示意图;
图4是本发明的半导体封装直接电性连接的基板结构实施例1的剖面示意图;
图5是本发明的半导体封装直接电性连接的基板结构实施例2的剖面示意图;
图6是本发明的半导体封装直接电性连接的基板结构实施例3的剖面示意图;以及
图7是本发明的半导体封装直接电性连接的基板结构实施例4的剖面示意图。
具体实施方式
本发明所述的各实施例的附图,以示意方式说明本发明的基本架构,因此其仅显示本发明有关的构成,且显示的构成并非以实际实施的数目、形状及尺寸比例绘制,其实际实施时的数目、形状及尺寸为一种选择性的设计,且其构成布局形态可能更为复杂。
实施例1
请参阅图4,它是本发明的半导体封装直接电性连接的基板结构的剖面示意图,该半导体封装直接电性连接的基板结构40包括:一承载结构,该承载结构可以是一承载板400,构成该承载板400的材料可以是金属板或绝缘板,该承载板400中形成有至少一贯穿其表面的开孔400a;至少一半导体芯片43,收纳于该承载板开孔400a中,其表面具有可供电性连接的电性连接垫43a;至少一线路增层结构42,形成于该半导体芯片43与承载板400上,该线路增层结构42包括介电层420、形成于该介电层420上的线路层421以及贯穿该介电层420供电性连接到该线路层421的导电结构422,该导电结构422可例如是导电盲孔,且该导电结构422能够电性连接到收纳于该承载板400开孔400a中的半导体芯片43上的电性连接垫43a,其中该介电层420的材料可以是如纤维强化树脂、酚聚脂、环氧树脂层或光感应性树脂等,且设置在该半导体芯片43及承载板400上介电层420,是能够充填在该半导体芯片43与承载板400间的空隙;以及一散热片44,可通过一导热胶41局部设置在该承载板400上,封闭该承载板开孔400a,并使该散热片44可以与半导体芯片43相接合。再者,在该线路增层结构42表面可设置一防焊层45,该防焊层45形成有多个开孔,外露出该线路增层结构42外缘线路部分,供形成多个如焊球46等的导电元件,供该嵌埋于承载板400的半导体芯片43能够电性导接到外部装置。其中,该散热片44仅需局部设置在该承载板400上对应接置半导体芯片43处,为后续承载板400提供较大的空间用于容置其它电子元件。
实施例2
请参阅图5,它是本发明的半导体封装直接电性连接的基板结构实施例2的剖面示意图,本发明实施例2中的该半导体封装直接电性连接的基板结构50包括:一承载结构,该承载结构为一电路板500形式,该电路板500具有至少一贯穿其表面的开孔500a,另在该电路板500中形成有多条线路层500b,且这些线路层500b间可以借由电镀导通孔或导电盲孔等层间导电结构500c加以电性连接;至少一半导体芯片53,是收纳于该电路板开孔500a中,其表面具有可供电性连接的电性连接垫53a;至少一线路增层结构52,形成于该半导体芯片53及用以收纳该半导体芯片53的电路板500上,该线路增层结构52包括有介电层520、形成于该介电层520上的线路层521以及穿过该介电层520电性连接该线路层521的导电结构522,该导电结构522可以是导电盲孔,且该导电结构522可以电性连接到该电路板500表面线路层500b及收纳于该电路板开孔500a中的该半导体芯片53上的电性连接垫53a;以及,一散热片54,可通过一导热胶51局部设置在该电路板500上以封闭该电路板开孔500a,并与半导体芯片53相接合。本发明另可以一防焊层55覆盖于该线路增层结构52表面线路及该电路板500未为散热片54所覆盖的部分,且该防焊层55具有多个开孔以外露出该线路增层结构52表面线路部分及电路板500表面线路部分,在该线路增层结构52表面线路部分上形成多个如焊球56等的导电元件,供该嵌埋于电路板500的半导体芯片53能够电性导接到外部装置;以及多个电子元件57,接置于该电路板500一侧的防焊层55上,该电子元件57可以电性连接到该电路板500表面线路部分,其中该电子元件57可以是主动元件或被动元件。
因此,在本发明实施例2中的半导体封装直接电性连接的基板结构50与实施例1的结构大致相同,其主要差异是在于该实施例2中的承载结构是采用电路板形式,该电路板500中形成有多条线路层500b,且这些线路层500b间可以借由电镀导通孔或导电盲孔等层间导电结构500c加以电性连接。当然该电路板500也可以其他具有线路层的形式,非仅以如图5所示的电路板结构为限。如此,后续即可在该电路板500(承载结构)未形成线路增层结构52的一侧形成防焊层55,该防焊层55形成有多个开孔以外露出该电路板500表面线路层部分,用于接置多个如主动元件或被动元件等电子元件57,该电子元件57可以通过该电路板500的线路层500b与层间导电结构500c电性连接到该线路增层结构52,进而与收纳于该电路板开孔500a的半导体芯片53电性导接,借以提升电性质量。
实施例3
请参阅图6,它是本发明的半导体封装直接电性连接的基板结构实施例3的剖面示意图,在本发明实施例3中的半导体封装直接电性连接的基板结构60是与实施例1大致相同,其主要差异是在于该承载结构61是一多层承载板形式,如图所示该承载结构61包括第一承载板600及第二承载板601,该第一、第二承载板600、601可以是金属板、绝缘板、电路板,且该第一、第二承载板600、601各具有至少一穿透其表面的开孔600a、601a,该第二承载板开孔601a尺寸是大于第一承载板开孔600a的尺寸,且该第二承载板601的开孔601a位置是对应于该第一承载板600的开孔600a位置,将该第二承载板601接置于该第一承载板600上,形成多个容置空间,用于收纳半导体芯片63及电子元件68,同时再通过至少一形成于该半导体芯片63、电子元件68及第二承载板601上的线路增层结构62,可以将该半导体芯片63及电子元件68作电性连接。其中,一散热片64可通过一导热胶65局部设置于该第一承载板600上对应接置半导体芯片63处,为后续承载结构61提供较大的空间,用于容置其它电子元件。
此外,该承载结构61可采用金属或陶瓷等散热材质,供接置于该多层承载结构容置区域上的电子元件68有效逸散热量。再者,该承载结构61并非仅以二层结构为限,它可任意扩充到多层结构,借以提供电子元件更多的容置空间。
实施例4
请参阅图7,它是本发明的半导体封装直接电性连接的基板结构的剖面示意图,本发明实施例4中的半导体封装直接电性连接的基板结构70与实施例2大致相同,其主要差异是在于该承载结构是一多层电路板700形式,且在该电路板700下半部形成有第一开孔700a,在该电路板上半部形成有第二开孔701a,该第二开孔701a是对应于第一开孔700a位置,且该第二开孔701a尺寸是大于第一开孔700a的尺寸,借以形成有多个容置空间以供收纳半导体芯片73及电子元件78,同时再通过至少一形成于该半导体芯片73、电子元件78及电路板700上的线路增层结构72,可以将该半导体芯片73及电子元件78作电性连接,借以提升电性功能;再者,在该电路板700中形成有多个线路层700b,且这些线路层700b间可以借由电镀导通孔或导电盲孔等层间导电结构700c加以电性连接。如此,后续即可在该电路板700(承载结构)未供形成线路增层结构72的一侧形成防焊层75,该防焊层75形成有多个开孔以外露出该电路板表面线路层部分,用于接置多个如主动元件或被动元件等电子元件77,该电子元件77可以通过该电路板700的线路层700b与层间导电结构700c,电性连接到该半导体构装结构的线路增层结构72,与收纳于该电路板第一、第二开孔700a、701a的半导体芯片73及电子元件78进行电性导接。其中,一散热片74,可通过一导热胶71局部设置于该电路板700上对应接置半导体芯片73处,同时为该电路板700提供较大的空间,用于容置其它电子元件。
Claims (19)
1.一种半导体封装直接电性连接的基板结构,其特征在于,该半导体封装直接电性连接的基板结构包括:
一承载结构,具有至少一贯穿开孔;
至少一半导体芯片,收纳于该承载结构的贯穿开孔中,且该半导体芯片表面形成有电性连接垫;
至少一线路增层结构,形成于该半导体芯片及承载结构上,且该线路增层结构中形成有多个导电结构,电性连接到该半导体芯片上的电性连接垫;以及
一散热片,局部接置于该承载结构,以封闭其开孔的一侧,并与该半导体芯片相接合。
2.如权利要求1所述的半导体封装直接电性连接的基板结构,其特征在于,该承载结构是金属板或绝缘板。
3.如权利要求1所述的半导体封装直接电性连接的基板结构,其特征在于,该承载结构是一多层承载板形式,上层承载板开孔尺寸是大于下层承载板开孔尺寸,且这些开孔位置是相互对应。
4.如权利要求3所述的半导体封装直接电性连接的基板结构,其特征在于,该多层承载板的开孔中可容置半导体芯片及电子元件。
5.如权利要求4所述的半导体封装直接电性连接的基板结构,其特征在于,该半导体芯片及电子元件是与线路增层结构相互电性连接。
6.如权利要求1所述的半导体封装直接电性连接的基板结构,其特征在于,该线路增层结构包括介电层、叠置在该介电层上的线路层以及形成于该介电层中的导电结构。
7.如权利要求6所述的半导体封装直接电性连接的基板结构,其特征在于,该介电层可以充填在该半导体芯片与承载结构间的空隙。
8.如权利要求1所述的半导体封装直接电性连接的基板结构,其特征在于,该线路增层结构的外表面植置有多个导电元件。
9.如权利要求1所述的半导体封装直接电性连接的基板结构,其特征在于,该导电结构是导电盲孔。
10.一种半导体封装直接电性连接的基板结构,其特征在于,该半导体封装直接电性连接的基板结构包括:
一承载结构,具有至少一贯穿开孔且具有至少一线路层的电路板;
至少一半导体芯片,收纳于该承载结构的贯穿开孔中,且该半导体芯片表面形成有电性连接垫;
至少一线路增层结构,形成于该半导体芯片及承载结构上,且该线路增层结构中形成有多个导电结构,电性连接到该半导体芯片上的电性连接垫;以及
一散热片,局部接置于该承载结构,以封闭其开孔的一侧,并与该半导体芯片相接合。
11.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,该半导体封装直接电性连接的基板结构还包括至少一电子元件,是接置于该承载结构未形成线路增层结构的一侧,且该电子元件是电性连接到该承载结构的线路层。
12.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,该承载结构是单层电路板或多层电路板。
13.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,电路板上半部及下半部形成有开孔,其中电路板上半部开孔尺寸是大于电路板下半部开孔尺寸,且这些开孔位置是相互对应。
14.如权利要求13所述的半导体封装直接电性连接的基板结构,其特征在于,该承载结构的开孔中是可容置半导体芯片及电子元件。
15.如权利要求14所述的半导体封装直接电性连接的基板结构,其特征在于,该半导体芯片及电子元件可与线路增层结构相互电性连接。
16.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,该线路增层结构包括介电层、叠置在该介电层上的线路层以及形成于该介电层中的导电结构。
17.如权利要求16所述的半导体封装直接电性连接的基板结构,其特征在于,该介电层是充填在该半导体芯片与承载结构间的空隙。
18.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,该线路增层结构的外表面植置有多个导电元件。
19.如权利要求10所述的半导体封装直接电性连接的基板结构,其特征在于,该导电结构是导电盲孔。
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CN102194802A (zh) * | 2010-03-19 | 2011-09-21 | 林总贤 | 电子组装体 |
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