CN1940973A - 闪存卡 - Google Patents

闪存卡 Download PDF

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Publication number
CN1940973A
CN1940973A CNA2006100726837A CN200610072683A CN1940973A CN 1940973 A CN1940973 A CN 1940973A CN A2006100726837 A CNA2006100726837 A CN A2006100726837A CN 200610072683 A CN200610072683 A CN 200610072683A CN 1940973 A CN1940973 A CN 1940973A
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flash memory
flash
substrate
intermediary
controller
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CN100492406C (zh
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陈维斌
葛维沪
陈弘典
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KINGSTON TECHNOLOGY FAR EAST C
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KINGSTON TECHNOLOGY FAR EAST C
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Abstract

一种存储卡包含基板、位于该基板上之存储器晶元、位于该存储器晶元上之控制器晶元以及中介物，该中介物围绕该控制器晶元且位于该存储器晶元上，其中该中介物使得线接合至该基板最少化。一种系统及方法可达成下列目的：(1)通过减少基板上的线接合垫数目以及置入可装设进卡内侧边界之尽可能大的晶元，以增加存储卡的密度；(2)如有必要堆叠时，更有效率地堆叠闪存晶元，以增加闪存卡的密度；(3)仅需少量必要的信号输入/输出接合线至基板，以改善生产合格率。

Description

闪存卡
技术领域
本发明涉及一种闪存，更详细来说，涉及一种高密度之闪存卡。
背景技术
闪存卡之应用主要为大众消费电子产品所需要，例如数码相机(digitalstill camera)、手机、PDA或者MP3播放器等，这些产品皆朝向更小的封装方式以及高密度发展。当封装方式变得更迷你且元件密度变得更高的时候，以创新的方法包含多个闪存元件于特定闪存卡的有限空间内之需求便被提出来。
公知技术在处理更高密度包装闪存卡时是通过线接合一个或多个闪存晶元和一个闪存控制器来达成。在物理尺寸上，闪存晶元通常远大于闪存控制器晶元。闪存晶元和闪存控制器是各自独立地线接合在闪存卡的基板上。
基板通常有互连轨迹用以联系闪存控制器、闪存晶元以及闪存卡界面中的信号，接着基板被用树脂塑形或者以外壳覆盖，最后制造成完工的闪存卡。
举例来说，假如有大约40个信号和接合垫在控制器上，且大约20个信号和接合垫在每一个闪存晶元上，若闪存控制器晶元和闪存晶元两者皆利用线接合与基板相联系，则会产生布置上之限制。传统上，一个闪存晶元的设计需要60个接合垫于基板上，每多增加一个闪存晶元需要20个以上的接合垫，因此，闪存晶元的尺寸必须较小以留下空间给线接合垫。再者，由于应用于多层晶元层之错综式接合线(staggering bonding wires)的必要性，也会产生生产合格率上的问题。
综上所述，一种系统和方法用以提供高密度、较小的封装方式的闪存卡以应对前述的问题是需要的，此系统必须能简单实施、节省成本以及适用于现有的环境。本发明实为迫切需要。
发明内容
一种存储卡包含基板、存储器晶元、控制器晶元以及中介物，该存储器晶元位于该基板上，该控制器晶元位于该存储器晶元上，该中介物围绕该控制器且位于该存储器晶元上，其中该中介物使得线接合至该基板实质上得以缩减。一种根据本发明之系统及方法可达成下列目的：(1)尽可能的利用大号的存储器晶元，通过缩减基板上的线接合垫数目及嵌入尽可能大之晶元至给定之卡内围，以增加闪存卡的密度；(2)更有效地堆叠闪存晶元以增加闪存卡的密度；以及(3)尽可能地实质缩减连接到基板上的接合线的数目，以改善生产合格率。
附图说明
图1为闪存卡示意图；
图2为公知闪存卡之线接合基板之俯视图；
图3为公知闪存卡之线接合基板之剖面图；
图4为公知来自多层晶元之错综式接合线之俯视图；
图5为公知来自多层晶元之错综式接合线之剖面图；
图6为具有中央裁切区以容纳闪存控制器晶元之晶元中介物之俯视图；
图7为具有中央裁切区以容纳闪存控制器晶元之晶元中介物之剖面图；
图8为堆叠两个闪存晶元设计之剖面图；
图9为堆叠两个闪存晶元设计之侧视图；
图10为堆叠三个闪存晶元设计之剖面图；
图11为堆叠三个闪存晶元设计之侧视图；以及
图12为回圈高度与两个接合垫之间的横向距离的函数表示图。
主要元件标记说明
10：闪存卡             11：闪存卡界面
12：闪存控制器         13：闪存控制器
18：导线               19：接合垫
20：导线               21：闪存卡
22：基板               23：闪存晶元
24：控制器晶元         25：接合垫
26：接合垫             27：接合垫
34：轨迹               35：接合垫
36：轨迹               37：轨迹
38：导线               118：导线
119：接合垫            120：导线
122：基板              123：闪存
124：闪存控制器晶元    125：接合垫
126：接合垫            127：接合垫
133：闪存卡界面        134：轨迹
135：接合垫            138：导线
151：导线              152：导线
153：D2                154：D1
155：H2                156：H1
219：接合垫            221：闪存卡
222：基板              223：闪存晶元
224：闪存控制器晶元    225：接合垫
226：接合垫            227：接合垫
228：裁切区            233：闪存卡界面
235：接合垫            238：导线
240：接合垫            242：中介物
243：连接轨迹          244：连接轨迹
318：接合垫            319：接合垫
321：闪存卡            322：基板
323：闪存晶元          324：闪存控制器晶元
326：接合垫            327：接合垫
342：中介物            345：间隔物
423：闪存晶元          445：间隔物
523：闪存晶元
具体实施方式
本发明涉及一种闪存，更详细来说，涉及一种高密度之闪存卡。以下说明用以使所属技术领域的技术人员得以实施及使用本发明，且用以专利申请并符合其相关规定。在此列举之实施例、一般原理及特征可迅速地被所属技术领域的技术人员所了解，故本发明之实施方式并非用来限制本发明之范畴，本发明之权利范围应根据在此说明之原理及特征作最宽的解释。
图1所示为一种公知的闪存卡10，此闪存卡10包含闪存卡界面11、闪存控制器12以及一个或多个闪存晶元13。闪存卡界面11通常以连接器或是金手指接触点(gold finger contacts)之形式，作为与诸如数码相机、手机、PDA、MP3播放器或者个人计算机等之主机装置的沟通桥梁。闪存控制器12控制位于卡上的闪存13，并且透过闪存卡界面11响应来自这些主机装置的要求。
工艺上，闪存控制器12和闪存13嵌在一片基板上，该基板具有内建闪存卡界面11以及在控制器12与存储器13间的连接轨迹。闪存控制器12和闪存13可以是裸晶元形式或是已包装形式。本发明特别着重于使用至少两个裸晶元半导体元件，且这两个元件具有不同晶元尺寸的应用。
工艺上，公知利用晶元形式元件之闪存卡倾向于采取两个方式的其中一个，其为并排方式(side-by-side approach)和堆叠方式，以下将详细说明此两种方式。
图2为一个较大闪存晶元23之公知布局方式，以及以并排方式位于基板22的一边之较小控制器晶元24的俯视图。图3为如同图2所示相同布局的剖面图。
在如图2所示之并排方式中，闪存控制器24和闪存晶元23并排放置于基板22上，导线18、20及38分别连接两晶元上的接合垫19、27及40至在基板22上的接合垫25、26及35。基板22需要大约30个接合垫以容纳闪存控制器24的连接，另外需要额外的20个接合垫以容纳闪存晶元23的连接。如图3所示，基板22是由内部轨迹34、36及37层压组合以连接闪存控制器24、闪存晶元23及闪存卡界面33。并排方式的工艺是相对比较简单的，然而，因为基板22上总共需要50个接合线和接合垫，严格地限制了能使用于给定闪存卡21的闪存和闪存控制器的尺寸。
图4为一个较大闪存晶元123以及以堆叠方式位于基板122的一边之较小控制器晶元124之公知布局方式的俯视图。图5为如同图4所示相同布局的剖面图。
在如图4所示之堆叠方法中，闪存控制器晶元124被放置于在基板122上之闪存晶元123上，导线118、120及138分别连接两晶元上的接合垫119、127及140至下方基板122的接合垫125、126及135。由于采用多层堆叠的方式，错综式的线接合是必须的。基板122需要大约30个接合垫以容纳闪存控制器124的连接，另外需要额外的20个接合垫以容纳闪存晶元123的连接。如图5所示，基板122是通过轨迹134层压以连接闪存控制器124、闪存晶元123及闪存卡界面133。由于错综式的线接合方式需要基板122更多的空间以分配接合垫和导线，使得闪存晶元的尺寸受到限制，基板需要空间以容纳总共50个额外的接合线和接合垫。由于闪存控制器被放置于闪存晶元上，因此相对于并排方式，闪存控制器晶元尺寸上的限制与并排方式相比是比较少的。当两者差不多相等，且基板有可利用的共同空间时，较大的控制器晶元将会缩减该闪存的尺寸。
本发明兼顾公知并排方式及堆叠方式于闪存晶元的尺寸限制，本发明更节省基板上周围线接合的空间以及简化线接合的复杂度。因此，可容纳更多存储器的较大晶元尺寸且可用于并排方式或是堆叠方式。
本发明之系统和方法可解决上述之问题而达到以下的目的：(1)通过缩减基板上的线接合垫数目，尽可能地放置最大的闪存晶元于给定的几何空间内，以达到最大化闪存卡的密度；(2)如有需要，能够有效地堆叠闪存晶元，以增加闪存卡的密度；(3)尽可能地减少连接至基板之接合线以改善生产合格率。
为了更仔细地描述本发明的特征，请参见以下之详述并参阅相关之附图。
图6为本发明之闪存卡之俯视图，其布局包含位于基板222上之较大的闪存晶元223、中央裁切区中介物242以及闪存控制器晶元224。图7为图6布局之剖面图。
在本实施例中，如图6所示，中介物242位于在基板222上之闪存晶元223上，中介物242之材质类似于基板222，其具有接合垫及预先安排好之连接轨迹243及244，其亦可以是一种薄的、用铜/聚酰亚胺制造之单金属层软板(1-metal layer flex circuit)。中介物242之尺寸恰好足以使得其接合垫227位于暴露闪存晶元接合垫226的旁边。如同图6及图7所示，中介物242具有接合垫227及225分别合适地安排以靠近下方闪存晶元223及中央的闪存控制器晶元224相对应之接合垫226及219，其亦具有相对应之接合垫240合适地安排以连接在主基板222上方且在闪存晶元下方之接合垫235。如图7所示，这些由中介物242而来的导线238是唯一用以连接到基板222，且通过基板222上之轨迹234依次连接至闪存卡界面233。
不同于公知方式，本发明几乎转移所有从晶元到下方的基板222的连接线路至闪存卡221上方的中介物242。通过改变基板上的接合垫数目由50个左右减少到低于10个(节省了80％)，以实质地减少基板222所需的接合垫空间，这也使得由于空间供应给接合垫而导致无法实现之实质较大闪存晶元，在节省基板222的空间后变为可能。再者，通过使用中介物242，闪存控制器晶元224不需要直接放置在基板222上，因此于闪存控制器晶元的尺寸上具有较少的限制，这与公知堆叠方式有相同的好处。一般而言，本发明改善了闪存晶元尺寸与实际闪存卡尺寸之比例，自大约62％达到90％或更高。本发明允许较大的闪存晶元，因此可使用较高密度的晶元于同样的闪存卡221设计。
如图6及图7所示，当闪存控制器晶元224堆叠于中介物242上，亦即位于闪存晶元223上时，为了不增加额外的高度，中介物242具有位于中间区域之裁切区228，该裁切区228足以容纳闪存控制器晶元224。闪存控制器晶元224像一个岛屿直接坐落在闪存晶元223上，而不是位于中介物242上。
如图8及图9所示，若需要堆叠更多的闪存晶元，则可使用在晶元上之可弯曲电路中介物342。如图10及图11所示，需注意如果有必要的话，此可弯曲的中介物342可被折迭成弯曲的样子来扩展更多的闪存晶元堆叠323、423及523。
图8为依照本发明使用之两个闪存晶元323及423、在晶元上之可弯曲的电路中介物342以及位于基板322上之闪存控制器晶元324之布局之剖面图。图9为图8所示之布局之侧视图。
如图8及图9所示，间隔物345在闪存控制器晶元324及堆叠于其上的闪存晶元423之间是需要。如图10及图11所示，假如需要更多的堆叠闪存晶元523，额外的间隔物445是必要的。
图10为依照本发明应用之三个闪存晶元323、423及523、在晶元上之可弯曲电路中介物342以及位于基板322上之闪存控制器晶元324之布局剖面图。图11为图10之布局之侧视图。
间隔物345及445之高度小于公知堆叠闪存卡设计，理由是此间隔物的高度为线接合回圈高度(wire bonding loop height)的函数，较低的回圈高度需要较低的间隔物高度。如图12所示，回圈高度亦为两个接合垫之间的横向距离的函数。
如图12所示，接合垫A及接合垫B之间的距离为D1 154，接合垫A及接合垫C之间的距离为D2 153。导线151和152分别提供给这两对接合垫，其相对应的回圈高度分别为H1 156及H21 55。较短的横向距离D1154需要有较小的回圈高度H1 156。如图11所示，由于使用中介物342，中介物342及闪存晶元523、423及323间相对应的接合垫327及326能够物理上地互相邻近。如图10所示，中介物342及闪存控制器晶元324间相对应的接合垫319及318能够物理上地互相邻近。因此于每个相对应的接合垫之间能够具有最短的导线，故产生最小的决定性的回圈高度。较小的间隔物345及445之整体效能会增加更多闪存晶元323、423及523之堆叠高度的可能性，因此达到闪存卡321的更高密度。
替代性实施例
一替代性实施例是放置控制器单元于闪存晶元的中间，且在不需要晶元中介物之情况下直接使用晶元对晶元(die-to-die)线接合。
另一替代性实施例是于闪存上形成晶元再分配层(redistribution layer)以代替晶元中介物，唯一不同处在于再分配层可在闪存晶圆上制成，而中介物通常在基板组合时才置入个别的闪存晶元。
其它替代性实施例为使用可弯曲的基板，而不使用晶元上的可弯曲中介物。
相较于已有技术之优点
不同于公知方式将所有来自闪存控制器及闪存晶元上之接合垫之所有接合线连接至基板，本发明之闪存卡利用如图6所示之晶元中介物缩减接合线的数目。如图7及图8所示，中介物位于闪存晶元上，以接合垫及轨迹来连接闪存控制器晶元、闪存晶元及闪存卡界面。由于闪存卡界面信号被限制在一定的数目(少于10)，且通常被闪存控制器所控制，因此它们是唯一需要被线接合至基板上之信号，这将惊人地缩减基板上的线接合垫数目从约50个至低于10个，缩减80％。
本发明接合线的长度将比公知方式更平均地分布在晶元中介物，与图4所示之公知闪存晶元堆积情况相比，没有接合线需要跨越其它导线。
如同图4之公知晶元尺寸及图6之本发明晶元尺寸所示，使用晶元中介物以线接合连接于闪存晶元及闪存控制器间可有效地减少基板上之线接合空间，同时允许使用尽可能大的闪存晶元于闪存卡上。
使用直接线接合之晶元中介物以节省基板周边线接合空间。
使用中央裁切区之晶元中介物以容纳闪存控制器晶元，如图9所示，这缩减了整体的高度并且允许更高的密度。
使用可弯曲的电路晶元中介物使得闪存晶元堆叠能够扩张。
通过临近适合的中介物垫，本发明亦缩减了线接合长度，更缩减了接合线的回圈高度，进而允许使用较薄的间隔物，因此，可堆叠更多闪存晶元于相同闪存卡上。
上述所列举之实施例仅用来例举本发明之实施方式，以及阐释本发明之技术特征，并非用来限制本发明之范畴。任何所属技术领域的技术人员均可在不违背本发明之技术原理及精神的情况下，对上述实施例进行修改及变化，因此本案之权利范围应以权利要求所主张之内容为依据。

Claims (12)

1.一种存储卡，其特征是包含：
基板；
存储器晶元，位于该基板上；
控制器晶元，位于该存储器晶元上；以及
中介物，耦接于该控制器晶元，且位于该存储器晶元上，其中该中介物使得线接合至该基板最少化。
2.根据权利要求1所述之存储卡，其特征是该中介物围绕该控制器。
3.根据权利要求1所述之存储卡，其特征是该中介物位于该控制器上。
4.根据权利要求2所述之存储卡，其特征是包含：
第二存储器晶元，耦接至该中介物；以及
间隔物，用以隔开该存储器晶元与该第二存储器晶元；
其中，该存储器晶元与该第二存储器晶元通过线接合电连接至该中介物。
5.根据权利要求1所述之存储卡，其特征是该中介物包含多个接合垫以及至少一个连接轨迹。
6.根据权利要求2所述之存储卡，其特征是该中介物包含位于中间区域之裁切区，该裁切区足以容纳该控制器晶元。
7.根据权利要求1所述之存储卡，其特征是该中介物包含弯曲部，该弯曲部可弯曲位于晶元部件上。
8.根据权利要求2所述之存储卡，其特征是该控制器晶元之高度是根据围绕该控制器晶元之该中介物以最小化。
9.根据权利要求4所述之存储卡，其特征是该间隔物之高度为该线接合回圈高度之函数。
10.一种闪存卡，其特征是包含：
基板；
第一存储器晶元，位于该基板上；
闪存控制器晶元，位于该第一存储器晶元上；
弯曲中介物，耦接该第一闪存晶元上，其中该弯曲中介物使得线接合至该基板最少化；
至少一个其它闪存晶元，其中该闪存耦接于该弯曲中介物；以及
间隔物，用以隔开该第一闪存晶元与该第二存储器晶元。
11.根据权利要求10所述之存储卡，其特征是该弯曲中介物包含多个接合垫以及至少一个连接轨迹。
12.根据权利要求10所述之存储卡，其特征是该弯曲中介物包含位于中间区域之裁切区，该裁切区足以容纳该闪存控制器晶元。
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