TWI310193B - Flash memory card - Google Patents

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Publication number
TWI310193B
TWI310193B TW095111485A TW95111485A TWI310193B TW I310193 B TWI310193 B TW I310193B TW 095111485 A TW095111485 A TW 095111485A TW 95111485 A TW95111485 A TW 95111485A TW I310193 B TWI310193 B TW I310193B
Authority
TW
Taiwan
Prior art keywords
flash
flash memory
memory cell
controller
memory card
Prior art date
Application number
TW095111485A
Other languages
English (en)
Other versions
TW200713301A (en
Inventor
Ben Chen
Wei H Koh
David Hung-Dien Chen
Original Assignee
Kingston Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kingston Technology Corp filed Critical Kingston Technology Corp
Publication of TW200713301A publication Critical patent/TW200713301A/zh
Application granted granted Critical
Publication of TWI310193B publication Critical patent/TWI310193B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5388—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates for flat cards, e.g. credit cards
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

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1310193 九、發明說明： 【發明所屬之技術領域】 係關於一種 一本發明係關於一種快閃記憶體，更詳細來說 高密度之快閃記憶卡。 【先前技術】 ^之f社縣大眾消費電子產品所需要，例如 數位相機(digital still camera)、手機、pDA 或者 Mp3 這些產品皆朝肖更小的封裝方式以及高密度發展 變得更迷你且元件密度變得更高的時候，以創新“" 出來 山 ydi « ' 1 内之需求便被提 習知技術在處理更高密度包裝快閃記憶卡時係藉由線接 。-個或多個快閃記麵晶元和—快閃控·來達成。在^理 尺1上，快閃記憶體晶元通常遠大於快閃控 元和快閃控制器是各自獨立地線接合在心記=的 元以軌!用以聯繫快閃控制器、快閃記憶體晶 卡介面中的訊號，接著基版被麟脂塑形或者 以外级覆盍，最後製造成完工的快閃記憶卡。 舉例來說’假如有大約4〇個峨 =^=兩=_=快 上的接口垫，因此，快閃記憶體晶元的尺寸 1310193 必須較，i:以留下空間給線接合塾。再者，由於應用在複數晶元 層之錯綜式接合線(staggering bonding wires)的必要性，也舍產 生生產良率上的問題。 $座 綜上所述，-種系統和方法用以提供高密度、較小的封 方，的快閃記針以應付前述的問殿需要的，H統必須能 簡單實施、節錢本以及翻於财崎境。本發明實 需要。 m 【發明内容】 二種記憶卡包含-基版、-記憶體晶元一控制器晶元以 及一中介物’該記憶體晶元位於該基版上，該控制器晶元位於 該記憶體晶it上’該中介物圍繞該控制器且位於該記憶體晶元 上’其中該中介物使得線接合至該基版實質上得以縮減。一種 根^本，明之系統及方法可達成下列目的：⑴儘可能的利用 大置的6己憶體晶元’藉由縮減基版上的線接合塾數目及嵌入最 大可能之晶;T：至給定之卡内圍，以增加快閃記針的密度；⑺ 更有效地堆疊快閃記’Jt體晶元以增加記憶卡的密度丨以及 (3)儘可能地實質縮減連制基版±的接合線的數目，以 生產良率。 【實施方式】 一本發明係關於-種快閃記憶體，更詳細來說，侧於一種 =度之快閃記憶卡。以下說日關以使該技術領域具有通常知 f者，以實施及使用本發明，且狀專利申請並符合其相關規 ^在此解之實補、—般原理及概係可迅速地被該技術 ::具有通f知識者所瞭解，故本發明之實施態樣並非用來限 之㈣’本發明之侧範圍應根據在此說明之原理及 特徵作最寬廣的解釋。 1310193 包人為—習知的快閃記憶卡1G，此快閃記憶卡10 快pV?二曰，」面11、一快閃記憶控制1112以及一個或多個 接閃卡介面11通扣連接11或是金手指 器12控制位於 透過快閃卡介面丨丨回應來自這些主機裝置的要求。茨且 版I*在’快閃控制11 12和快閃記麵13係嵌在一片美 是已包裝形式:本發;= :稞晶導體元件，且這兩個元件具有不同晶元尺㊁： 取兩=:其;==^^ ^ approach> 式，s體〜元23之習知佈局方 Μ的俯視圖。第3圖為如同ί 2圖2所t相元 乃外而要額外的20個接合墊以容納快閃記憶 ^ 24 1310193 體晶元23的連接。如第3圖所示，基版22係由内部軌跡34、 36及37層壓組合以連接快閃控制器24、快閃記憶體晶元23 及快閃卡介面33。並排方式的製程是相對比較簡單的，然而， ^為基版22上總共需要50個接合線和接合墊，嚴格地限制了 能使用於給定快閃記憶卡21的快閃記憶體和快閃控制器的尺 寸0 、第4圖所示為一個較大快閃記憶體晶元123以及一以堆疊 方式位在基版122的一邊之較小控制器晶元124之習知佈局方 式的俯視圖。第5圖為如同第4圖所示相同佈局的剖面圖。 第4圖所示之堆疊方法中’快閃控制器晶元124被放 置於在基版122上之快閃記憶體晶元123上，導線118、 及138分別連接兩晶元上的接合墊119、127及140至下方其 版的接合墊125、126及135。由於採用多層堆疊的方式1 ，综式的線接合是必須的。基版122 大約3()健合塾以 ^納快閃控制器124的連接，另外需要額外的2()個接合塾以 谷納快閃記憶體晶元123的連接。如第5圖所示，基版12 罐以連接快閃控制器124、快閃記憶體晶元123 由於錯綜式的線接合方式需要基版122更 2二間配接合塾和導線，使得快閃記憶體晶元的尺寸受 J 版需要空間以容納總共5〇個額外的接合線和接合 藝。由於快閃控制器被放置於快閃記憶體晶元上，因此二 f 晶元尺寸上的限制她 是^ 交少的。當秘差不多鱗，且基版村比 較大的控制器晶元將會縮減該快閃的尺寸。 、 本發明兼顧習知並排方式及堆疊方式於快 的尺寸限制’本發日収節省基版上顯線接合的^以及^ 1310193 晶元尺寸且 線接合的複雜度。因此，可容納更多記憶體的較大 可用在並排方式或是堆疊方式。 .本發明之系統和方法可解決上述之問題而達 的.（1)藉由縮減基版上的線接合墊數目，儘可 爭 的快閃記憶體晶元於-給定的幾何空間内，以達=^置匕= δ己憶卡的紐；⑺如有需要’能財效地堆 體曰 元’以增加快閃記憶卡的密度;(3)儘可能地』
之接合線以改善生產良率。 至基版 閱相細地描述本發_舰，請參見以下之詳述並參 第6圖所示為本發明之快閃記憶卡之俯視圖，其 位於基版222上之一較大的快閃記憶體晶元223、二 ί Γ2Γ2以及—快閃控制器晶元224 °第7圖為第6'圖佈 局之nlj面圖。 在本實施例中，如第6圖所示，中介物242位於在基版 222上之快閃記憶體晶元223上，中介物242之 版222，其具有接合墊及預先安排好之連接執跡2料了 其亦可以Hf的、義/聚齡胺製造之單金屬層軟板 (l_metal layer flex drcuit)。中介物242之尺寸恰好足以使得其 接，墊227位於暴露快閃晶元接合墊a6的旁邊。如同第^ 及第7 f所示’中介物242具有接合墊撕及225分別合適地 女排以#近下方快閃憶體晶元223及中央的快閃控制器晶 元224相對應之接合塾226及219，其亦具有相對應之接^塾 240合適地安排以連接在主基版⑽上方且在快閃記憶體晶元 下方之接合墊235。如第7圖所示’這些由中介物242而來的 1310193 導線238疋唯一用以連接到基版222，且經由基版222上之勒 跡234依序連接至快閃卡介面233。 不同於習知方式，本發明幾乎轉移所有從晶元到下方的基 版222的連接線路至快閃卡22!中央的中介物2幻。藉由改g 基版上的接合墊數目由5〇個左右減少到低於1〇個(節省 8〇%) ’以實質地減少基版222所需的接合塾空間，這也使 由於空間供應給接合麵導致無法實現之實質較大快閃記憶 體晶元’在節省基版222的空間後變為可能。再者，藉由;用以 中介物242 ’快閃控制器晶元224不需要直接放置在基版從 上，因此於快閃控制器晶元的尺寸上具有較少的限制 ^堆疊方式有相同的好處。—般而言，本發明改善了快^ 與^際快閃記憶卡尺寸之比例，自大約62%達到 9〇二〇或更，。本發明鱗較大的_記碰晶元，因此 較尚密度的晶元於同樣的快閃記憶卡221設計。 如第6圖及第7圖所示，當快閃控制器晶元224堆疊於 "物242上’亦即位於快閃記憶體晶元223上時，為了不辦加 :介ί242具有位於中間區域之一裁切區22曰8， 224像-個島峡直接坐落在快閃記憶體晶元223 於中介物242上。 个疋位 元，9日圖所示’若需要堆疊更多的快閃記憶體晶 兀叮使用-在曰曰疋上之可彎曲電路中介物3犯。如 =及弟11圖所不’需注意如果有必要的話，此 Γ隹疊的樣子來擴展更多的快閃記憶體= 1310193 及42?、，二斤照本發明使用之兩個快閃記憶體晶元323 Ϊ ^上之曲的電路中介物342以及一位於基 為第8圖之佈局：“日：324之佈局之剖面圖。第9圖所示 324 在=控制器晶元 圖及第11圖所示，假如需要 ^^要=第10 額外的間隔物445是必要的。 1昧門德體曰曰兀523 323 不為+依照本發明應用之三個快閃記憶體晶元 位減Γ，晶元上之可彎曲電路中介物342以及一 圖10 1= 快閃控制器晶元324之佈局剖面圖。第11 圖為第10圖之佈局之側視圖。 理由445之高度小於習知堆疊快閃記憶卡設計， 疋ϋ隔物的高度係為線接合迴圈高度(Wire bonding 如函數，較低的迴圈高度需要較低的間隔物高度。 2 2圖所不，迴圈高度亦為兩個接合塾之間的橫向距離的 函數。 ^第人I2圖所7^，接合塾A及接合墊丑之間的距離為D1 ，接δ墊A及接合墊c之間的距離為D2 153。導線151 別提供給這兩對接合墊，其相對應的迴圈高度分別為 =1 15=及H2 155。較短的橫向距離D1 154需要有較小的迴圈 南度H1 156。如第11圖所示’由於使用中介物342，中介物 342及快閃記憶體晶元523、423及323間相對應的接合墊327 及326能夠物理上地互相鄰近。如第1〇圖所示，中介物342 及快閃控制益晶元324間相對應的接合墊319及318能夠物理 1310193 上地互相鄰近。目此於每個相職的接合狄·邮有最短 的導線’故產生最小的決定性的迴圈高度。較小的間隔物345 及445之整體效能會增加更多快閃記憶體晶元323、似及仍 之堆疊高度的可能性’因此達到快閃記憶卡321的更高密度。 替代性實施例 -替代性實施例佩置鋪H單元於朗赌體晶元的 中間，且在不需要晶对介物之情況下直接使用晶元對晶元 (die-to-die)線接合。 另-替代性實施例係於㈣記憶體上形成晶元再分配芦 (redistribution layer)以代替晶元中介物，唯一不同處在於再| 配層可在快閃a己憶體晶圓上製成，而中介物通常在基版組合 才置入個別的快閃記憶體晶元。 、’ 而不使用晶元上 其他替代性實施例為使用可彎曲的基版， 的可彎曲中介物。 相較於先前技術之優點 不同於習知方式將所有來自快閃控制器及快閃記憔體曰 兀上之接合墊之所有接合線連接至基版，本發明之快閃^憶^ 利用如第6圖所示之晶元中介物縮減接合線的數目。如第7圖 及第8圖所示，中介物位於快閃記憶體晶元上，以接合墊 跡來連接快離制||晶元 '快閃記舰晶元及快閃卡介面 於快閃卡介面訊號被限制在一定的數目（少於1〇)，且通常 閃控y器所控制，因此它們是唯一需要被線接合至基版上之^ 號，這將驚人地縮減基版上的線接合墊數目從約5〇個 個，縮減齡。 縱低於 12 1310193 中人長度將比f知方式更平均地分布在晶元 干，使如用同^知f元尺寸及第6圖之本發明晶元尺寸所 二二物以線接合連接於快閃記憶體晶元及快閃控 制器間可有效地減少基版上之線接合 可能的快閃記紐晶元於,_記㈣ f騎使用竑大 間 使用直接線接合之晶元中介物以節省基版周邊線接合空 第9 ΪΠί之ΐ元中介物以容納快閃控制器晶元，如 第9圖所不，域減了整體的高度並且鱗更高的密度。 晶元堆疊 能夠=可f㈣電路晶元中介物使得快閃記憶體 爭縮Ϊ 合的中介物塾’本發日月亦縮減了線接合長度， ^此項㈣之人士均可在不違穌剌之 情況下，對上述實施例進行修改及變化 ^ 利園 應以下述申請專職_錄之内料依據沐案之權利範圍 【圖式簡單說明】 13 1310193 f1圖所示雜呢憶卡示音圖· 第32 =心=之; 接合基版之俯視圖； ^第4瞭她 圖；第5騎示為f知來自多層晶元之錯綜式接合線之剖面 之晶元中介中央裁切區以容納快閃控制器晶元 之晶巾絲她以容峨卩输制器晶元 葉;=示兩個快閃記憶體晶元設計之剖面圖; 第ίο圖ί為ϋ兩個快閃記憶體晶元設計之側視圖，· ϊ 三個快閃記憶體晶元設計之剖面圖； 以及騎4堆⑥二谢綱記紐晶元設計之側視圖； 函數圖圖所不為迴圈高度與兩個接合塾之間的橫向距離的 【主要元件符號說明】 1〇:快閃記憶卡 12:快閃記憶控制器 18:導線 2〇:導線 22:基版 24:控制器晶元 郎：接合墊 34:軌跡 祁：軌跡 11 :快閃卡介面 13 :快閃記憶控制器 19 =接合墊 21 :快閃記憶卡 23 :快閃記憶體晶元 & =接合墊 =接合墊 35 :接合墊 37 ·軌跡 1310193
38 :導線 119 :接合墊 122 :基版 124 :快閃控制器晶元 126 :接合墊 133 :快閃卡介面 135 :接合墊 151 :導線 153 : D2 155 ： H2 219 :接合墊 222 :基版 224 :快閃控制器晶元 226 :接合墊 228 :裁切區 235 :接合墊 240 :接合墊 243 :連接執跡 318 :接合墊 321 :快閃記憶卡 323 :快閃記憶體晶元 326 :接合墊 342 :中介物 423 :快閃記憶體晶元 523 :快閃記憶體晶元 118 :導線 120 :導線 123 :快閃記憶體 125 :接合墊 127 :接合墊 134 :執跡 138 :導線 152 :導線 154 ： D1 156 ： H1 221 :快閃卡 223 :快閃記憶體晶元 225 :接合墊 227 :接合墊 233 :快閃卡介面 238 :導線 242 :中介物 244 :連接軌跡 319 :接合墊 322 :基版 324 :快閃控制器晶元 327 :接合墊 345 :間隔物 445 :間隔物 15

Claims (1)

131 (M°93i485號專利申請案 申請專利範圍替換本（無劃線版本，2009年2月） 十、申請專利範圍： 1. 一種記憶卡，包含： 一基版’該基版包含複數第一接合墊； 一記憶體晶元，位於該基版上，該記憶體晶元包含複 二接合墊，鄰近該複數第一接合塾； 乐 一控制器晶元’位於該記憶體晶元上，該控制器晶元人 複數第三接合墊；以及 一中介物(interposer)，耦接於該控制器晶元，且位於該 憶體:曰曰元上，該中介物包含複數第四接合塾，鄰近該複 一、第二及第三接合墊，以使得線接合於其間其中該中 之該複數第四接合墊使得線接合轉移至該中介物，以 物線接合至該基版最少化。 2. 如請求項1所述之記憶卡，其中該中介物圍繞該控制器晶元。 3. 如請求項2所述之記憶卡，包含： 一苐一5己憶體晶元，耗接至該中介物；以及 一間隔物(spacer)，用以隔開該記憶體晶元與該第二記情 體晶元。 4.如請求項！所述之記憶卡，其中該中介物包含至少一連接執跡 (connecting trace) ° 5. 如請求項2所述之記憶+ ’其中該中介物包含位於一中間區域 之一裁切區(cutout)，該裁切區足以容納該控制器晶元。 如請求項1所述之記憶卡，其中該中介物包含 曲部係可彎曲位在晶元部件上。 1以弓 16 6. 1310193 所述之記憶卡’其中該控制器晶元具有-高度，該 同度係根據圍繞該控制器晶元之該中介物以達成Lr匕 之卡，其中該間隔物之高度係為該中介物 ~5己‘u體晶元間之一打線距離之函數。 9. —種快閃記憶卡，包含： 一基版，該基版包含複數第一 體晶=;=憶=士 =，該第-快_ -快閃ϊίίΓ 鄰近該複數第一接合墊； 閃押綱曰1控曰曰70 ’位於該第一快閃記憶體晶元上，該快 内控制Wtl包含複數第三接合塾； —彎曲中介物，耦接該第一快閃記情俨a 包含複數第四接合塾，鄰近勒曰一曰兀上，該中介物 以使得魂接人私甘# 5X 弟、弟一及第三接合墊， 最3線接5於其間’其中該彎曲中介物使得線接合至該基版 至少一第二快閃記憶體晶元，其中曰一 係輕接於該-曲中介物；以及 H夬門5己隐體曰曰兀 一間隔物，用以隔開該第一快閃記情體晶元 記憶體晶元。 體曰曰兀與該弟一快閃 彎曲中介物包含至少一 10·如請求項9所述之快閃記憶卡，其中該 連接執跡。 〃 17
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