CN1909222A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN1909222A
CN1909222A CNA2006101009992A CN200610100999A CN1909222A CN 1909222 A CN1909222 A CN 1909222A CN A2006101009992 A CNA2006101009992 A CN A2006101009992A CN 200610100999 A CN200610100999 A CN 200610100999A CN 1909222 A CN1909222 A CN 1909222A
Authority
CN
China
Prior art keywords
semiconductor device
straight line
semiconductor substrate
electrical connection
resin projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101009992A
Other languages
English (en)
Other versions
CN100452374C (zh
Inventor
田中秀一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN1909222A publication Critical patent/CN1909222A/zh
Application granted granted Critical
Publication of CN100452374C publication Critical patent/CN100452374C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02375Top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02377Fan-in arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

提供一种安装性良好的半导体装置。半导体装置包括:形成有电极(14)的半导体基板(10);形成在半导体基板(10)上且沿着一条直线(100)排列的多个树脂突起(20);形成在树脂突起(20)上且与电极(14)电连接的多个电连接部(30)。多个树脂突起(20)分别呈向与直线(100)交叉的方向延伸的形状。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
已知在布线基板上安装有半导体装置(例如参照特开平2-272737号公报)的类型的电子模块。为了制造可靠性高的电子模块,将布线基板的布线图案和半导体装置的电连接部电连接是很重要的。
发明内容
本发明的目的在于,提供一种可靠性高的半导体装置。
(1)本发明的半导体装置,包括:半导体基板,其形成有多个电极;多个树脂突起,其形成在所述半导体基板上且沿一条直线排列而构成;和多个电连接部,其形成在所述树脂突起上且与所述电极电连接,所述多个树脂突起具有向与所述直线交叉的方向延伸的形状。根据本发明,能够提供安装性良好的半导体装置。
(2)在该半导体装置中,所述树脂突起也可以具有按照与所述直线倾斜交叉的方式延伸的形状。
(3)在该半导体装置中,所述树脂突起也可以具有按照与所述直线正交的方式延伸的形状。
(4)在该半导体装置中,所述半导体基板也可以为半导体芯片,所述直线也可以沿着所述半导体基板的形成有所述电极的面的一个边延伸。
(5)在该半导体装置中,所述半导体基板的形成有所述电极的面也可以呈长方形,所述直线也可以沿着所述长方形的长边延伸。
(6)在该半导体装置中,也可以在每个所述树脂突起上形成有多个所述电连接部。
附图说明
图1(A)~图1(C)是用于说明适用本发明的实施方式的半导体装置的图;
图2(A)~图2(C)是用于说明适用本发明的实施方式的半导体装置的图;
图3是用于说明适用本发明的实施方式的半导体装置的图;
图4是用于说明适用本发明的实施方式的变形例的半导体装置的图;
图5是用于说明适用本发明的实施方式的变形例的半导体装置的图。
1-半导体装置;10-半导体基板;12-集成电路;14-电极;16-钝化膜;20-树脂突起;21-树脂突起;22-树脂突起;30-电连接部;32-布线;40-布线基板;42-基底基板;44-布线图案;45-电连接部;50-粘接剂;52-粘接层;100-直线。
具体实施方式
以下,参照附图说明适用本发明的实施方式。但是,本发明并不限定于以下的实施方式。另外,本发明包括将以下的实施方式以及变形例自由组合而得到的装置。
图1(A)~图3是用于说明适用本发明的实施方式的半导体装置的图。在此,图1(A)是适用本发明的实施方式的半导体装置1的俯视图。但是,在图1(A)中为了说明而省略了电极14以及电连接部30(布线32)。另外,图1(B)是图1(A)的一部分放大图,图1(C)是图1(B)的IC-IC线剖面图。
本实施方式的半导体装置包括半导体基板10。半导体基板10例如也可以是硅基板。半导体基板10如图1(A)所示也可以呈芯片状。即,半导体基板10也可以是半导体芯片。或者,半导体基板10也可以呈晶片状(未图示)。此时,半导体基板10也可以包括成为多个半导体芯片(半导体装置)的区域。在半导体基板10上也可以形成集成电路12(参照图1(C))。集成电路12的构成并不特别限定,但是也可以包含晶体管等有源元件或电阻、线圈、电容器等无源元件。在半导体基板10呈芯片状的情况下,半导体基板10的形成有集成电路12的面(有源面)呈长方形(参照图1(A)。但是,半导体基板10的有源面也可以呈正方形(未图示)。
在半导体基板10上,如图1(B)以及图1(C)所示形成有多个电极14。电极14例如也可以形成在半导体基板10的形成有集成电路12的面(有缘面)。电极14也可以沿着半导体基板10的一个边而被排列。电极14也可以沿着半导体基板10的多个边而被排列。在半导体基板10的有源面呈长方形的情况下,电极14也可以沿着两个长边(仅)而被排列。但是,半导体装置也可以进一步包括沿着半导体基板10的有源面的短边而被配列的电极(未图示)。电极14也可以沿着半导体基板10的一个边排列成一列。但是,电极14也可以沿着一个边排列成多个列(未图示)。
电极14也可以与集成电路12电连接。或者也可以包括未与集成电路12电连接的导电体,并称作电极14。电极14也可以是半导体基板的内部布线(电极)的一部分。电极14也可以由铝或铜等金属形成。
半导体基板10如图1(C)所示也可以具有钝化膜16。钝化膜16也可以形成为使电极14露出。钝化膜16也可以具有使电极14露出的开口部。钝化膜例如也可以是SiO2和SiN等无机绝缘膜。或者,钝化膜16也可以是聚酰亚胺树脂等有机绝缘膜。
本实施方式的半导体装置如图1(A)~图1(C)所示,包括多个树脂突起20。树脂突起20被形成在半导体基板10上。多个树脂突起20沿着一条直线100而被排列。即,本实施方式的半导体装置也可以包括沿着一条直线100而被排列的、可分成组的多个树脂突起20。此时,树脂突起20也可以设置成能分成一个或多个组。另外,直线100也可以是沿着半导体基板(半导体芯片)的外形的一个边延伸的直线。半导体基板10的形成有电极14的面的外形呈长方形的情况下,直线100也可以是沿着该长边延伸的直线。即,多个树脂突起20也可以沿着半导体芯片的长边而被配置。此外,多个树脂突起20也可以隔开间隔而被排列。
树脂突起20分别呈向与直线100交叉的方向延伸的形状。树脂突起20如图1(A)以及图1(B)所示,也可以呈以与直线100倾斜地交叉的方式延伸的形状。树脂突起20例如也可以呈从半导体基板10(半导体芯片)的中心沿着以放射状延伸的直线而延伸的形状。
树脂突起20的材料并不特别限定,即也可以使用已公知的任意的材料。例如,树脂突起20也可以由聚酰亚胺树脂、硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯并环丁烯(BCB:benzocyclobutene)、聚苯并恶唑(PBO:polybenzoxazole)、酚醛树脂等树脂形成。
本实施方式的半导体装置包括多个电连接部30。电连接部30被形成在树脂突起20上。此时,在一个树脂突起20上也可以形成多个电连接部30(参照图1(B))。或者,在一个树脂突起20上也可以仅形成一个电连接部30(未图示)。电连接部30也可以分别与电极14电连接。例如,电连接部30也可以指以从电极14引出至树脂突起20上的方式形成的布线32的一部分(与树脂突起20重叠的区域)。此时,电连接部30也可以指在布线32中作为外部端子来利用的部分。此外,布线32也可以在树脂突起20的两侧以与半导体基板10(钝化膜16)接触的方式形成。另外,布线32也可以向与直线100交叉的方向延伸。
布线32(电连接部30)的结构以及材料并不特别限定。例如,布线32也可以由单层形成。或者,布线32也可以由多个层形成。此时,布线32也可以包括由钛钨形成的第一层和由金形成的第二层(未图示)。
本实施方式的半导体装置1也可以呈上述的构成。根据半导体装置1,能够提供安装性良好的半导体装置。即,根据半导体装置1,能够有效地制造可靠性高的电子模块1000(参照图3)。以下对其效果进行说明。
将半导体装置1安装于布线基板40的方法并不特别限定,但是参照图2(A)~图2(C)对其一例进行说明。首先,对布线基板40进行说明。布线基板40也可以包括基底基板42和布线图案44。基底基板42的材料并不特别限定,也可以是有机系列或无机系列的任意材料,也可以是由这些复合结构构成的材料。作为基底基板42也可以利用由无机系列的材料形成的基板。此时,基底基板42也可以是陶瓷基板或玻璃基板。在基底基板42为玻璃基板的情况下,布线基板40也可以是电光学面板(液晶面板/电致发光面板等)的一部分。布线图案44也可以由ITO(Indium TinOxide)、Cr、Al等金属膜、金属化合物膜或者这些复合膜形成。此时,布线图案44也可以与驱动液晶的电极(扫描电极、信号电极、对置电极等)电连接。或者,基底基板42也可以是由聚对苯二甲酸乙酯(PET)构成的基板或薄膜。或者,作为基底基板42也可以使用聚酰亚胺树脂构成的挠性基板。作为挠性基板也可以使用由FPC(Flexible Printed Circuit)或TAB(Tape Automated Bonding)所使用的布带(tape)。此时,布线图案44也可以层叠例如铜(Cu)、铬(Cr)、钛(Ti)、镍(Ni)、钛钨(Ti-W)中的任一个而形成。并且,布线图案44包括电连接部45。电连接部45是在布线图案44中利用于与其他部件的电连接的部分。另外,布线图案44也可以形成为,其一部分通过基底基板42的内侧(未图示)。
以下,说明在布线基板40上搭载半导体装置1的工序。首先,如图2(A)所示,将半导体装置1配置在布线基板40上,并进行定位,使得半导体装置1的电连接部30(树脂突起20)与布线基板40的布线图案44(电连接部45)对置。此时,在半导体装置1和布线基板40之间也可以设置粘接剂50。粘接剂50如图2(A)所示,也可以设置在布线基板40上。粘接剂50例如也可以利用薄膜状的粘接剂。粘接剂50也可以是绝缘性的粘接剂。粘接剂50也可以是树脂系列粘接剂。其后,如图2(B)所示,对半导体装置1和布线基板40进行按压。在本工序中,也可以通过树脂突起20使粘接剂50流动(参照图2(B))。并且,使电连接部30与布线图案44(电连接部45)接触(参照图2(C))。本工序也可以在加热环境下进行。由此,能够提高粘接剂50的流动性。此外,在本工序中,也可以通过半导体基板10和布线基板40来压碎树脂突起20,使树脂突起20弹性变形(参照图2(C))。由此,由于通过树脂突起20的弹性力来按压电连接部30和电连接部45(布线图案44),因此能够制造电连接可靠性高的电子模块。并且,如图(C)所示,也可以使粘接剂50硬化而形成粘接层52。也可以通过粘接层52来维持半导体基板10和布线基板40之间的间隔。即,也可以通过粘接层52来维持树脂突起20弹性变形后的状态。例如,在将树脂突起20压碎后的状态下使粘接剂50硬化,从而能够维持树脂突起20弹性变形后的状态。
通过上述的工序,也可以将半导体装置1安装在布线基板40上。进一步,经过检查工序,也可以制造图3所示的电子模块1000。电子模块1000也可以是显示设备。显示设备例如是液晶显示设备或EL(ElecticalLuminescence)显示设备。并且,半导体装置1(半导体基板10)也可以是控制显示设备的驱动IC。
如上说明,在将半导体装置1安装在布线基板40上的工序中,预先,在半导体装置1和布线基板40之间设置粘接剂50的情况下,通过树脂突起20(电连接部30)使粘接剂50流动。此时,为了将半导体装置1的电连接部30和布线图案44(电连接部45)电连接,而在电连接部30和电连接部45之间以粘接剂50不残留的方式进行半导体装置1的安装工序是很重要。换言之,在布线基板40上安装半导体装置1的工序中,若从电连接部30和电连接部45之间开始能够有效地排出粘接剂50,则能够有效地制造可靠性高的电子模块。即,若在半导体装置1和布线基板40之间有效地使粘接剂50流动,则能够有效地制造可靠性高的电子模块。
但是,如上说明,半导体装置1包括沿着一个直线100而被排列的多个树脂突起20。并且,树脂突起20呈向直线100交叉的方向延伸的形状。因此,根据半导体装置1,容易地使粘接剂50向与直线100交叉的方向流动。详细而言,根据半导体装置1,粘接剂50可以在相邻的两个树脂突起20之间流动。即,粘接剂50,可通过树脂突起20之间向与直线100交叉的方向流动。另外,树脂突起20呈向直线100交叉的方向延伸的形状。因此,在粘接剂50向与直线100交叉的方向流动的情况下,粘接剂50沿着树脂突起20流动。即,通过树脂突起20来控制粘接剂50的流动方向。由此,根据半导体装置1,能够使安装时的粘接剂50的流动电阻变小。因此,根据半导体装置1,在安装时,粘接剂50难以在树脂突起20和布线基板40(电连接部45)之间残留,能够可靠地使电连接部30和电连接部45电连接。另外,由于粘接剂50的流动电阻变小,从而能够有效地安装半导体装置1。
即,根据本实施方式的半导体装置,能够提供可有效地制造可靠性高的电子模块的半导体装置。
图4以及图5是用于说明适用本发明的实施方式的变形例的半导体装置的图。
在图4所示的例中,树脂突起21呈以与直线100正交的方式延伸的形状。另外,在图4所示的例中,电极14也可以并排在与直线100交叉的方向上。换言之,电极14也可以配置成,向与直线100交叉的方向延伸且可分成多个组。此时,该组也可以通过与树脂突起21平行排列的电极14来构成。
在图5所示的例中,树脂突起22呈向其中心与半导体基板10的对角线的交点一致的假设的圆或椭圆(未图示)的接线方向延伸的形状。
根据这些半导体装置,也能得到与半导体装置1相同的效果。因此,能够有效地制造可靠性高的电子模块。
此外,本发明并不限定于上述的实施方式,可以进行各种变形。例如,本发明包括与实施方式中所说明的构成实际上相同的构成(例如,功能、方法以及结果相同的构成、或者目的以及效果相同的构成)。另外,本发明包括置换实施方式中所说明的构成的无本质性的部分的构成。另外,本发明包括:得到与实施方式中所说明的构成相同的作用效果的构成、或实现相同的目的的构成。另外,本发明包括对实施方式中所说明的构成附加了公知技术的构成。

Claims (6)

1.一种半导体装置,其特征在于,包括:
半导体基板,其形成有多个电极;
多个树脂突起,其形成在所述半导体基板上,且沿一条直线排列;和
多个电连接部,其形成在所述树脂突起上,且与所述电极电连接,
所述多个树脂突起呈向与所述直线交叉的方向延伸的形状。
2、根据权利要求1所述的半导体装置,其特征在于,
所述树脂突起具有按照与所述直线倾斜交叉的方式延伸的形状。
3、根据权利要求1所述的半导体装置,其特征在于,
所述树脂突起具有按照与所述直线正交的方式延伸的形状。
4、根据权利要求1~3中任意一项所述的半导体装置,其特征在于,
所述半导体基板为半导体芯片,
所述直线沿着所述半导体基板的形成有所述电极的面的一个边延伸。
5、根据权利要求4所述的半导体装置,其特征在于,
所述半导体基板的形成有所述电极的面呈长方形,
所述直线沿着所述长方形的长边延伸。
6、根据权利要求1~5中任意一项所述的半导体装置,其特征在于,
在每个所述树脂突起上分别形成有多个所述电连接部。
CNB2006101009992A 2005-08-03 2006-08-01 半导体装置 Expired - Fee Related CN100452374C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005225452 2005-08-03
JP2005225452A JP4273347B2 (ja) 2005-08-03 2005-08-03 半導体装置

Publications (2)

Publication Number Publication Date
CN1909222A true CN1909222A (zh) 2007-02-07
CN100452374C CN100452374C (zh) 2009-01-14

Family

ID=37106460

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101009992A Expired - Fee Related CN100452374C (zh) 2005-08-03 2006-08-01 半导体装置

Country Status (5)

Country Link
US (1) US7576424B2 (zh)
EP (1) EP1750304A2 (zh)
JP (1) JP4273347B2 (zh)
CN (1) CN100452374C (zh)
TW (1) TWI309867B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105984218A (zh) * 2015-03-16 2016-10-05 精工爱普生株式会社 电子装置
CN107257736A (zh) * 2015-03-04 2017-10-17 精工爱普生株式会社 Mems装置、记录头以及液体喷射装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4353289B2 (ja) 2007-08-20 2009-10-28 セイコーエプソン株式会社 電子デバイス及び電子機器

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02272737A (ja) * 1989-04-14 1990-11-07 Citizen Watch Co Ltd 半導体の突起電極構造及び突起電極形成方法
US5144823A (en) * 1991-03-05 1992-09-08 Robert Gene Smith Bend angle indicator
JPH05144823A (ja) 1991-11-15 1993-06-11 Tanaka Kikinzoku Kogyo Kk 高密度バンプ形成方法
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
JP3336859B2 (ja) 1996-05-29 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
EP1271640A3 (en) 1996-07-12 2003-07-16 Fujitsu Limited Mold for manufacturing semiconductor device
TW324847B (en) * 1996-12-13 1998-01-11 Ind Tech Res Inst The structure of composite bump
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
JPH10321631A (ja) * 1997-05-19 1998-12-04 Oki Electric Ind Co Ltd 半導体装置およびその製造方法
JP2001110831A (ja) * 1999-10-07 2001-04-20 Seiko Epson Corp 外部接続突起およびその形成方法、半導体チップ、回路基板ならびに電子機器
TW478089B (en) * 1999-10-29 2002-03-01 Hitachi Ltd Semiconductor device and the manufacturing method thereof
JP2001127256A (ja) * 1999-10-29 2001-05-11 Fuji Xerox Co Ltd 半導体装置
US6710446B2 (en) * 1999-12-30 2004-03-23 Renesas Technology Corporation Semiconductor device comprising stress relaxation layers and method for manufacturing the same
JP4465891B2 (ja) 2001-02-07 2010-05-26 パナソニック株式会社 半導体装置
US6759311B2 (en) * 2001-10-31 2004-07-06 Formfactor, Inc. Fan out of interconnect elements attached to semiconductor wafer
JP3969295B2 (ja) * 2002-12-02 2007-09-05 セイコーエプソン株式会社 半導体装置及びその製造方法と回路基板及び電気光学装置、並びに電子機器
JP2005005306A (ja) * 2003-06-09 2005-01-06 Seiko Epson Corp 半導体装置、半導体モジュール、電子デバイス、電子機器および半導体モジュールの製造方法
JP3938128B2 (ja) 2003-09-30 2007-06-27 セイコーエプソン株式会社 半導体装置とその製造方法、回路基板、電気光学装置、及び電子機器
JP4218622B2 (ja) 2003-10-09 2009-02-04 セイコーエプソン株式会社 半導体装置の製造方法
JP3994989B2 (ja) * 2004-06-14 2007-10-24 セイコーエプソン株式会社 半導体装置、回路基板、電気光学装置および電子機器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107257736A (zh) * 2015-03-04 2017-10-17 精工爱普生株式会社 Mems装置、记录头以及液体喷射装置
CN105984218A (zh) * 2015-03-16 2016-10-05 精工爱普生株式会社 电子装置

Also Published As

Publication number Publication date
US20070029672A1 (en) 2007-02-08
CN100452374C (zh) 2009-01-14
TW200721334A (en) 2007-06-01
US7576424B2 (en) 2009-08-18
JP4273347B2 (ja) 2009-06-03
JP2007042868A (ja) 2007-02-15
TWI309867B (en) 2009-05-11
EP1750304A2 (en) 2007-02-07

Similar Documents

Publication Publication Date Title
US7851912B2 (en) Semiconductor device
US7728424B2 (en) Semiconductor device and method of manufacturing the same
US7582967B2 (en) Semiconductor device, electronic module, and method of manufacturing electronic module
US8138612B2 (en) Semiconductor device
CN1893057A (zh) 半导体装置及其制造方法
US20070057371A1 (en) Semiconductor device
CN1909222A (zh) 半导体装置
US8115309B2 (en) Semiconductor device
US7144758B2 (en) Manufacturing method of semiconductor device, including differently spaced bump electrode arrays
CN1901149A (zh) 半导体装置及其制造方法
KR100755354B1 (ko) 반도체 장치
KR100759309B1 (ko) 반도체 장치
KR100773408B1 (ko) 반도체 장치
JP4720992B2 (ja) 半導体装置
CN1551341A (zh) 半导体装置、电子器件、电子机器及半导体装置的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090114

Termination date: 20130801